| Package Code | K6499MK+1B |
| Outline Number | 21-0765 |
| Land Pattern Number | 90-0605 |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opSC1905A-00A00
data-opSC1905A-00A00E
+1.8V DC Supply Voltage for Digital Circuits.Do Not Connect. Reserved for internal use.Do Not Connect. Reserved for internal use.+1.8V DC Supply Voltage for Analog Circuits.+3.3V DC Supply Voltage for Analog Circuits.Ground for Shield of RF Signal.RF Output Signal, Differential Positive Output.RF Output Signal, Differential Negative OutputDo Not Connect. Reserved for internal use.Do Not Connect. Reserved for internal use.Bandgap Resistor.RF Input Signal, Differential Positive Input.RF Input Signal, Differential Negative Input.Do Not Connect. Reserved for internal use.Do Not Connect. Reserved for internal use.Do Not Connect. Reserved for internal use.Do Not Connect. Reserved for internal use.RF Feedback Signal, Differential Positive Input.RF Feedback Signal, Differential Negative Input.Dedicated External Filter Capacitor #0.Dedicated External Filter Capacitor #0.Dedicated External Filter Capacitor #1.Dedicated External Filter Capacitor #1.Dedicated External Filter Capacitor #2.Dedicated External Filter Capacitor #2.Dedicated External Filter Capacitor #3.Dedicated External Filter Capacitor #3.Crystal Input. For standard internal clock, connect crystal or ceramic resonator from XTALI to XTALO. May alternatively be driven by an external clock.Crystal Output. Excitation driver for crystal or ceramic resonator.Active-Low Reset Input. Has internal pullup to DVDD33.Watch Dog Timer Enable. WDTENB enabled when high. Has internal pullup to DVDD33. See applications schematic for further details.SPI Clock. Has internal pulldown to GND.SPI Slave Select Enabled "Low". Has internal pullup to DVDD33.SPI Slave Data Input to RFPAL. Has internal pulldown to GND.SPI Slave Data Output from RFPAL. Tri-state. DVDD33 logic.Digital General Purpose Input 1. Has internal pullup to DVDD33. See Firmware Release Notes for further details.General Purpose Status Output, as Defined in Firmware Release Notes. Open-drain output with internal pullup to DVDD33.+3.3V DC Supply Voltage for Digital Circuits.Load Enable. Required for FW upgrades. Has internal pulldown to GND. See applications schematic for further details.Do Not Connect. Reserved for internal use. Has internal pulldown to GND.Do Not Connect. Reserved for internal use. Has internal pulldown to GND.Digital General Purpose Input 0. Do not connect. Reserved for future use. Has internal pulldown to GND. See applications schematic for further details.Common Ground for Entire Integrated Circuit. Also provides path for thermal dissipation.