Application Circuits
Typical Application Circuits
Typical Use Case with PCM Mode Record and Playback
DIGITAL MICROPHONE INPUT 1
DIGITAL
MICROPHONE
INPUT
1
DIGITAL MICROPHONE INPUT 2
DIGITAL
MICROPHONE
INPUT
2
DIGITAL MICROPHONE INPUT 3
DIGITAL
MICROPHONE
INPUT
3
MAX98050
MAX98050
Digital Core Input Power Supply. The device transitions to hardware shutdown, and all registers are reset to their PoR values when this drops below its UVLO threshold. Bypass to DGND with at least a 1µF capacitor.
DVDD
DVDD
Digital Interface Logic Level Power Supply. Selects the reference logic voltage level for the PCM and I2C digital interfaces. Bypass to DGND with at least a 0.1µF capacitor.
DVDDIO
DVDDIO
Device Quiet Ground. Ground reference for all sensitive and core analog blocks.
GND
GND
Device Digital Ground. Ground reference for the amplifier class-D switching stage, the digital interfaces, and the digital core.
DGND
DGND
Serial Interface Address Select. This connection selects from four possible I2C slave addresses.
ADDR
ADDR
Headphone Amplifier Positive Output
OUTP
OUTP
Headphone Amplifier Negative Output
OUTN
OUTN
PCM Data Output Bus. Internally pulled down to DGND (RPD) when disabled.
DOUT
DOUT
PCM Data Input. Internally pulled down to DGND (RPD).
DIN
DIN
PCM Frame Clock Input. Internally pulled down to DGND (RPD).
LRCLK
LRCLK
PCM Bit Clock Input. Internally pulled down to DGND (RPD).
BCLK
BCLK
Analog Microphone 1 Negative Input
INN1
INN1
Hardware Interrupt Output. For the full signal swing in open-drain mode, connect an external pullup resistor (typically at least 1.5kΩ) to DVDDIO. A software enabled internal 100kΩ pullup resistor is also available. A pullup resistor is not needed in push-pull mode.
IRQ
IRQ
Device Hardware Enable Input. When pulled low, the device is placed into and held in hardware shutdown. When pulled high to DVDDIO, the device can exit hardware shutdown if all supplies are above their UVLO thresholds.
HW_EN
HW_EN
Analog Low Supply. This is the input supply for low voltage analog and the amplifier in class-AB mode. The device transitions to hardware shutdown, and all registers are reset to their PoR values when this drops below its UVLO threshold. This can be connected directly to AVDD3, and both supplies share a single bypass capacitor to DGND of at least 1µF. If not connected to AVDD3, then bypass it separately to GND.
AVDD2
AVDD2
Analog High Supply. This is the input supply for the high voltage analog, the amplifier high-swing class-D mode, and the analog 1.6V linear regulator. The device transitions to hardware shutdown, and all registers are reset to their PoR values when this drops below its UVLO threshold. Bypass to GND with at least a 1µF capacitor.
AVDD1
AVDD1
Analog Microphone 3 Negative Input
INN3
INN3
Analog Microphone 2 Negative Input
INN2
INN2
Analog Microphone 1 Positive Input
INP1
INP1
Analog Microphone 3 Positive Input
INP3
INP3
Analog Microphone 2 Positive Input
INP2
INP2
I2C-Compatible Serial-Clock Input. For the full signal swing, connect an external pullup resistor (typically 1.5kΩ for FM+ clock rate support) to DVDDIO.
SCL
SCL
I2C-Compatible Serial-Data Input/Output. For the full signal swing, connect an external pullup resistor (typically 1.5kΩ for FM+ clock rate support) to DVDDIO.
SDA
SDA
0.1µF
0.1µF
1µF
1µF
1.8V OR 1.2V
1.8V OR 1.2V
1µF
1µF
PCM AUDIO BUS (I2S / TDM)
PCM
AUDIO
BUS
(
I
2
S
/ TDM)
1.5kΩ
1.5kΩ
I2C CONTROL BUS
I
2
C CONTROL
BUS
HARDWARE CONTROLS
HARDWARE
CONTROLS
HEADPHONE OUTPUT
HEADPHONE
OUTPUT
ANALOG MICROPHONE INPUT 1
ANALOG
MICROPHONE
INPUT
1
(GROUND PLANE)
(GROUND PLANE)
Microphone Bias Input Supply. Provides the input to the microphone bias linear regulator. Connect to a supply exceeding the minimum dropout voltage for the selected output microphone bias level. Can be directly connected to a single cell battery. Connect to GND or leave unconnected if the microphone bias is not used (always disabled). If microphone bias is used, bypass to GND with a 1µF capacitor.
MBVDD
MBVDD
1µF
1µF
Gated Microphone Bias Output 2. This output provides the selected microphone bias output voltage when both microphone bias is enabled and this output is enabled. Leave unconnected if this microphone bias output is never enabled, otherwise bypass to GND with at least a 0.1µF capacitor (may be shared if the analog microphone requires bypass as well).
MICBIAS2
MICBIAS2
ANALOG MICROPHONE BIAS OUTPUTS
ANALOG
MICROPHONE
BIAS OUTPUTS
1.4V to 4.8V
1.4V to 4.8V
Gated Microphone Bias Output 3. This output provides the selected microphone bias output voltage when both microphone bias is enabled and this output is enabled. Leave unconnected if this microphone bias output is never enabled, otherwise bypass to GND with at least a 0.1µF capacitor (may be shared if the analog microphone requires bypass as well).
MICBIAS3
MICBIAS3
1.8V
1.8V
1µF
1µF
Amplifier Low Supply. This is the amplifier low power class-D mode supply. The device transitions to hardware shutdown, and all registers are reset to their PoR values when this drops below its UVLO threshold. This can be connected directly to AVDD2, and both supplies share a single bypass capacitor to DGND of at least 1µF. If not connected to AVDD2, then bypass it separately to DGND.
AVDD3
AVDD3
1µF
1µF
Analog High Supply Linear Regulator Output. This is the output of the analog 1.6V linear regulator. Bypass to GND with a 1µF capacitor. This should never be connected to an external load.
AVDD1_REG
AVDD1_REG
1.2V
1.2V
Internally Connected. Not used for normal device operation. Connect to GND externally.
I.C.
I.C.
1.2V
1.2V
0.1µF
0.1µF
ANALOG MICROPHONE INPUT 2
ANALOG
MICROPHONE
INPUT
2
ANALOG MICROPHONE INPUT 3
ANALOG
MICROPHONE
INPUT
3
Digital Microphone Interface 1 Data Input
DMD1
DMD1
Digital Microphone Interface 3 Data Input
DMD3
DMD3
Digital Microphone Interface 2 Data Input
DMD2
DMD2
Digital Microphone Interface 1 Clock Output
DMC1
DMC1
Digital Microphone Interface 3 Clock Output
DMC3
DMC3
Digital Microphone Interface 2 Clock Output
DMC2
DMC2
INTERRUPT
INTERRUPT
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
2.2µF
Direct Microphone Bias Output 1 and Bypass Connection. Whenever microphone bias is enabled, this output always provides the selected microphone bias output voltage (cannot be gated). Leave unconnected if microphone bias is never enabled, otherwise always bypass to GND with a 2.2µF capacitor.
MICBIAS1
MICBIAS1
0.1µF
0.1µF
