Pin Specifications

Pin Configuration MAX98050 WLP Package
PIN NAME FUNCTION REF SUPPLY TYPE
Pin Description
D6 AVDD1 Analog High Supply. This is the input supply for the high voltage analog, the amplifier high-swing class-D mode, and the analog 1.6V linear regulator. The device transitions to hardware shutdown, and all registers are reset to their PoR values when this drops below its UVLO threshold. Bypass to GND with at least a 1µF capacitor. Power
F5 AVDD2 Analog Low Supply. This is the input supply for low voltage analog and the amplifier in class-AB mode. The device transitions to hardware shutdown, and all registers are reset to their PoR values when this drops below its UVLO threshold. This can be connected directly to AVDD3, and both supplies share a single bypass capacitor to DGND of at least 1µF. If not connected to AVDD3, then bypass it separately to GND. Power
E5 AVDD3 Amplifier Low Supply. This is the amplifier low power class-D mode supply. The device transitions to hardware shutdown, and all registers are reset to their PoR values when this drops below its UVLO threshold. This can be connected directly to AVDD2, and both supplies share a single bypass capacitor to DGND of at least 1µF. If not connected to AVDD2, then bypass it separately to DGND. Power
F2 DVDD Digital Core Input Power Supply. The device transitions to hardware shutdown, and all registers are reset to their PoR values when this drops below its UVLO threshold. Bypass to DGND with at least a 1µF capacitor. Power
F3 DVDDIO Digital Interface Logic Level Power Supply. Selects the reference logic voltage level for the PCM and I2C digital interfaces. Bypass to DGND with at least a 0.1µF capacitor. Power
A6 MBVDD Microphone Bias Input Supply. Provides the input to the microphone bias linear regulator. Connect to a supply exceeding the minimum dropout voltage for the selected output microphone bias level. Can be directly connected to a single cell battery. Connect to GND or leave unconnected if the microphone bias is not used (always disabled). If microphone bias is used, bypass to GND with a 1µF capacitor. Power
C6 AVDD1_REG Analog High Supply Linear Regulator Output. This is the output of the analog 1.6V linear regulator. Bypass to GND with a 1µF capacitor. This should never be connected to an external load. AVDD1 Power
D5 MICBIAS1 Direct Microphone Bias Output 1 and Bypass Connection. Whenever microphone bias is enabled, this output always provides the selected microphone bias output voltage (cannot be gated). Leave unconnected if microphone bias is never enabled, otherwise always bypass to GND with a 2.2µF capacitor. MBVDD
D4 MICBIAS2 Gated Microphone Bias Output 2. This output provides the selected microphone bias output voltage when both microphone bias is enabled and this output is enabled. Leave unconnected if this microphone bias output is never enabled, otherwise bypass to GND with at least a 0.1µF capacitor (may be shared if the analog microphone requires bypass as well). MBVDD
E4 MICBIAS3 Gated Microphone Bias Output 3. This output provides the selected microphone bias output voltage when both microphone bias is enabled and this output is enabled. Leave unconnected if this microphone bias output is never enabled, otherwise bypass to GND with at least a 0.1µF capacitor (may be shared if the analog microphone requires bypass as well). MBVDD
B6 GND Device Quiet Ground. Ground reference for all sensitive and core analog blocks. Power
F4 DGND Device Digital Ground. Ground reference for the amplifier class-D switching stage, the digital interfaces, and the digital core. Power
E1 SCL I2C-Compatible Serial-Clock Input. For the full signal swing, connect an external pullup resistor (typically 1.5kΩ for FM+ clock rate support) to DVDDIO. DVDDIO
F1 SDA I2C-Compatible Serial-Data Input/Output. For the full signal swing, connect an external pullup resistor (typically 1.5kΩ for FM+ clock rate support) to DVDDIO. DVDDIO
D2 IRQ Hardware Interrupt Output. For the full signal swing in open-drain mode, connect an external pullup resistor (typically at least 1.5kΩ) to DVDDIO. A software enabled internal 100kΩ pullup resistor is also available. A pullup resistor is not needed in push-pull mode. DVDDIO
E2 ADDR Serial Interface Address Select. This connection selects from four possible I2C slave addresses. DVDDIO
E3 HW_EN Device Hardware Enable Input. When pulled low, the device is placed into and held in hardware shutdown. When pulled high to DVDDIO, the device can exit hardware shutdown if all supplies are above their UVLO thresholds. DVDDIO
D1 BCLK PCM Bit Clock Input. Internally pulled down to DGND (RPD). DVDDIO
C1 LRCLK PCM Frame Clock Input. Internally pulled down to DGND (RPD). DVDDIO
B1 DIN PCM Data Input. Internally pulled down to DGND (RPD). DVDDIO
A1 DOUT PCM Data Output Bus. Internally pulled down to DGND (RPD) when disabled. DVDDIO
E6 OUTP Headphone Amplifier Positive Output AVDD1
F6 OUTN Headphone Amplifier Negative Output AVDD1
C4 INP1 Analog Microphone 1 Positive Input AVDD1_REG
C5 INN1 Analog Microphone 1 Negative Input AVDD1_REG
B4 INP2 Analog Microphone 2 Positive Input AVDD1_REG
B5 INN2 Analog Microphone 2 Negative Input AVDD1_REG
A4 INP3 Analog Microphone 3 Positive Input AVDD1_REG
A5 INN3 Analog Microphone 3 Negative Input AVDD1_REG
C3 DMC1 Digital Microphone Interface 1 Clock Output DVDDIO
C2 DMD1 Digital Microphone Interface 1 Data Input DVDDIO
B3 DMC2 Digital Microphone Interface 2 Clock Output DVDDIO
B2 DMD2 Digital Microphone Interface 2 Data Input DVDDIO
A3 DMC3 Digital Microphone Interface 3 Clock Output DVDDIO
A2 DMD3 Digital Microphone Interface 3 Data Input DVDDIO
D3 I.C. Internally Connected. Not used for normal device operation. Connect to GND externally. Power