Detailed Description

Detailed Description Device State Control

The device supports three distinct operating states. Hardware shutdown and software shutdown are low-power states that support very limited device functionality. Audio playback and/or record are only possible in the audio state.

A combination of hardware and software controls are provided to configure the current device operating state. If properly sequenced, the state transitions do not result in audible glitches. The device protection and monitor features can also force operating state changes (and are detailed separately from the state descriptions). Forced state transitions that are the result of fault conditions may result in audible glitches.

Hardware Shutdown State

When the device is first powered up or after a hardware reset event, the device always initializes into the hardware shutdown (or reset) state. In hardware shutdown, the device is configured to its lowest power state. Upon entering hardware shutdown, the device is globally placed into a reset condition. As a result, the I²C control interface is disabled and all device registers are returned to their PoR states.

When exiting hardware shutdown, the device initializes and then transitions into the software shutdown state. During this transition (as part of initialization), the OTP register trim settings are loaded. If the transition to software shutdown completes successfully, an INIT_DONE_* interrupt is generated. If this interrupt is seen unexpectedly during normal operation, this may be interpreted by software as an unexpected device reset or re-initialization.

If the OTP load routine fails to complete successfully during the transition, the device automatically retries several times. If the retries continue to fail, the transition is completed and an OTP_FAIL_* interrupt is generated once the device reaches the software shutdown state. To manually retry initialization, the software can reset the device with the software reset bit (RST). However, if the transition to software shutdown continues to fail (even with stable supplies in place prior to the transition), this may be indicative of a damaged or incorrectly trimmed device and it should not be operated.

When the hardware reset input (HW_EN) is asserted low, the device enters (or remains in) hardware shutdown. The device is also placed into hardware shutdown anytime the AVDDn, DVDD, or DVDDIO supplies drop below their respective UVLO thresholds. The device only exits hardware shutdown when all of these supplies are all above their respective UVLO thresholds, and the hardware reset input (HW_EN) is asserted high. Once all these conditions are met, the device automatically exits hardware shutdown, and transitions into software shutdown.

Software Shutdown State

The device enters the software shutdown state after it transitions out of hardware shutdown state and when exiting the audio state. When the device is in the software shutdown state (AUDIO_EN = 0), all blocks are automatically disabled and in their lowest power states except for interfaces (including I²C for programming), fault recovery monitors (such as clock stop auto recovery), and the AMIC bias generator. In the software shutdown state, all device registers can be programmed without restriction and all programmed register states are retained. If the software reset bit (RST) is written with a 1, the device is reset (all register states return to PoR values), and the device automatically transitions back into the software shutdown state.

The audio enable bit (AUDIO_EN) must be set high to allow the device to transition out of software shutdown state and into the audio state. Once it is set high the device may transition to the audio state (if at least one audio channel is enabled) and the transition is complete when the appropriate interrupts have been generated (PB_PWRUP_DONE_* and/or REC_PWRUP_DONE_* if enabled). When the audio enable bit (AUDIO_EN) is set low (or all audio channels are disabled) the device transitions back from the audio state to the software shutdown state, and when the transition is completed, a power down done (PWRDN_DONE_*) interrupt is generated (if enabled).

Audio State

The device transitions from the software shutdown state to the audio state when the audio enable bit (AUDIO_EN) is set high, and at least one PCM record channel enable bit (RECn_PCM_EN) or the PCM playback channel enable bit (PB_EN) is also set high.

The transition from the software shutdown state to the audio state is complete and the enabled audio channels are ready when the appropriate interrupts have been generated (PB_PWRUP_DONE_* and/or REC_PWRUP_DONE_* if enabled). In addition, if the device is already in the audio state (with only record active) and the playback channel is dynamically enabled, the playback power-up done interrupt (PB_PWRUP_DONE_*) is generated when the device is ready to receive playback data. Likewise, if the device is already in the audio state (with only playback active) and one or more audio record channels are dynamically enabled (when previously all three were disabled), the record power-up done interrupt (REC_PWRUP_DONE_*) is generated when the device is ready to transmit record data. The record power-up done interrupt does not flag again if additional record channels are dynamically enabled while one or more record channels are already active.

In the audio state, dynamically enabling or disabling the record channels does not disrupt active audio on the playback channel (with or without active digital filter channels). When either the audio enable control bit (AUDIO_EN) is set low or when all three record channels and the playback channel are all disabled, the audio channels are powered down normally and the device transitions back into software shutdown state.

Audio State Quiescent Power Consumption

The typical device quiescent power consumption in the audio state for a variety of common use case configurations are detailed below. All supplies and operation conditions are configured to the global default settings (as shown in the Electrical Characteristics Table unless otherwise indicated). A typical hybrid filter profile (feedback and feed-forward microphone record) has two low-latency digital filter channels and the playback compensation channel active. A typical feed-forward (microphone record) filter profile has just a single low-latency digital filter channel active. These profiles can be used to implement common filter use cases including ambient / voice filters and ANC filters. Typical profiles assume each active low-latency digital filter channel has eight biquad bands enabled and tuned, and that when active the playback compensation channel has six biquad bands enabled and tuned.

Table 1. PCM Interface Playback Only Quiescent Power
DEVICE MODE AND CONFIGURATION	I_AVDD1 (mA)	I_AVDD2 (mA)	I_DVDD (mA)	I_DVDDIO (mA)	POWER (mW)
Playback at f_S = 48kHz, High-Performance Mode	0.03	0.46	1.7	0.002	2.65
Playback at f_S = 48kHz, Low-Power Mode	0.03	0.38	1.7	0.002	2.55
Playback at f_S = 48kHz, Noise Gate Enabled, High-Performance Mode	0.03	0.46	1.09	0.002	1.92
Playback at f_S = 48kHz, 5-Band Equalizer Enabled in Pass-Through, High-performance Mode	0.03	0.46	1.78	0.002	2.75
Playback at f_S = 8kHz, High-Performance Mode	0.03	0.46	1.49	0.002	2.40
Playback at f_S = 192kHz, High-Performance Mode	0.03	0.46	2.07	0.002	3.09

Table 2. PCM Interface Record Only Quiescent Power
DEVICE MODE AND CONFIGURATION	I_AVDD1 (mA)	I_AVDD2 (mA)	I_DVDD (mA)	I_DVDDIO (mA)	POWER (mW)
Two AMIC Record Channels at f_S = 48kHz, High-Performance Mode	2.18	0.05	2.11	0.013	6.54
Three AMIC Record Channels at f_S = 48kHz, High-Performance Mode	3.26	0.05	2.41	0.013	8.84
Two AMIC Record Channels at f_S = 48kHz, Low-Power Mode	1.71	0.05	2.11	0.013	5.69
Three AMIC Record Channels at f_S = 48kHz, Low-Power Mode	2.55	0.05	2.41	0.013	7.56
Two AMIC Record Channels at f_S = 16kHz, Low-Power Mode	1.71	0.05	1.76	0.003	5.26
Two DMIC Record Channels at f_S = 48kHz, DMIC Clock at 3.072MHz	0.016	0.05	1.92	0.14	2.64
Two DMIC Record Channels at f_S = 8kHz, DMIC Clock at 768kHz	0.016	0.05	1.50	0.04	1.96

Table 3. PCM Interface Record and Playback Quiescent Power
DEVICE MODE AND CONFIGURATION	I_AVDD1 (mA)	I_AVDD2 (mA)	I_DVDD (mA)	I_DVDDIO (mA)	POWER (mW)
Playback and Two AMIC Record Channels at f_S = 48kHz, High-Performance Modes	2.18	0.46	2.95	0.013	8.04
Playback and Three AMIC Record Channels at f_S = 48kHz, High-Performance Modes	3.26	0.46	3.27	0.013	10.36
Playback and Two AMIC Record Channels at f_S = 48kHz, Low-Power Modes	1.71	0.38	2.95	0.013	7.09
Playback and Three AMIC Record Channels at f_S = 48kHz, Low-Power Modes	2.55	0.38	3.27	0.013	8.99
Playback and Two AMIC Record Channels at f_S = 16kHz, High-Performance Modes	2.18	0.46	2.50	0.005	7.49
Playback and Two DMIC Record Channels at f_S = 48kHz, DMIC Clock at 3.072MHz	0.03	0.46	2.79	0.14	4.20
Playback and Two DMIC Record Channels at f_S = 8kHz, DMIC Clock at 768kHz	0.03	0.46	2.21	0.04	3.33

Table 4. PCM Interface Playback with Digital Filter Channels Quiescent Power
DEVICE MODE AND CONFIGURATION	I_AVDD1 (mA)	I_AVDD2 (mA)	I_DVDD (mA)	I_DVDDIO (mA)	POWER (mW)
Playback with Compensation Enabled at f_S = 48kHz, Two AMIC Input Digital Filter Channels at f_S = 192kHz, Typical Hybrid Profile, High-Performance Modes	2.18	0.46	5.26	0.002	10.79
Playback with Compensation Enabled at f_S = 48kHz, Two AMIC Input Digital Filter Channels at f_S = 192kHz, Typical Hybrid Profile, Low-Power Modes	1.71	0.38	5.26	0.002	9.85
Playback with Compensation Enabled at f_S = 48kHz, Two AMIC Input Digital Filter Channels at f_S = 384kHz, Typical Hybrid Profile, High-Performance Modes	2.18	0.46	7.28	0.002	13.21
Playback at f_S = 48kHz, One AMIC Input Digital Filter Channel at f_S = 192kHz, Typical Feed-Forward Profile, High-Performance Modes	1.10	0.46	3.88	0.002	7.19
Playback at f_S = 48kHz, One AMIC Input Digital Filter Channel at f_S = 192kHz, Typical Feed-Forward Profile, Low-Power Modes	0.87	0.38	3.88	0.002	6.68
Playback with Compensation Enabled at f_S = 48kHz, Two DMIC Inputs at 3.072MHz to Digital Filter Channels at f_S = 192kHz, Typical Hybrid Profile, High-Performance Modes	0.03	0.46	5.17	0.13	7.04
Playback at f_S = 48kHz, One DMIC Input at 3.072MHz to Digital Filter Channel at f_S = 192kHz, Typical Feed-Forward Profile, High-Performance Modes	0.03	0.46	3.77	0.07	5.26

State Transition Diagram

Figure 7 shows the three device states and the state transition conditions. Normal state transitions between the audio state and the software shutdown state do not produce audible glitches on the output of the playback channel in excess of specifications (with the appropriate rate of volume ramping enabled on the playback channel and on any active digital filter channels).

If playback ramping is disabled, to avoid audible glitches the audio playback data needs to be silent (zero codes) and the low-latency digital filter channels should be disabled prior to enabling or disabling the playback channel (playback data ramping is then the responsibility of the host after enabling and prior to disabling the playback channel). Furthermore, the host should stop accepting record channel data prior to disabling a channel and/or initiating a transition from the audio state to the software shutdown state.

Forced state transitions occur immediately and may impact record data and/or produce audible playback glitches (see Figure 7). Fault events (such as clock failure, data error, amplifier overcurrent, FLL unlock, etc.) that occur unexpectedly during active audio record and/or playback (audio state) result in a forced state transition to the software shutdown state. Before initiating a software reset event (RST bit), de-asserting the hardware enable input (HW_EN pin), or disabling supplies (AVDDn, DVDD, or DVDDIO to below UVLO thresholds), the device should always be placed into the software shutdown state. If these actions are taken while the device is in the audio state, they trigger a forced state transition either to the hardware shutdown state (hardware enable and supply UVLO) or to the software shutdown state (reset event transitions briefly to hardware shutdown state to reset PoRs and then transition back into the software shutdown state).

Figure 7. Device State Transition Diagram

Device Sequencing

The recommended device power-up and power-down sequences are provided for two use cases: simple record and/or playback and for playback with the low-latency digital filter channels enabled. Steps with the same number followed by a letter can be performed in any order (i.e., steps nA, nB, and nC are non-sequential sub-steps of step n). Note that these example sequences are for static use cases, and that for details regarding dynamic use case switching (enabling and disabling of audio channels while in the audio state) see the corresponding section for a given audio channel.

Example Sequencing for Audio Playback and/or Record

The following recommended device sequencing examples apply to audio playback, audio record, or use cases with both (all with the internal low-latency digital filter channels disabled). Note that while not described here, once the device is in the audio state, it is also possible to dynamically enable and disable audio playback and audio record channels without interrupting any already active channels as long as the register control bit restrictions are observed.

Table 5. Recommended Power-Up Sequence: Audio Record and/or Playback
STEP	ACTION (STATE)	DETAILED DESCRIPTION
0	None (Hardware Shutdown State)	This is the lowest power state. The device and all registers are fully reset in this state, and no control or audio interface interactions are possible.
1A	Power Up Device Supplies (Hardware Shutdown State)	Power the AVDD1, AVDD2, AVDD3, DVDD, and DVDDIO supplies to above the respective UVLO thresholds. No supply sequencing is required. Optionally, if an analog microphone bias output is needed, also power MBVDD.
1B	Set the Hardware Enable (Hardware Shutdown State)	Drive the hardware enable input (HW_EN) high or always connect to DVDDIO.
2	Transition to the Software Shutdown State (State Transition)	Once all conditions are met (steps 1A and 1B), the device automatically transitions to the software shutdown state. The transition is complete after the hardware enable time (t_{HW_EN}) has elapsed (if no errors/retries are needed). Do not attempt to program the device during this transition. When the transition successfully completes, an INIT_DONE interrupt is generated.
3	None (Software Shutdown State)	This is the lowest power state where register settings are retained and the I²C interface is active. Can be used for a system idle/standby case or when system is active, but no audio use case is active. It is recommended that the system software verifies and then clears any interrupts upon entering this state.
4A	Program Device Registers (Software Shutdown State)	The system software should fully configure the device registers (except AUDIO_EN) for the desired audio use case.
4B	Configure the Analog Microphone Bias if Needed (Software Shutdown State)	If the analog microphone bias is needed while the device is in the software shutdown state, it can be configured and enabled at any time. If not, then it can be configured here but not enabled. It is then best to sequence the microphone bias enable (AMIC_BIAS_EN) just before the audio enable in step 5.
4C	Enable the External Clocks (Software Shutdown State)	Start the PCM interface clocks before exiting the software shutdown state.
5	Set Global Audio Enable Bit (Software Shutdown State)	Set the global audio enable bit high (AUDIO_EN) to allow the device to transition to the audio state (if all other conditions are met). If playback is enabled and playback volume ramping is disabled, then the input PCM playback data should be silent prior to and during the state transition.
6	Transition to the Audio State (State Transition)	The state transition is complete after the audio turn-on time (t_ON) has elapsed. Note that the duration of the audio turn-on time (t_ON) varies based on the configured record input charge time and playback volume ramp time. The transition has successfully completed when the power-up done interrupts are generated (REC_PWRUP_DONE_* and/or PB_PWRUP_DONE_*).
7	Audio Record/Playback (Audio State)	The device is in the audio state with record and/or playback active (as configured). To avoid errors and audible glitches during any device programming in the audio state, all register restrictions must be observed.

Table 6. Recommended Power-Down Sequence: Audio Record and/or Playback
STEP	ACTION (STATE)	DETAILED DESCRIPTION
0	Audio Record/Playback (Audio State)	The device is in the audio state with record and/or playback active.
1	Clear Global Audio Enable Bit (Audio State)	Set the global audio enable bit (AUDIO_EN) low to direct the device to transition to the software shutdown state. If playback was enabled and playback volume ramping was disabled, then the input PCM playback data should be silent prior to and during the state transition.
2	Transition to the Software Shutdown State (State Transition)	The transition is complete after the audio turn-off time (t_OFF) has elapsed. Note that the duration of the audio turn-off time (t_OFF) varies based on the configured playback volume ramp time. The transition has successfully completed when the power down interrupt is generated (PWRDN_DONE_*).
3	Idle/Reprogram Device (Software Shutdown State)	The device can idle in the software shutdown state, and the clocks can be disabled to save power. The device can be freely reconfigured in this state. It is recommended that the system software verify and then clear any interrupts upon entering this state. To return from this idle state to the audio state, start from step 3 in Table 5 and follow the power-up sequence from there.
4	Transition to the Hardware Shutdown State (State Transition)	Before transitioning to the hardware shutdown state, first ensure that the external clocks are disabled. Then, either assert the hardware enable input (HW_EN) to a valid logic low level for longer than the hardware disable time (t_{HW_DIS}) or power down any supply with a UVLO to below the threshold.
5	None (Hardware Shutdown State)	This is the lowest power state. All supplies may be disabled if desired. The device (including all interfaces and registers) is fully reset in this state.

Example Sequencing for Audio Playback with Low-Latency Digital Filters Active

The following recommended device sequencing applies to a use case of audio playback with one or both low-latency digital filter channels enabled. It is very similar to the sequencing for audio playback and/or record. However, a few extra steps are included for low-latency digital filter channel enable and disable.

Table 7. Recommended Typical Power-Up Sequence: Audio Playback with Low-Latency Digital Filter Channels
STEP	ACTION (STATE)	DETAILED DESCRIPTION
0	None (Hardware Shutdown State)	This is the lowest power state. The device and all registers are fully reset in this state, and no control or audio interface interactions are possible.
1A	Power Up Device Supplies (Hardware Shutdown State)	Power the AVDD1, AVDD2, AVDD3, DVDD, and DVDDIO supplies to above the respective UVLO thresholds. No supply sequencing is required. Optionally, if an analog microphone bias output is needed, also power MBVDD.
1B	Set the Hardware Enable (Hardware Shutdown State)	Drive the hardware enable input (HW_EN) high or always connect to DVDDIO.
2	Transition to the Software Shutdown State (State Transition)	Once all conditions are met (steps 1A and 1B), the device automatically transitions to the software shutdown state. The transition is complete after the hardware enable time (t_{HW_EN}) has elapsed (with no errors/retries). Do not program the device during this transition. When the transition successfully completes, an INIT_DONE interrupt is generated.
3	None (Software Shutdown State)	This is the lowest power state where register settings are retained and the I²C interface is active. Can be used for a system idle/standby case or when system is active, but no audio use case is active. It is recommended that the system software verify and then clear any interrupts upon entering this state.
4A	Program the Device Registers (Software Shutdown State)	The system software should fully configure the device registers (except AUDIO_EN) for the playback with low-latency digital filters (DF) use case. Ensure that the desired microphone inputs channel(s), digital filter channel(s), playback compensation channel, and the playback channel are all configured and ready to be enabled. For a smooth startup, enable volume ramping and enable digital mute on all channels.
4B	Configure the Analog Microphone Bias if Needed (Software Shutdown State)	If the analog microphone bias is needed while the device is in the software shutdown state, it can be configured and enabled at any time. Otherwise, to save power it should not be enabled until just before the state transition.
4C	Enable the External Clocks (Software Shutdown State)	Start the PCM interface clocks before exiting the software shutdown state. To save power, this should not be done until just before the state transition.
5	Set Global Audio Enable Bit (Software Shutdown State)	Set the global audio enable bit (AUDIO_EN) high to allow the device to transition to the audio state (if all other conditions are met). If playback volume ramping is disabled, then the input PCM playback data should be silent prior to and during the state transition.
6	Transition to the Audio State (State Transition)	The state transition is complete after the audio turn-on time (t_ON) has elapsed. Note that the duration of the audio turn-on time (t_ON) can vary based on the configured record input charge time and playback volume ramp time (if not muted). The transition has successfully completed when the playback power-up done interrupt (PB_PWRUP_DONE_*) is generated.
7A	Begin Audio Playback (Audio State)	The device is in the audio state and is receiving PCM playback data from the host. For smooth startup, first unmute the playback channel before unmuting the digital filter and playback compensation channels. If audio playback data starts after the playback volume/unmute ramp (or if playback volume ramping is disabled), the host is responsible for playback audio data ramping.
7B	Unmute the Low-Latency Digital Filter and Playback Compensation Channels (Audio State)	In the audio state, microphone input data samples begin filling and settling the low-latency digital filters. For best results, allow time for a few samples to propagate before un-muting the low-latency digital filter and playback compensation channels. The optimal timing depends on the tuned filter response and sample rate settings. Once unmuted, the channels ramp up and are mixed into the playback channel.
8	Audio Playback with Digital Filter Channels Active (Audio State)	To avoid errors and audible glitches, during any device programming in the audio state all register restrictions must be observed.

Table 8. Recommended Typical Power-Down Sequence: Audio Playback with Low-Latency Digital Filter Channels
STEP	ACTION	DETAILED DESCRIPTION
0	Audio Playback with Digital Filter Channels Active (Audio State)	The device is in the audio state with playback and digital filters active.
1	Clear Global Audio Enable Bit (Audio State)	For a smooth power-down, enable volume ramping and first mute the digital filter channels, the playback compensation channel, and the playback channel prior to power-down. Next, set the global audio enable bit (AUDIO_EN) low to transition to the software shutdown state. If playback volume ramping is disabled, the input PCM playback data should be silent and digital filter data should be muted prior to and during the transition.
2	Transition to the Software Shutdown State (State Transition)	The transition is complete after the audio turn-off time (t_OFF) has elapsed. Note that the duration of the audio turn-off time (t_OFF) varies based on the configured playback volume ramp time. The transition has successfully completed when the power-down interrupt (PWRDN_DONE_*) is generated.
3	Idle/Reprogram Device (Software Shutdown State)	The device can idle in the software shutdown state and clocks can be disabled to save power. The device can be freely reconfigured in this state. It is recommended that the system software verify and then clear any interrupts upon entering this state. To return from this idle state to the audio state, start from step 3 in Table 7 and follow the power-up sequence from there.
4	Transition to the Hardware Shutdown State (State Transition)	Before transitioning to the hardware shutdown state, first ensure that the external clocks are disabled. Then, either assert the hardware enable input (HW_EN) to a valid logic low level for longer than the hardware disable time (t_{HW_DIS}) or power down any supply with a UVLO to below the threshold.
5	None (Hardware Shutdown State)	This is the lowest power state. All supplies may be disabled if desired. The device (including all interfaces and registers) is fully reset in this state.

PCM Digital Audio Interface

The flexible PCM slave digital audio interface supports a set of common audio playback channel sample rates from 8kHz to 192kHz and record channel sample rates from 8kHz to 48kHz. The PCM interface supports timing for standard I²S, left justified, and TDM data formats. The PCM interface is disabled and powered down when both the PCM data input (DIN) and PCM data output (DOUT) are disabled.

Figure 8. PCM Input and Output Audio Data Channels

PCM Clock Configuration

The PCM slave interface requires the host to supply both the bit clock (BCLK) and frame clock (LRCLK). To configure the PCM interface clock inputs, the host must program the PCM interface (and playback channel) sample rate (PCM_PB_SR) and the BCLK to LRCLK ratio (PCM_BSEL). The configured PCM interface (and playback) sample rate must match the frequency of the frame clock (LRCLK).

The PCM record channel sample rate (PCM_REC_SR) may be set to the same rate or a lower rate than the playback channel sample rate (PCM_PB_SR) according to the restrictions in Table 9. Only integer playback to record clock ratios are supported.

When the PCM record channel sample rate is set to a lower rate than the playback channel (DIN receive), the PCM output data (DOUT transmit) contains extra frames (based on the playback to record sample rate ratio). By default, the extra record channel output data frames contain repeated record data samples. However, by setting the PCM_TX_NO_RPT_SAMP bit high, each record data sample is sent only once, instead of repeated samples, followed by zero code data in the extra frames.

Table 9. Supported Playback to Record Sample Rate Ratios
N/A = NOT AVAILABLE N/S = NOT SUPPORTED		PCM RECORD CHANNEL SAMPLE RATE IN KILOHERTZ (REC_SR)
N/A = NOT AVAILABLE N/S = NOT SUPPORTED		48	44.1	32	24	22.05	16	12	11.025	8
PCM PLAYBACK CHANNEL SAMPLE RATE IN KILOHERTZ (PCM_PB_SR)	192	4	N/S	6	8	N/S	12	16	N/S	24
	176.4	N/S	4	N/S	N/S	8	N/S	N/S	16	N/S
	96	2	N/S	3	4	N/S	6	8	N/S	12
	88.2	N/S	2	N/S	N/S	4	N/S	N/S	8	N/S
	48	1	N/S	N/S	2	N/S	3	4	N/S	6
	44.1	N/A	1	N/S	N/S	2	N/S	N/S	4	N/S
	32	N/A	N/A	1	N/S	N/S	2	N/S	N/S	4
	24	N/A	N/A	N/A	1	N/S	N/S	2	N/S	3
	22.05	N/A	N/A	N/A	N/A	1	N/S	N/S	2	N/S
	16	N/A	N/A	N/A	N/A	N/A	1	N/S	N/S	2
	12	N/A	N/A	N/A	N/A	N/A	N/A	1	N/S	N/S
	11.025	N/A	N/A	N/A	N/A	N/A	N/A	N/A	1	N/S
	8	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A	1

The device supports a range of BCLK to LRCLK clock ratios (PCM_BSEL) ranging from 32 to 512. However, based on the selected PCM interface sample rate (LRCLK frequency) the configured clock ratio cannot result in a required BLCK frequency that exceeds 24.576MHz.

PCM Data Format Configuration

The device supports the I²S, left-justified, and TDM data formats, and the PCM operating mode is selected using the PCM_FORMAT bit field.

I²S and Left-Justified Mode

The I²S and left-justified PCM data formats support two channels that can be 16, 24, or 32 bits in length. The BCLK to LRCLK ratio (PCM_BSEL) must be configured to be twice the desired channel length. The audio data word size is then configurable to 16, 24, or 32 bits in length using the PCM_CHANSZ bit, and must be programmed to be less than or equal to the configured channel length. If the configured channel length exceeds the configured data word size, the data input LSBs are truncated and the data output LSBs are padded with either zero or Hi-Z data (based on the PCM_TX_EXTRA_HIZ bit setting). If only one data output channel is needed and the bus is shared with another device, the unused channel should not have data assigned to it and Hi-Z padding is recommended to avoid potential data collisions.

Table 10. Supported I²S and Left-Justified Mode Configurations
CHANNELS	CHANNEL LENGTH	BCLK TO LRCLK RATIO (PCM_BSEL)	SUPPORTED DATA WORD SIZES (PCM_CHANSZ)
2	16	32	16
	24	48	16, 24
	32	64	16, 24, 32

With the default settings, a falling LRCLK edge indicates the start of a new frame and the left channel data (Channel 0), while a rising LRCLK edge indicates the right channel data (Channel 1). In I²S mode, the MSB of the audio word is latched on the second active BCLK edge after an LRCLK transition. In left-justified mode, the MSB of the audio word is latched on the first active BCLK edge after an LRCLK transition.

The BCLK active edge (rising or falling) used for data capture (DIN receive) and data output (DOUT transmit) is selected using the PCM_BCLKEDGE bit. The PCM_CHANSEL bit configures which LRCLK edge indicates the start of a new frame (and channel 0), and LRCLK transitions always align with the inactive BCLK edge. The data output is valid on the same active BCLK edge as the data input. The data output also transitions on the same edge as the data input.

Figure 9. I2S Timing Mode Example — Figure 9. I²S Timing Mode Example

Figure 10. Left-Justified Mode Timing Examples

TDM Modes

The provided TDM modes support timing for up to eight digital audio input channels (DIN receive) each containing 16, 24, or 32 bits of data. The record channel data output (DOUT transmit) is structured into 8-bit slots, and the timing can support up to a maximum of 64 data output slots. The data output word size is always 24 bits (for record channels 1 through 4) and output data can be assigned to any set of sequential data output slots. 16-bit output data and transmit timing can also be supported by assigning data to partially overlapping data output slots. The number of TDM input channels and output slots is determined by both the selected BCLK to LRCLK ratio (PCM_BSEL) and the selected data word and channel length (PCM_CHANSZ).

For a given valid configuration, the number of available data input (DIN) channels per frame is calculated as follows:

Number of Available Data Input Channels = BCLK to LRCLK Ratio / Channel Length

For a given valid configuration, the number of available 8-bit data output (DOUT) slots per frame is calculated as follows:

Number of Available Data Output Slots = BCLK to LRCLK Ratio / 8

Table 11 shows the supported TDM mode configurations. In some configurations, the maximum PCM interface and playback sample rate is limited to less than 192kHz to avoid violating the BCLK frequency limit of 24.576MHz.

Table 11. Supported TDM Mode Configurations
INPUT DATA CHANNELS	OUTPUT DATA SLOTS	INPUT DATA WORD SIZE (PCM_DATA_WIDTH)	BCLK TO LRCLK RATIO (PCM_BSEL)	MAXIMUM PLAYBACK SAMPLE RATE (PCM_PB_SR)
2	4	16	32	192kHz
	6	24	48
	8	32	64
4	8	16	64
	12	24	96
	16	32	128
8	16	16	128
	24	24	192	96kHz
	32	32	256
16	32	16	256
	48	24	384	48kHz
	64	32	512	48kHz

With the default PCM interface settings, in TDM mode a rising frame clock (LRCLK) edge acts as the frame sync pulse and indicates the start of a new frame. The frame sync pulse width must be at least one bit wide, however the falling edge can occur at any time as long as it does not violate the setup time of the next frame sync pulse rising edge. The PCM_CHANSEL bit can be used to invert the active LRCLK edge (sync pulse) used to start a TDM frame.

In TDM mode, the MSB of the first audio word can be latched on the first (TDM Mode 0), second (TDM Mode 1), or third (TDM Mode 2) active BCLK edge after the sync pulse, and this is programmed with the PCM_FORMAT bit field. Additionally, the PCM_BCLKEDGE bit selects the active BCLK edge that is used for data capture and data output. The data output is valid on the same active BCLK edge as the data input, and the data output also transitions on the same edge as data input.

PCM Data Channel Configuration

The PCM interface data input (DIN) receives the source data for the playback channel (and playback compensation channel), while the data output (DOUT) can transmit the data from both the three microphone record channels and the playback DSP output monitor channel. In addition, the PCM interface also provides a data loopback mode (PCM data input looped back to the PCM data output) and an internal data loop-through mode (any microphone record channel output data looped through to become the input of the playback channel).

PCM Data Input

The PCM interface data input (DIN) is enabled with the PCM_RX_EN bit, and the playback channel can accept data from any valid PCM input data channel. The PCM data input (DIN) channel to the playback channel is selected with the PCM_PB_SOURCE bit field. In I²S and left-justified modes, only 2 input data channels are available while in TDM mode up to 16 channels of input data may be available. If the PCM data input is disabled (PCM_RX_EN = 0), a zero code value is driven into the playback channel.

PCM Data Output

The PCM interface data output (DOUT) is enabled by the PCM_TX_EN bit field, and can transmit any output data source onto any valid output channel or slot. The PCM data output accepts source data from both the microphone record channels and the playback DSP monitor channel.

In I²S and left-justified mode, only 2 data output channels are available in each output transmit frame (channel 0 and 1). Only a single output data source can be assigned to each data output channel (unless channel interleaving is enabled). The PCM data output word length (PCM_CHANSZ) and channel length (PCM_BSEL) are configured independently.

In TDM mode, each output transmit frame can contain up to 64 sequential 8-bit data output slots, each of which is numbered from 0 up to a maximum of 63. The record channel data outputs are assigned individually to data output slots (8 bits). Unlike the PCM playback data input (where in TDM mode the data word and channel length are always identical at 16, 24, or 32 bits), in TDM mode the PCM record data output channels are always 24 bits in length (3 slots). The data output sources and control bit fields are shown in Table 12.

Table 12. PCM Record Output Data Sources
OUTPUT DATA SOURCE	OUTPUT SOURCE ENABLE	SLOT ASSIGNMENT
Microphone Record Channel 1	REC1_PCM_EN	PCM_REC1_SLOT
Microphone Record Channel 2	REC2_PCM_EN	PCM_REC2_SLOT
Microphone Record Channel 3	REC3_PCM_EN	PCM_REC3_SLOT
Playback DSP Monitor Channel	REC4_PCM_EN	PCM_REC4_SLOT

An individual enable and slot assignment bit field is provided for each output data source. In I²S and left-justified modes, use output slot 0 to assign data to channel 0 and output slot 1 to assign data to channel 1. In TDM mode, the slot assignment selects the slot where the 24-bit record output data transmit begins (i.e., if the 24-bit output data is assigned to slot 5, slots 5, 6 and 7 are occupied).

In TDM mode, each record data output source can be assigned to any valid data output slot. It is invalid to assign record output channels to the same starting slot. However, it is valid to truncate the 24-bit data by partially overlapping channel assignments (for example, to create 16-bit record data outputs). It is, however, invalid to assign a data source to any starting slot that does not exist in the frame structure of the current PCM interface configuration (for example, if the configuration has 16 slots, assigning data to slot 20 is invalid). Table 13 shows a few TDM mode configuration examples.

Any data output (DOUT) slots that exist in the current frame structure but have no output data type assigned to them (unused slots) are either Hi-Z or driven with a 0 code (set by slot with the PCM_TX_SLOT_HIZ bit field). Likewise, if a data output source is disabled, then the assigned data output slots are considered unused and are also either Hi-Z or driven with a 0 code (as set by the PCM_TX_SLOT_HIZ bit field).

Table 13. Example Record Output Data Slot Assignments
USE CASE DESCRIPTION	RECORD 1	RECORD 2	RECORD 3	RECORD 4
32-Bit Input Data with 2 Channels 16-Bit Output Data (No Padding) with 8 Slots	Slot 0	Slot 2	Slot 4	Slot 6
24-Bit Input Data with 4 Channels 24-Bit Output Data (No Padding) with 12 Slots	Slot 0	Slot 3	Slot 6	Slot 9
32-Bit Input Data with 4 Channels 24-Bit Output Data (8-Bit Pad) with 16 Slots	Slot 0	Slot 4	Slot 8	Slot 12

PCM Data Output Channel Interleaving

In I²S and left-justified use cases, the PCM interface limits the number of available data output channels to 2 making it impossible to fit more than 2 record channel data output channels (from either a single or multiple devices) onto a single shared data output (DOUT) line. For these cases, the PCM data output (DOUT) can be configured to allow output data sources from a single device to share a single data output channel. To enable channel-interleaved mode, perform the following:

Set the PCM_TX_INTERLEAVE bit high.
Set the PCM_TX_INTERLEAVE_SEL bit field to select which two microphone record channels (microphone record channel 1, 2, or 3) can be interleaved. The playback monitor data on record channel 4 cannot be interleaved.
Assign the two selected record channel data output sources to the same valid data output channel (using the PCM_RECn_SLOT bit fields).

In this configuration, the record data sources are frame interleaved on the assigned data output channel. The data words are both equal in length, but if the channel length is longer than data word size the trailing padding bits are set to either Hi-Z or 0 code depending on the state of the PCM_TX_EXTRA_HIZ bit field.

To identify the record channel data source in channel-interleaved mode, the LSB of the data word is dropped (truncated). The data word is then right shifted by a single bit, and the now vacant MSB is replaced with either a 0 to indicate the first record channel number or a 1 to indicate the second record channel number (in order as set by the PCM_TX_INTERLEAVE_SEL bit field). For phase alignment, the first record channel data for a single sampling instant is always transmitted in the assigned channel on the first frame, followed by the second record channel data on the second frame. The MSB value and the transmission order allow the host to identify and phase-align the record channel output data across frames.

Since the record channel data is frame interleaved, the sample rate for the PCM interface and playback channel (PCM_PB_SR) must be greater than that of the record channel (PCM_REC_SR) by an integer ratio of 2 or greater. The example in Figure 12 shows a basic case where the sample rate of the PCM interface is twice that of the record channel.

Figure 12. I2S Mode PCM Data Output Channel Interleaving Example — Figure 12. I²S Mode PCM Data Output Channel Interleaving Example

PCM Data Output Drive Strength

The PCM data output logic level drive strength is configured with the PCM_DOUT_DRV bit field, and four different CMOS drive strength selections are available.

PCM Data Loopback and Loop-Through Modes

The PCM interface also supports data loopback and loop-through operating modes. The PCM data input (DIN) to data output (DOUT) loopback mode is enabled by setting the PCM_LB_DOUT_EN bit high. When enabled, the PCM input data source channel (as set by PCM_PB_SOURCE bit) replaces the the PCM record channel output data for any enabled microphone record channels (based on the RECn_PCM_EN settings). PCM data loopback mode requires that both the data input and data output interfaces be enabled (PCM_TX_EN and PCM_RX_EN), and configured to operate at the same sample rate (PCM_PB_SR and PCM_REC_SR set equal).

The PCM microphone record data to playback channel internal loop-through mode is configured with the PCM_PB_LT_EN bit field. When enabled, the selected microphone record channel data (microphone record channel 1, 2, or 3) replaces the PCM data input (DIN) as the input source for the playback channel. PCM internal data loop-through mode requires both the selected microphone record channel and playback channel be enabled (RECn_PCM_EN and PB_EN), and configured to operate at the same sample rate (PCM_PB_SR and PCM_REC_SR set equal).

Figure 13. PCM Data Loopback and Loop-Through Channels

I²C Slave Control Interface

The device provides an I²C slave control interface that is used to program the control registers. The device control registers in user space that are programmable with the I²C interface reside in the address space from 0x2000 to 0x27FF.

I²C Interface Address

When the I²C slave interface is active, the device slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. The address is programmable with the ADDR pin and is configured as shown in Table 14. The ADDR pin state is checked and locked in at the beginning of each I²C transaction on the connected bus. The ADDR input cannot be left unconnected.

In addition to the address set by the ADDR input, a group write address of 0x6A is available for cases where synchronized write transactions are needed across multiple devices. The group write address is enabled by default, but can be disabled by setting the I2C_GROUP_ADDR_EN = 0. When enabled, the device (or a group of devices) accept write transactions through the group address regardless of the ADDR connection. Group read transactions are not supported (and should not be attempted to avoid data collisions). The I2C_GW_DONE interrupt triggers when a transaction is successfully completed through the group write address. If a device in a given group does not generate the I2C_GW_DONE interrupt, the device state and register configuration should be checked. When the group write address is disabled, the device does not respond to any transactions through the group write address. Regardless of the state of the I2C_GROUP_ADDR_EN bit, transactions through the primary device address set by the ADDR input always function normally.

Table 14. Available I²C Slave Addresses
CONDITIONS	I²C SLAVE WRITE ADDRESS	I²C SLAVE READ ADDRESS
ADDR Connected to DVDDIO	0x62	0x63
ADDR Connected to DGND	0x64	0x65
ADDR Connected to SDA	0x66	0x67
ADDR Connected to SCL	0x68	0x69
I2C_GROUP_ADDR_EN = 1	0x6A	NA

I²C Interface Bit Transfer Protocol

One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (START and STOP conditions).

I²C Interface START and STOP Conditions

SDA and SCL idle high when the bus is not in use. An I²C master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high. A START condition from the master signals the beginning of a transmission to the slave. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition.

Figure 14. I2C Slave Interface START and STOP Condition Example — Figure 14. I²C Slave Interface START and STOP Condition Example

I²C Interface Early STOP Condition

The device recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition.

I²C Interface Acknowledge Bit

The acknowledge bit (ACK) is a clocked ninth bit that the slave uses to handshake receipt each byte of data when in write mode (Figure 15). The slave pulls down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication.

The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the slave is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not-acknowledge (NACK) is sent when the master reads the final byte of data from the slave followed by a STOP condition.

Figure 15. I2C Slave Interface Acknowledge Bit Example — Figure 15. I²C Slave Interface Acknowledge Bit Example

I²C Interface Write Data Format

A write to the device through the I²C slave interface includes transmission of a START condition, the slave address with the READ-WRITE bit set to 0, two bytes of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition.

Transmission of the slave address with the READ-WRITE bit set to 0 indicates that the I²C master intends to write data to the device. The device acknowledges receipt of the address byte during the ninth SCL pulse.

The second and third bytes transmitted from the master configure the device’s internal register address pointer. The pointer tells the device where to write the next byte of data. An acknowledge pulse is sent by the device upon receipt of each byte of the register address data.

The fourth byte sent to the device contains the data to be written to the chosen register address. An acknowledge pulse from the device signals receipt of the data byte. The address pointer auto increments to the next register address after each received data byte. This auto-increment feature allows the master to write to sequential registers within one continuous frame. The master signals the end of transmission by issuing a STOP condition.

Figure 16. I2C Master Writing One Byte of Data to the Slave Device — Figure 16. I²C Master Writing One Byte of Data to the Slave Device

Figure 17. I2C Master Writing n-Bytes of Data to the Slave Device — Figure 17. I²C Master Writing n-Bytes of Data to the Slave Device

I²C Interface Read Data Format

There are two ways to read data back from the slave device. First, a START condition followed by a read command resets the address pointer to the default starting register at address 0x2000. Therefore, simply sending the devices slave address with the READ-WRITE bit set to 1 initiates a read operation with the internal register address pointer starting from 0x2000. In this case, the device acknowledges receipt of its slave address by pulling SDA low during the ninth SCL clock pulse.

Instead, the address pointer can be preset to a specific target register address before a read command is issued. The master can preset the slave register address pointer by first sending the device's slave address with the READ-WRITE bit set to 0 (write command) followed by two commands containing the target register address for the address pointer. A REPEATED START condition is then sent followed by the read command (slave address with the READ-WRITE bit set to 1). This begins a read command with the internal register address pointer set to the target register address.

In either scenario, the first byte transmitted from the device contains the contents of the register that the address pointer is set to. Transmitted data is valid on the rising edge of SCL. The master acknowledges (ACK) receipt of each read byte during the acknowledge clock pulse. The address pointer then auto-increments after each acknowledged read data byte. This auto-increment feature allows multiple registers to be read sequentially within one continuous frame.

The master must issue an acknowledge (ACK) for all correctly received bytes except the last byte. To terminate the read operation, the final byte must be followed by a not acknowledge (NACK) from the master and then a STOP condition. A not-acknowledge (NACK) followed by a STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the address pointer is reset and the first data byte to be read is from register 0x2000.

Figure 18. I2C Master Reading One Byte of Data from the Slave Device — Figure 18. I²C Master Reading One Byte of Data from the Slave Device

Figure 19. I2C Master Reading n-Bytes of Data from the Slave Device — Figure 19. I²C Master Reading n-Bytes of Data from the Slave Device

Interrupts

The device supports individually enabled status interrupts for sending feedback to the host about events that have occurred on-chip. When enabled, device interrupts are sent on the IRQ output.

Interrupt Bit Field Composition

Each device interrupt source has five individual bit field components. The function of each component is detailed below and the corresponding bit fields for each source can be identified by the appended suffix (shown in parentheses).

Raw Status (RAW)

Each interrupt source has a read-only bit to indicate the real-time raw status of the interrupt source.

State (STATE)

Each interrupt source has a read-only state bit that is set whenever a rising edge occurs on the associated raw status bit. The state bit is set regardless of the setting of the source enable bit.

Flag (FLAG)

Each interrupt source has a read-only flag bit. If the source enable bit is set, then the flag bit is set and an interrupt can be generated whenever the source state bit is set.

Enable (EN)

Each interrupt source has a dynamic read/write enable bit. When the enable bit is set, the associated flag bit is set and an interrupt can be generated whenever the source state bit is set.

Clear (CLR)

Each interrupt source has a dynamic write-only clear bit that resets the associated state and flag bits low when a 1 is written. Writing a 0 to the clear bit has no effect. The IRQ bus is de-asserted if all flag bits are low.

Interrupt IRQ Output Configuration

The IRQ output is used to signal the host when an interrupt event occurs, and is enabled when the IRQ_EN bit is 1. Once enabled, the IRQ output asserts anytime an interrupt event occurs (any FLAG bit is set high), and de-asserts when all events are cleared (all FLAG bits set low). The IRQ_POL bit selects the assert polarity of the IRQ bus. Interrupt events assert the IRQ bus low if IRQ_POL is 0 and high if IRQ_POL is 1.

The device allows the user to configure the drive mode, drive strength, and polarity of the IRQ output. The IRQ_MODE bit controls the output drive mode. If IRQ_MODE is 0, the IRQ output is configured as an open-drain output, and requires an external pullup resistor (typically 1.5kΩ). Alternatively, setting the IRQ_INT_PU bit to 1 enables an internal 100kΩ weak pullup resistor.

If IRQ_MODE is 1, then the IRQ output is configured as a push-pull CMOS output. In this mode, the IRQ_DRV bit field sets the drive strength of the IRQ output. Four different drive strength options are available.

Interrupt Event Sources

The events listed in Table 15 and Table 16 can cause IRQ bus interrupts when enabled (if the interrupt source enable bit is high).

Table 15. Device Interrupt Event Sources 1
REGISTER ADDRESS	BIT NUMBER	INTERRUPT SOURCE	BIT NAME	DESCRIPTION
0x2001 0x2003 0x2005 0x2007 0x2009	7	Device Initialization Done Event	INIT_DONE_*	Indicates when the device has completed the transition from a reset event or the hardware shutdown state into the software shutdown state. Once this occurs, the device is ready to accept programming through the I²C control interface.
	6	OTP Load Failed Event	OTP_FAIL_*	Indicates that the OTP load routine that runs when initializing the device has failed to complete successfully.
	5	Power Down to Software Shutdown State Done Event	PWRDN_DONE_*	Indicates the device has successfully completed power down into the software shutdown state from the audio state.
	4	Playback Channel Enabled in the Audio State	PB_PWRUP_DONE_*	Indicates the device has both transitioned out of the software shutdown state, and that the playback channel is enabled and ready to receive audio data.
	3	Record Channel Enabled in the Audio State	REC_PWRUP_DONE_*	Indicates the device has both transitioned out of the software shutdown state, and that at least one record channel is enabled and ready to transmit audio data. This interrupt is not generated when at least one record channel is already active, and additional record channels are dynamically enabled.
	2	Clock Monitor Error Event	CLOCK_ERR_*	Indicates that the clock monitor has detected a clock error event. Clock error events can only be generated when the audio enable bit (AUDIO_EN) is first set high.
	1	Clock Monitor Auto Recovery Event	CLOCK_REC_*	Indicates that the clock monitor has detected a clock recovery event. Clock recovery events can only generated in auto mode after a clock error event has first occurred.
	0	Data Monitor Error Event	DATA_ERR_*	Indicates that the playback data monitor has detected a data error event. Data error events can only be generated when the audio enable bit (AUDIO_EN) is first set high.

Table 16. Device Interrupt Event Sources 2
REGISTER ADDRESS	BIT NUMBER	INTERRUPT SOURCE	BIT NAME	DESCRIPTION
0x2002 0x2004 0x2006 0x2008 0x200A	7	FLL Unlock Error Event	FLL_ERR_*	Indicates that the FLL either failed to lock while transitioning from software shutdown to the audio state, or that FLL lock was lost while the device was operating in the audio state.
	6	I²C Group Write Done Event	I2C_GW_DONE_*	Indicates that the I²C slave interface received and completed a write transaction through the I²C Group Address of 0x6A.
	5	-	-	-
	4	Playback Amplifier Overcurrent Protection Event	AMP_OCP_*	Indicates that the playback amplifier output overcurrent protection limit was exceeded.
	3	Playback Compensation Channel Ramp Done Event	PBC_RMP_DONE_*	Indicates that the playback compensation channel has finished ramp-up or down during an enable, mute, unmute, or volume change.
	2	Digital Filter Channel 2 Ramp Done Event	DF2_RMP_DONE_*	Indicates that digital filter channel 2 has finished ramp-up or down during an enable, disable, mute, unmute, or volume change.
	1	Digital Filter Channel 1 Ramp Done Event	DF1_RMP_DONE_*	Indicates that digital filter channel 1 has finished ramp-up or down during an enable, disable, mute, unmute, or volume change.
	0	Playback Channel Ramp Done Event	PB_RMP_DONE_*	Indicates that the playback channel has finished ramp-up or down during an enable, disable, mute, unmute, or volume change.

Microphone Input Channels

The device features three microphone input channels. The three channels can operate concurrently, and each is capable of independently selecting either an analog microphone (AMIC) or digital microphone (DMIC) as the input source with the respective RECn_SEL bit field. This allows for any combination of three analog and/or digital microphones to be active concurrently. The digital filters in each channel are automatically configured based on both the selected input source (AMIC or DMIC inputs) and the internal digital filter sample rate setting (DSP_SR).

The device provides three audio input pairs each with a pre-amplifier and an ADC capable of supporting either a single-ended or differential analog microphone (or a line level) input. The device also provides three separate digital microphone interfaces each capable of supporting either a mono or stereo digital microphone connection. More than three microphones may be connected to the device (for multiple use cases), however only three can be accepted as concurrent inputs for any given single use case.

Each microphone input channel can route output data concurrently to both a designated record channel and a low-latency digital filter channel (microphone input channel 3 can route data to both the DF1 and DF2 channels). Table 17 shows all of the input source and output data options for each of the three microphone input channels.

Table 17. Microphone Input Channel Connections
CHANNEL	INPUT SOURCE SELECTION	OUTPUT DATA ROUTING
Microphone Input 1	AMIC ADC 1 or Any DMIC Interface	Record Channel 1 and/or Digital Filter Channel 1
Microphone Input 2	AMIC ADC 2 or Any DMIC Interface	Record Channel 2 and/or Digital Filter Channel 2
Microphone Input 3	AMIC ADC 3 or Any DMIC Interface	Record Channel 3 and/or Digital Filter Channel 1 and/or 2

Figure 20. Microphone Input Channel Detailed Block Diagram

Analog Microphone Inputs

The device provides three analog inputs each capable of supporting one differential or single-ended analog microphone (AMIC) or line level connection. Each input includes a dedicated AMIC pre-amplifier and ADC stage, and is individually enabled and disabled with the respective AMICn_EN bit. The device also provides a programmable, low-noise AMIC bias generator with three separate output connections.

The device includes settings that adjust both the power consumption and performance of the analog microphone inputs. Prior to enabling a given analog microphone input, the AMIC pre-amplifier and ADC can be configured with the AMICn_LP_MODE bit to operate in either high performance mode or low power mode. All three AMIC input channels are clocked at the same rate with the same oversampling ratio (OSR). To reduce power consumption, the ADC clock rate and OSR can be reduced by setting the AMIC_ADC_RATE bit to 1 prior to enabling any of the AMIC inputs.

Differential analog microphones must be AC-coupled to both the positive and negative analog microphone inputs directly. For single-ended analog microphones, AC-couple the microphone output to the positive input directly, and AC-couple the negative input to ground (either directly near the device or if possible to a point close to the ground connection of the analog microphone). Each analog microphone pre-amplifier provides a separate programmable analog gain level and input impedance setting. The pre-amplifier programmable gain range is from -6dB to +21dB with a 3dB step size, and is selected by channel with the respective AMICn_PGA_GAIN bit field setting. Each pre-amplifier can be individually configured with the AMICn_PGA_RIN bit to present (when active) either the normal (35kΩ) or reduced (10kΩ) input impedance. Reduced input impedance mode provides a significant reduction in noise, but may not be compatible with all analog microphones and input coupling capacitors. The gain and input impedance settings should be configured based on the connected microphone prior to enabling a given AMIC input, and should not be changed while that input is enabled.

By default, the analog microphone input channels have dynamic range extension (DRE) and ADC output data dither enabled. When DRE is enabled, the gain structure of the input channel adjusts automatically based on the detected input signal level to maximize ADC dynamic range, while preserving the input headroom determined by the selected pre-amplifier gain setting. DRE can be independently disabled for a given AMIC input channel by setting the respective AMICn_DRE_EN bit to 0. In addition, dither can also be disabled for any input channel by setting the respective AMICn_DITH_EN bit to 0.

Figure 21. Differential and Single-Ended Analog Microphone Connections

Analog Microphone Control Sequencing

Analog microphone input channels can only be active when the device is in the audio state. The enable bits (AMICn_EN) are all located in the same register, and can be programmed in either the software shutdown state or dynamically in the audio state. When dynamically enabling record or digital filter channels with an analog microphone input, the analog microphone input enable bit should be set first before setting the enable for either the destination record channel (RECn_PCM_EN) and/or the digital filter channel (DF1_EN or DF2_EN). Likewise, when dynamically disabling record and/or digital filter channels with analog microphone inputs, the record and/or digital filter channels should be disabled first before disabling the analog microphone input.

If one or more AMICn_EN bits is set high while the device is in the software shutdown state, the configured analog microphone input channels are not enabled until the device transitions to the audio state. During this transition, the input common mode bias level of the analog microphone input amplifiers is automatically fast charged. However, the minimum required fast charge duration varies depending upon the size of the attached input coupling capacitor, and this can be configured for four common values with the AMIC_CT_SEL bit field. To prevent the automatic fast charging of a given input channel, set the respective AMICn_FAST_CHRG_BYPASS bit high prior to exiting the software shutdown state.

When an analog microphone input channel is dynamically enabled while the device is already in the audio state, the input common mode bias is not automatically fast charged. If fast charging is needed, to manually force it first set the respective fast charge force bit (AMICn_FAST_CHRG_FORCE) high prior to dynamically enabling that channel. Next, set the respective input channel enable bit (AMICn_EN) high. Finally, after an appropriate fast charge duration has elapsed (based on the attached input coupling capacitor), set the fast charge force bit low to transition to normal operation for that input channel.

If individual analog microphone inputs (pre-amplifier and ADC) need to be dynamically disabled to save power (independent of the remaining active inputs, and without disrupting the digital timing and phase alignment of the destination record or digital filter channels), leave the appropriate AMICn_EN bits set high and instead set the AMICn_PD bit high. This has the same effect as setting the AMICn_EN bit low except that the AMIC input source still provides zero code data to the microphone input channel and any active destination channels (record or digital filter).

To retain the common mode bias level (for currently unused analog microphone inputs when exiting software shutdown or after a given input is dynamically disabled), set the respective AMICn_PGA_HIZ_EN bit high prior to disabling the input channel or transitioning to/from the software shutdown state. This results in a slight increase in quiescent power, but it allows disabled analog microphone input channels (dynamically disabled or in software shutdown) to present a high impedance value over the entire full-scale input swing range. This allows an analog microphone input to share a single analog microphone with another device in the system (by presenting high impedance when the other device is using the microphone).

Analog Microphone Bias Generator

The device provides a regulated, low noise analog microphone bias generator that includes three separate voltage outputs. The analog microphone bias generator and the primary output (MICBIAS1) are enabled by setting the AMIC_BIAS_EN bit to 1. Once MICBIAS1 is enabled, the other two voltage outputs (MICBIAS2 and MICBIAS3) can also be enabled by setting the AMIC_BIAS_OUT2 and AMIC_BIAS_OUT3 bits to 1. Setting AMIC_BIAS_EN to 0 disables all three voltage outputs.

The analog microphone bias generator only operates when the MBVDD supply is powered. The voltage output level can then be configured to any of eight possible voltage levels (ranging from 1.2V up to 3V) with the AMIC_BIAS_SEL bit field. For the output voltage regulation to meet specifications, the MBVDD voltage level must exceed the minimum drop out voltage for the configured microphone bias output voltage level. The microphone bias generator can quickly charge up to a selected output level (either on enable, or if the AMIC_BIAS_SEL bit is dynamically changed from a lower setting to a higher setting while the AMIC bias is active). However, by default AMIC bias discharge is slower (on disable or dynamically from a higher level to a lower level). While this is not an issue when dynamically changing from a higher AMIC bias level to a lower one, this could be a problem if a fast turn off is required. For this scenario, the discharge speed on AMIC bias disable can be increased by setting the AMIC_BIAS_PD_EN bit to 1 (prior to disable).

By default, the analog microphone bias generator operates in low-noise mode. This operating mode minimizes output noise and is best used with microphones with very high SNR or with low-power supply rejection. An example of this is a typical electret condenser microphone (ECM) where the bias input and microphone output share the same connection. The microphone bias generator can instead be placed into lower power mode by setting the AMIC_BIAS_LP_MODE bit to 1. In this operating mode, bias voltage output noise is increased but quiescent power is significantly decreased. Microphone bias low-power mode is best used with microphones with sufficient power supply rejection to tolerate the increased output noise (such as typical analog and digital MEMs microphones).

Digital Microphone Interface

The device provides three separate digital microphone interfaces, each with a clock output and data input connection capable of supporting either a mono or stereo digital microphone connection. This allows for a maximum of six digital microphones to be connected to the device for different use case configurations. However, as the device only provides three microphone input channels, it supports concurrent record (in any given use case) from a maximum of three digital microphone channels (or a combined total of three channels split between analog and digital microphones).

Each of the three digital microphone interfaces can be independently enabled and disabled with the appropriate DMICn_EN bit, and each of the 6 DMIC input data channels can be routed to any of the three microphone input channels (as selected by the respective RECn_SEL bit field). Most digital microphones do not provide an enable/disable control input connection, and if the supply is connected it actively consumes power anytime it is clocked. To minimize inactive digital microphone power, whenever a given interface is disabled the clock output is gated and both the clock output and data input connections are placed in a high impedance state. Four different drive strength options are provided for the clock output of each interface, and the drive strength is configured with the respective DMICn_DRV bit field.

All three digital microphone interfaces share a single source clock, and the clock frequency (and therefore sample rate) is selected from three supported rates with the DMIC_RATE bit field. The three supported digital microphone interface clock frequencies vary depending on whether or not the device is operating from a bit clock that is an integer multiple of either a 48kHz (default) time base or a 44.1kHz time base.

Table 18. Supported Digital Microphone Interface Sample Rates
DMIC CLOCK RATE SETTING	BIT CLOCK ON A 48kHz TIME BASE	BIT CLOCK ON A 44.1kHz TIME BASE
DMIC_RATE = 0x0	f_DMIC = 768kHz	f_DMIC = 705.6kHz
DMIC_RATE = 0x1	f_DMIC = 1.536MHz	f_DMIC = 1.4112MHz
DMIC_RATE = 0x2	f_DMIC = 3.072MHz	f_DMIC = 2.8224MHz

The fastest digital microphone clock rate setting (DMIC_RATE = 0x2) provides the best performance when DMIC inputs are routed to the internal low-latency digital filter channels. While all three digital microphone clock rates are compatible with the PCM record channels, performance degrades as the DMIC to record channel sample rate ratio (over sampling ratio) decreases. Table 19 shows which DMIC clock rate settings are compatible with each channel and sample rate combination.

Table 19. Digital Microphone to Channel Sample Rate Combinations
DIGITAL MICROPHONE CLOCK RATE	DIGITAL FILTER CHANNEL SAMPLE RATE	PCM RECORD CHANNEL SAMPLE RATE
768kHz/705.6kHz	Not Recommended	f_S ≤ 16kHz
1.536MHz/1.4112MHz	Not Recommended	f_S ≤ 32kHz
3.072MHz/2.8224MHz	f_S = 96kHz/192kHz/384kHz	f_S ≤ 48kHz

Figure 23. Digital Microphone Input Channel Detailed Block Diagram

Digital Microphone Control Sequencing

Digital microphone interfaces can only be active when the device is in the audio state. The enable bits (DMICn_EN) are all located in the same register, and can be programmed in either the software shutdown state or dynamically in the audio state. When dynamically enabling record or digital filter channels with a digital microphone input, the digital microphone interface enable bits should be set first before setting the enable for (and later unmuting) either the destination record channel (RECn_PCM_EN) and/or the digital filter channel (DF1_EN or DF2_EN). Likewise, when dynamically disabling record and/or digital filter channels with digital microphone inputs, the record and/or digital filter channels should be first muted and then disabled before disabling the digital microphone input interface.

Digital Microphone Interface Frame Configuration

By default, a new digital microphone interface frame starts on a falling clock edge with data for interface channel 0 captured on the next rising edge and data for interface channel 1 captured on the next falling edge. If the DMIC_FRAME_SEL bit is set to 1, this is reversed with each new frame starting on a rising edge instead. When a digital microphone interface is connected to a stereo pair of digital microphones, it is critical that the two connected digital microphones be configured to use opposite edges for data output transmission to avoid contention.

All three digital microphone interfaces use the same frame start polarity (as selected by DMIC_FRAME_SEL). This ensures that data captured in the same frame from any of the three interfaces (and from either channel 0 or channel 1) is phase aligned internally when routed separately to different record or digital filter channels.

Figure 24. Digital Microphone Interface Default Frame Structure Example

Figure 25. Digital Microphone Interface Inverted Frame Structure Example

Record Channel Configuration

The device provides 4 record channels, each of which outputs audio data through the PCM interface. Three of the record channels (record channels 1, 2, and 3) directly accept microphone data (AMIC or DMIC) from the respective microphone input channel (microphone input channels 1, 2, and 3). The fourth record channel (record channel 4) provides a subset of digital stages and can only accept data from the playback channel monitor. The audio data in each channel is routed through the record channel filters and signal processing before reaching the PCM interface transmitter (DOUT).

Figure 26. Record Channel Detailed Block Diagram

Record Channel Control Sequencing

Record channels can only be active when the device is in the audio state. Each individual record channel is enabled and disabled with the respective record channel enable bit (RECn_PCM_EN). If one or more RECn_PCM_EN bit is set high while the device is in the software shutdown state, the selected record channels are not enabled until the device transitions to the audio state. Alternatively, the record channel enable bits may be set dynamically while the device is already in the audio state. To guarantee that input data is available, the respective input source channel (microphone and/or playback) should be enabled prior to enabling the destination record channel(s). Likewise, for dynamic disable sequencing, the record channel(s) should be disabled first before disabling the respective input source channel.

For static record channel enable (record channel configuration while in the software shutdown state), record channels are always phase aligned as long as all of the required record channels for a given use case have their respective enable bits (RECn_PCM_EN) set high prior to the device transitioning from the software shutdown state to the audio state. While in the software shutdown state, the record channels can be configured (or reconfigured) without any sequencing restrictions (as long as the audio enable bit is set last in the sequence).

To ensure record channel phase alignment for dynamic record channel enables (record channel configuration while in the active state), all of the channels needed for a given use case should be enabled at the same time. To facilitate this, the record channel enable bits (RECn_PCM_EN) are all located in the same register and can be programmed with a single command. If record channels are enabled dynamically at different times with separate write commands then channel phase alignment may not be preserved. Record channel enables should never be dynamically changed while any given record channel activation or deactivation is already in progress.

When the first enabled record channel (or channels) is active and ready for use (either through a dynamic or static enable), the device generates a REC_PWRUP_DONE_* interrupt event. A dynamic enable of additional record channels (when at least one channel is already active) does not generate additional interrupts. In this case, the host system does not receive an interrupt and should wait for the maximum turn-on time (for dynamic record channel enable) to expire before using the newly enabled record channel.

Record Channel Data Inversion

The output data from each record channel (1 through 4) can optionally be inverted by setting the respective RECn_INVERT bit to 1.

Record Channel DC Blocking Filters

A DC blocking filter can be individually enabled for each of the three primary record channels (record 1, 2, and 3) by setting the respective RECn_DCBLK_EN bit to 1. Record channel 4 (playback monitor channel) does not include the DC blocking filter function.

The DC blocking filter corner frequency is selected for each record channel with the respective RECn_DCBLK bit field, and the corner frequency scales with the record sample rate. The higher corner frequency setting reduces audio band flatness but results in faster settling times for record channel enables.

Record Channel Digital Volume Control

The three primary record channels (record 1, 2, and 3) include a programmable digital volume control. Record channel 4 (playback monitor channel) does not include a digital volume control. The record channel digital volume controls provide an attenuation range of 0dB to -63.5dB in 0.5dB steps, and is configured with the respective RECn_VOL bit field. Record channel volume should not be changed while the channel is active.

Record Channel Digital Gain Adjust

The three primary record channels (record 1, 2, and 3) include a programmable digital gain adjustment. Record channel 4 (playback monitor channel) does not include the digital gain adjustment. The record channel digital gain adjustment provides a gain range of 0dB to +31dB in 1dB steps, and is programmed by channel with the respective RECn_GAIN bit field. The record gain adjust is provided for use cases where a positive record channel gain offset is required, and is commonly required with digital microphone inputs (to match the full-scale input signal level to the full scale of the record channel). The record channel gain adjust setting should not be changed while the respective record channel is active.

Record Channel Delay Stage

The record channel delay stage can individually add from 0 to 7.5 samples of delay to each record channel, and is configured with the respective RECn_DELAY bit field. The record channel delay stage is positioned between the first and second stage of record channel decimation filters. At this point in the record filter chain, the data sample rate is determine by the selected internal DSP sample rate (as set by DSP_SR bit, regardless of the selected PCM record channel sample rate). As a result, record channel delay is configured in terms of the number of samples at this selected internal DSP sample rate (DSP_SR) rather than in terms of the record channel output sample rate (PCM_REC_SR).

The only exception occurs when the record channel sample rate (PCM_REC_SR) is set to 32kHz, and the DSP sample rate (DSP_SR) is set to 96kHz. In this case, the maximum record channel delay is limited to 3.5 samples (and all settings of RECn_DELAY above this are limited to this value).

Internal Digital Filter Channel Configuration

The device provides two internal low-latency digital filter channels denoted respectively as the digital filter channel 1 (DF1) and digital filter channel 2 (DF2). The two channels are functionally identical and are used to support a variety of applications. These include noise cancellation applications (feed-forward, feedback, and hybrid filter profiles), both voice and ambient enhancement applications, transparency applications, and traditional sidetone applications. In addition, a third internal digital filter channel called the playback compensation channel (PBC) is provided in the playback channel. This channel is optimized for (but not limited to) implementing music/voice compensation and/or general feedback compensation filters.

The enable/disable controls, mute toggles, and bank switch controls for all three internal digital channels are placed in the same register (by function). Any programming changes initiated by a single register write command results in a synchronized response across all active internal digital filter channels (affected by the command). The banked DF1, DF2, and PBC channel and filter structure is designed to support dynamic or adaptive filter changes and use case transitions without disruption to active audio playback.

Figure 27. Internal Playback Compensation and Low-Latency Digital Filter Channels

Low-Latency Digital Filter Channel 1 (DF1) and Channel 2 (DF2) Configuration

The 2 low-latency digital filter channels contain the same functional blocks, and can be independently and dynamically enabled with the DF1_EN and DF2_EN bits. The digital filter channel enables are in the same register as the playback compensation channel enable (PBC_EN), and if any of the three enable bits are changed simultaneously with a single write command, the start of the enable (unmute) or disable (mute) action is synchronized across all channels (that are affected by the command).

Digital filter channel 1 can accept data from either microphone input channel 1 or channel 3, and the input data source is selected with the DF1_SEL bit. Likewise, digital filter channel 2 can accept data from microphone input channel 2 or channel 3, and the input data source is instead selected with the DF2_SEL bit. The low-latency digital filter channels both operate at the same sample rate, which is configured with the system level DSP_SR bit field.

The low-latency digital filter channels each provide two banks that can be dynamically swapped, and a subset of the DF1/DF2 register settings (12-band biquad filter coefficients, gain adjust level, and digital volume setting) are duplicated in each bank. The digital filter channel bank selection bits (DF1_BQ_BK_SEL and DF2_BQ_BK_SEL) are used to either select the active bank (prior to enabling the digital filter channel) or to dynamically switch the active bank (while the digital filter channel is active).

A dynamic bank switch temporarily requires additional processing, and as a result this feature is not supported when the digital filter channels are operating at the highest sample rate of 384kHz (as set by the DSP_SR bit). Attempting a dynamic bank swap when operating at a 384khz sample rate could result in an audible glitch. Instead (when operating at 384kHz), a dynamic bank swap can still be accomplished by first muting and disabling the digital filter channel (and active bank), then selecting the inactive bank, and finally by re-enabling and unmuting the channel.

Table 20. Low-Latency Digital FIlter Channel Dynamic Bank Select Restrictions
DIGITAL FILTER CHANNEL PARAMETER	CONFIGURATION SUPPORT
Channel Sample Rate (DSP_SR)	f_S = 96kHz	f_S = 192kHz	f_S = 384kHz
Dynamic Active Bank Switch Supported	Yes	Yes	No

As with the enable bits, the digital filter channel bank select controls are also in the same register as the playback compensation channel bank select control (PBC_BQ_BK_SEL). If any of the three bank select bits are dynamically changed simultaneously with a single write command, the bank switch action is synchronized across all active channels (that are affected by the command). While some bank specific register controls are restricted and cannot be changed for the currently active bank, the inactive bank controls can be programmed fully at any time.

Figure 28. Low-Latency Digital Filter Channel 1 and 2 Detailed Block Diagram

DF1/DF2 Channel Ultrasound Polyphase Elliptical Filter

Low-latency digital filter channels 1 and 2 each feature a fully programmable, 9th order polyphase elliptical all-pass filter. This filter is provided primarily for use cases requiring a high-order ultrasound filter, and can be enabled for the digital filter channels with the DF1_ULTRA_EN and DF2_ULTRA_EN bits respectively. Enabling the ultrasound filter results in increased channel latency (both baseline and based on the filter configuration). Furthermore, due to the increased processing required when the ultrasound filters in both channels are active, the record channel cannot have more than two channels active concurrently with them.

The nine ultrasound filter coefficients can be independently programmed for digital filter channels 1 and 2, and each individual coefficient is 3 bytes (24 bits) long. Each set of three registers (per coefficient) must be programmed consecutively for the settings to take effect. The coefficients are stored using a signed two’s complement format where the first 4 bits are the integer portion and the last 20 bits are the decimal portion (which results in an approximate +8 to -8 range for each coefficient). The ultrasound filter structure and coefficient placement is illustrated in Figure 29.

Figure 29. Low-Latency Digital Filter Channel Ultrasound Filter Structure

DF1/DF2 Channel Ultrasound Filter Coefficient Registers

The low-latency digital filter channels each contain a 9th order polyphase elliptical all-pass filter. The register structure for each coefficient is identical and repeated.

Each coefficient is sequentially placed in the register map covering a total of 36 addresses per digital filter channel. Within this structure, each individual coefficient spans four addresses, the first of which is blank followed by the three addresses that make up the 24-bit coefficient (lowest bits, middle bits, and highest bits in that order). Coefficient segments must be consecutively written for the new settings to take effect, but blank addresses may be skipped or written with any value as needed (when creating a programming sequence). All coefficients can be programmed when the device is in software shutdown, but should not be programmed while the ultrasound filter in a given digital filter channel is active.

Table 21 shows the address space where the coefficients for each digital filter channel are placed in the device register space.

Table 21. Ultrasound Filter Register Address Ranges
CHANNEL	START ADDRESS	END ADDRESS
Digital Filter Channel 1	0x2100	0x2123
Digital Filter Channel 2	0x2140	0x2163

Table 22 and Table 23 show the register address locations for each ultrasound filter coefficient for each of the respective digital filter channels.

Table 22. Digital Filter Channel 1 Ultrasound Filter Coefficient Register Addresses
COEFFICIENT	BLANK REGISTER	BITS [7:0] REGISTER	BITS [15:8] REGISTER	BITS [23:16] REGISTER
1	0x2100	0x2101	0x2102	0x2103
2	0x2104	0x2105	0x2106	0x2107
3	0x2108	0x2109	0x210A	0x210B
4	0x210C	0x210D	0x210E	0x210F
5	0x2110	0x2111	0x2112	0x2113
6	0x2114	0x2115	0x2116	0x2117
7	0x2118	0x2119	0x211A	0x211B
8	0x211C	0x211D	0x211E	0x211F
9	0x2120	0x2121	0x2122	0x2123
Blank	0x2124 to 0x213F

Table 23. Digital Filter Channel 2 Ultrasound Filter Coefficient Register Addresses
COEFFICIENT	BLANK REGISTER	BITS [7:0] REGISTER	BITS [15:8] REGISTER	BITS [23:16] REGISTER
1	0x2140	0x2141	0x2142	0x2143
2	0x2144	0x2145	0x2146	0x2147
3	0x2148	0x2149	0x214A	0x214B
4	0x214C	0x214D	0x214E	0x214F
5	0x2150	0x2151	0x2152	0x2153
6	0x2154	0x2155	0x2156	0x2157
7	0x2158	0x2159	0x215A	0x215B
8	0x215C	0x215D	0x215E	0x215F
9	0x2160	0x2161	0x2162	0x2163
Blank	0x2164 to 0x21FF

DF1/DF2 Channel Ultrasound Filter Example Coefficients

Six example ultrasound filter implementations are provided for each of the three supported digital filter channel sample rate options. For each supported sample rate, the examples provided have three different levels of stopband attenuation (-20dB, -40dB, and -60dB) and are provided for both a low cutoff frequency (approximate f_C ≈ 24kHz to 26kHz) and a higher cutoff frequency (approximate f_C ≈ 30kHz to 32kHz). Generally, as ultrasound filter stopband attenuation is increased, the latency of the implemented filter is also increased.

Table 24. Example Ultrasound Filters for f_S = 384kHz with Low Cutoff Frequencies
FILTER PARAMETER	FILTER CONFIGURATION
Cutoff Frequency	22.9kHz	22.5kHz	22.3kHz
Stopband Frequency	24.1kHz	24.2kHz	24.3kHz
Stopband Attenuation	-20dB	-40dB	-60dB
Coeficient B0 Value	0x0CAD01	0x0FAD3B	0x0F3665
Coeficient B1 Value	0xE531C9	0xE26DDC	0xE2AD5F
Coeficient B2 Value	0x100000	0x0C3F03	0x0C8470
Coeficient B3 Value	0x100000	0xE4E90D	0xE43CD8
Coeficient B4 Value	0x0F7454	0x0E9573	0x0FCAE8
Coeficient B5 Value	0xE2B8E3	0xE33EA6	0xE24A01
Coeficient B6 Value	0x100000	0x100000	0x0E1FD4
Coeficient B7 Value	0x100000	0x100000	0xE35139
Coeficient B8 Value	0xF4A53D	0xF31F18	0xF2623D

Table 25. Example Ultrasound Filters for f_S = 384kHz with High Cutoff Frequencies
FILTER PARAMETER	FILTER CONFIGURATION
Cutoff Frequency	29.1kHz	28.7kHz	28.4kHz
Stopband Frequency	30.7kHz	30.8kHz	30.9kHz
Stopband Attenuation	-20dB	-40dB	-60dB
Coeficient B0 Value	0x0BEF71	0x0F986B	0x0F042C
Coeficient B1 Value	0xE6FEC5	0xE3C81B	0xE4022E
Coeficient B2 Value	0x100000	0x0B6525	0x0BB38D
Coeficient B3 Value	0x100000	0xE66C42	0xE57E28
Coeficient B4 Value	0x0F51A9	0x0E3D4B	0x0FBD79
Coeficient B5 Value	0xE4299A	0xE4AC67	0xE39A30
Coeficient B6 Value	0x100000	0x100000	0x0DAB2A
Coeficient B7 Value	0x100000	0x100000	0xE4A0A8
Coeficient B8 Value	0xF5B820	0xF3E4A2	0xF2FDEE

Table 26. Example Ultrasound Filters for f_S= 192kHz with Low Cutoff Frequencies
FILTER PARAMETER	FILTER CONFIGURATION
Cutoff Frequency	22.9kHz	22.5kHz	22.8kHz
Stopband Frequency	24.0kHz	24.1kHz	28.0kHz
Stopband Attenuation	-20dB	-40dB	-60dB
Coeficient B0 Value	0x0A4D62	0x0F66F5	0x0EFD02
Coeficient B1 Value	0xEC541F	0xE8A6EC	0xE91AB5
Coeficient B2 Value	0x100000	0x0971F5	0x096DD2
Coeficient B3 Value	0x100000	0xEABB66	0xE9C6E4
Coeficient B4 Value	0x0F0044	0x0D6EB8	0x0C8C21
Coeficient B5 Value	0xE93E15	0xE96CA7	0xE9A46B
Coeficient B6 Value	0x100000	0x100000	0x100000
Coeficient B7 Value	0x100000	0x100000	0x100000
Coeficient B8 Value	0xF85198	0xF5D8E5	0xF4E487

Table 27. Example Ultrasound Filters for f_S = 192kHz with High Cutoff Frequencies
FILTER PARAMETER	FILTER CONFIGURATION
Cutoff Frequency	29.0kHz	28.6kHz	28.4kHz
Stopband Frequency	30.4kHz	30.5kHz	30.5kHz
Stopband Attenuation	-20dB	-40dB	-60dB
Coeficient B0 Value	0x0963F7	0x0F490A	0x0E4393
Coeficient B1 Value	0xF0B021	0xED54AF	0xED06B9
Coeficient B2 Value	0x100000	0x0843D2	0x0883C3
Coeficient B3 Value	0x100000	0xEE3198	0xEBE21F
Coeficient B4 Value	0x0ECFF0	0x0CF249	0x0F89CE
Coeficient B5 Value	0xEE07AD	0xEDBD21	0xED0565
Coeficient B6 Value	0x100000	0x100000	0x0BE92F
Coeficient B7 Value	0x100000	0x100000	0xEC9B63
Coeficient B8 Value	0xFA160F	0xF74017	0xF5BAFF

Table 28. Example Ultrasound Filters for f_S= 96kHz with Low Cutoff Frequencies
FILTER PARAMETER	FILTER CONFIGURATION
Cutoff Frequency	22.6kHz	23.3kHz	22.6kHz
Stopband Frequency	23.4kHz	27.3kHz	26.1kHz
Stopband Attenuation	-20dB	-40dB	-60dB
Coeficient B0 Value	0x082BBC	0x061BB0	0x0E8754
Coeficient B1 Value	0xFD0F31	0xFAB98D	0xFCE546
Coeficient B2 Value	0x100000	0x100000	0x05C22F
Coeficient B3 Value	0x100000	0x100000	0xF5E252
Coeficient B4 Value	0x0E8E5A	0x0D1A19	0x0AE1CA
Coeficient B5 Value	0xFD352D	0xFE1FAE	0xFA7F38
Coeficient B6 Value	0x100000	0x100000	0x100000
Coeficient B7 Value	0x100000	0x100000	0x100000
Coeficient B8 Value	0xFE6733	0xFBD99C	0xF97944

Table 29. Example Ultrasound Filters for f_S = 96kHz with High Cutoff Frequencies
FILTER PARAMETER	FILTER CONFIGURATION
Cutoff Frequency	28.6kHz	29.2kHz	28.6kHz
Stopband Frequency	29.4kHz	32.8kHz	31.8kHz
Stopband Attenuation	-20dB	-40dB	-60dB
Coeficient B0 Value	0x08582E	0x05FCA8	0x0E948E
Coeficient B1 Value	0x068144	0x035588	0x08BE0C
Coeficient B2 Value	0x100000	0x100000	0x04EF35
Coeficient B3 Value	0x100000	0x100000	0xFDC25B
Coeficient B4 Value	0x0E9CB7	0x0D3C61	0x0ADDA8
Coeficient B5 Value	0x090B05	0x095A64	0x05011D
Coeficient B6 Value	0x100000	0x100000	0x100000
Coeficient B7 Value	0x100000	0x100000	0x100000
Coeficient B8 Value	0x018FCE	0xFEEC70	0xFC4EAF

DF1/DF2 Channel 12-Band Biquad Filter

The low-latency digital filter channels each feature a banked 12-band filter where each band is a full, individually programmable digital biquad filter. The biquad filter can be enabled (and the number of active bands selected) by the digital filter channel and bank with the DF1_BQ_EN_BKn and DF2_BQ_EN_BKn bit fields (where n is A for bank A and B for bank B). Each channel and bank can be configured to have from 0 to 12 bands active, and inactive bands do not consume additional quiescent power. The gain (A), quality factor (Q), and frequency (f₀) limitations by biquad band vary by implemented filter type, and are described in the Electrical Characteristics Table.

The transfer function for biquad band is defined as:

$H (z) = \frac{(B_{0} + B_{1} z^{-1} + B_{2} z^{-2})}{(A_{0} + A_{1} z^{-1} + A_{2} z^{-2})}$

The biquad filter in each band has five user-programmable coefficients (B0, B1, B2, A1, and A2 with A0 fixed at 1), and each individual coefficient is 3 bytes (24 bits) long. Each set of three registers (per coefficient) must be programmed consecutively (in order) for the settings to take effect. The coefficients are stored using a signed two’s complement format where the first 2 bits are the integer portion and the last 22 bits are the decimal portion (which results in an approximate +2 to -2 range for each coefficient). This coefficient range and resolution allows for the implementation of several common filter types including peaking filters, high and low pass filters, and high and low shelving filters. The 2.22 format is a fixed point coefficient implementation that results in some range and resolution boundary limits for filter parameters (see the Biquad Filter Characteristics in the Electrical Characteristics Table).

The biquad filter coefficient register bits are uninitialized when the device first powers up, and the coefficients for any given channel, bank, and biquad band should be fully programmed before being enabled. The biquad filter coefficients can be freely written and read back when the device is in software shutdown (AUDIO_EN = 0) or when the respective digital filter channel (DF1 or DF2) is disabled (DF1_EN or DF2_EN set to 0). However, once enabled only inactive biquad banks and bands can be safely written (for example DF1 bank B can be written freely while DF1 bank A is enabled). Readback is restricted by channel enable, and attempting to read back the coefficients for either digital filter channel 1 or 2 while the respective channel is enabled and active may return all zero values.

DF1/DF2 Channel Biquad Filter Coefficient Registers

The low-latency digital filter channels each contain a 12-band biquad filter. Each of the filter bands and coefficients are duplicated over two banks to allow for the inactive bank to be dynamically updated (prior to initiating a bank swap for smooth filter profile transitions). The register structure for each band (and the five coefficients within each) is identical and repeated.

The coefficients of each band are sequentially placed in the same order in the register map (B0, B1, B2, A1, A2) for a total of 20 addresses per filter band. Within this structure, each coefficient spans four addresses, the first of which is blank followed by the three addresses that make up the 24-bit coefficient (lowest bits, middle bits, and highest bits in order). Coefficient segments must be consecutively written for the new settings to take effect, but blank addresses may be skipped or written with any value as needed (when creating a programming sequence). All coefficients can be programmed when the device is in software shutdown, but only inactive banks can be safely programmed while a given digital filter channel is active.

Table 30 shows the address space where the coefficients for each digital filter channel and bank are placed in the device register space.

Table 30. Digital Filter Channel Biquad Filter Register Address Ranges
CHANNEL	BANK	START ADDRESS	END ADDRESS
Digital Filter Channel 1	A	0x2400	0x24FF
Digital Filter Channel 1	B	0x2500	0x25FF
Digital Filter Channel 2	A	0x2600	0x26FF
Digital Filter Channel 2	B	0x2700	0x27FF

Table 31 shows how each filter band and coefficient are structured in the register space for each of the respective channels and banks. The underscore denotes where to insert the appropriate value (4, 5, 6, or 7) depending on which digital filter channel (1 or 2) and bank (A or B) are being programmed or read back.

Table 31. Digital Filter Channel and Bank Biquad Filter Coefficient Register Addresses
FILTER BAND	FILTER COEFFICIENT	BLANK REGISTER	BITS [7:0] REGISTER	BITS [15:8] REGISTER	BITS [23:16] REGISTER
1	B0	0x2_00	0x2_01	0x2_02	0x2_03
	B1	0x2_04	0x2_05	0x2_06	0x2_07
	B2	0x2_08	0x2_09	0x2_0A	0x2_0B
	A1	0x2_0C	0x2_0D	0x2_0E	0x2_0F
	A2	0x2_10	0x2_11	0x2_12	0x2_13
2	B0	0x2_14	0x2_15	0x2_16	0x2_17
	B1	0x2_18	0x2_19	0x2_1A	0x2_1B
	B2	0x2_1C	0x2_1D	0x2_1E	0x2_1F
	A1	0x2_20	0x2_21	0x2_22	0x2_23
	A2	0x2_24	0x2_25	0x2_26	0x2_27
3	B0	0x2_28	0x2_29	0x2_2A	0x2_2B
	B1	0x2_2C	0x2_2D	0x2_2E	0x2_2F
	B2	0x2_30	0x2_31	0x2_32	0x2_33
	A1	0x2_34	0x2_35	0x2_36	0x2_37
	A2	0x2_38	0x2_39	0x2_3A	0x2_3B
4	B0	0x2_3C	0x2_3D	0x2_3E	0x2_3F
	B1	0x2_40	0x2_41	0x2_42	0x2_43
	B2	0x2_44	0x2_45	0x2_46	0x2_47
	A1	0x2_48	0x2_49	0x2_4A	0x2_4B
	A2	0x2_4C	0x2_4D	0x2_4E	0x2_4F
5	B0	0x2_50	0x2_51	0x2_52	0x2_53
	B1	0x2_54	0x2_55	0x2_56	0x2_57
	B2	0x2_58	0x2_59	0x2_5A	0x2_5B
	A1	0x2_5C	0x2_5D	0x2_5E	0x2_5F
	A2	0x2_60	0x2_61	0x2_62	0x2_63
6	B0	0x2_64	0x2_65	0x2_66	0x2_67
	B1	0x2_68	0x2_69	0x2_6A	0x2_6B
	B2	0x2_6C	0x2_6D	0x2_6E	0x2_6F
	A1	0x2_70	0x2_71	0x2_72	0x2_73
	A2	0x2_74	0x2_75	0x2_76	0x2_77
7	B0	0x2_78	0x2_79	0x2_7A	0x2_7B
	B1	0x2_7C	0x2_7D	0x2_7E	0x2_7F
	B2	0x2_80	0x2_81	0x2_82	0x2_83
	A1	0x2_84	0x2_85	0x2_86	0x2_87
	A2	0x2_88	0x2_89	0x2_8A	0x2_8B
8	B0	0x2_8C	0x2_8D	0x2_8E	0x2_8F
	B1	0x2_90	0x2_91	0x2_92	0x2_93
	B2	0x2_94	0x2_95	0x2_96	0x2_97
	A1	0x2_98	0x2_99	0x2_9A	0x2_9B
	A2	0x2_9C	0x2_9D	0x2_9E	0x2_9F
9	B0	0x2_A0	0x2_A1	0x2_A2	0x2_A3
	B1	0x2_A4	0x2_A5	0x2_A6	0x2_A7
	B2	0x2_A8	0x2_A9	0x2_AA	0x2_AB
	A1	0x2_AC	0x2_AD	0x2_AE	0x2_AF
	A2	0x2_B0	0x2_B1	0x2_B2	0x2_B3
10	B0	0x2_B4	0x2_B5	0x2_B6	0x2_B7
	B1	0x2_B8	0x2_B9	0x2_BA	0x2_BB
	B2	0x2_BC	0x2_BD	0x2_BE	0x2_BF
	A1	0x2_C0	0x2_C1	0x2_C2	0x2_C3
	A2	0x2_C4	0x2_C5	0x2_C6	0x2_C7
11	B0	0x2_C8	0x2_C9	0x2_CA	0x2_CB
	B1	0x2_CC	0x2_CD	0x2_CE	0x2_CF
	B2	0x2_D0	0x2_D1	0x2_D2	0x2_D3
	A1	0x2_D4	0x2_D5	0x2_D6	0x2_D7
	A2	0x2_D8	0x2_D9	0x2_DA	0x2_DB
12	B0	0x2_DC	0x2_DD	0x2_DE	0x2_DF
	B1	0x2_E0	0x2_E1	0x2_E2	0x2_E3
	B2	0x2_E4	0x2_E5	0x2_E6	0x2_E7
	A1	0x2_E8	0x2_E9	0x2_EA	0x2_EB
	A2	0x2_EC	0x2_ED	0x2_EE	0x2_EF
Blank	-	0x2_F0 to 0x2_FF

DF1/DF2 Channel DC Blocking Filter

Low-latency digital filter channels 1 and 2 provide a DC blocking filter that can be enabled by setting the DF1_DCBLK_EN and DF2_DCBLK_EN bits to 1. The respective DC blocking filter corner frequencies are selected with the DF1_DCBLK and DF2_DCBLK bit fields. The configured corner frequency for each setting depends on the digital filter channel sample rate (DSP_SR) selected. The higher corner frequency settings reduce low-frequency audio band flatness, but result in faster settling times after digital filter channel enable.

DF1/DF2 Channel Digital Gain Adjust

The low-latency digital filter channels include a banked, programmable coarse digital gain adjustment. The digital filter channel digital gain adjustment provides a gain range of 0dB to +42dB in 6dB steps, and is programmed individually by channel and bank with the DF1_GAIN_BKn and DF2_GAIN_BKn bit fields (where n is A for bank A and B for bank B). The digital filter channel gain adjust is provided for use cases where a large positive gain offset is required, and should not be changed while the respective digital filter channel and bank is active.

DF1/DF2 Channel Digital Volume Control

The low-latency digital filter channels include a banked, dynamically programmable digital volume control. The digital volume control provides an attenuation range of 0dB to -31.5dB in 0.5dB steps, and is configured individually by channel and bank with the DF1_VOL_BKn and DF2_VOL_BKn bit fields (where n is A for bank A and B for bank B).

A digital mute is also provided for each digital filter channel, and is enabled with the DF1_VOL_MUTE and DF2_VOL_MUTE bits respectively. The digital filter and playback compensation channel mutes are all in the same register, and if any of the channel mute bits are changed simultaneously with a single write command the start of the mute or unmute action (and volume ramp if enabled) is synchronized across all affected channels.

When enabled, digital volume ramping occurs during digital filter channel startup, dynamic bank changes, volume changes, and digital mute toggling. Digital filter channel volume ramping can be dynamically enabled and disabled with the DF1_VOL_RMP_EN and DF2_VOL_RMP_EN bits, however the setting should never be changed while a volume ramp is in progress. For matched behavior and channel latency between the two channels, volume ramping should always be either enabled for both channels or disabled for both channels. When a volume ramp is complete, the device generates the appropriate ramp done interrupt (DF1_RMP_DONE_* and DF2_RMP_DONE_*). The duration of a given volume ramp is selected with the DF1_VOL_RMP_RATE and DF2_VOL_RMP_RATE bit fields respectively. Depending on the type of audio content and the characteristics of the speaker load, selecting faster ramp rates (typically those less than 32ms) or disabling ramping entirely can potentially result in audible glitches during volume changes.

DF1/DF2 Channel Dynamic Range Compression (DRC) and Limiter Stage

The low-latency digital filter channels include a flexible dynamic range compressor (DRC) and limiter stage that is enabled by channel with the DF1_DRC_EN and DF2_DRC_EN bits. The DRC/limiter stage features a programmable compression ratio, activation threshold, and attack and release time weighting factors.

When the digital filter channel DRC/limiter stage is enabled, if the signal (which is monitored with a running RMS level calculation) exceeds the configured compression threshold, the channel gain is reduced by the selected compression ratio. The compression threshold is programmable from a range of -62dBFS RMS to 0dBFS RMS, and the threshold is configured with the DF1_DRC_THR and DF2_DRC_THR bit fields. The compression ratio is also programmable with a limited number of settings covering a finite range from 2:1 up to 60:1, and is selected with the DF1_DRC_CMP and DF2_DRC_CMP bit fields. In addition, an infinite compression ratio setting is provided that effectively transforms the DRC stage into a signal limiter stage.

To determine the attack and release response, the channel DRC/Limiter stage internally uses a running RMS level calculation. The calculated RMS level is then compared to the configured compression threshold. This running RMS level calculation includes a weighting factor α (sometimes called a forgetting factor) that determines the relative weighting (or ratio) of the absolute signal level and the current RMS level result that is used to calculate the next RMS level result.

Each digital filter channel provides a separate attack weighting factor and release weighting factor setting for the RMS level calculations. The attack weighting factor (α_ATK) for a given channel is configured with the DF1_DRC_ATK_WF and DF2_DRC_ATK_WF bit fields. Likewise, the release weighting factor (α_RLS) for a given channel is configured with the DF1_DRC_RLS_WF and DF2_DRC_RLS_WF bit fields.

This RMS level calculation effectively sets the DRC attack time constant (t_{DRC_ATK}) and release time constant (t_{DRC_RLS}). To configure the desired DRC attack and release time constants relative to the configured digital filter channel sample rate (f_{S_DF} as set by DSP_SR), use the following equations to calculate the appropriate attack weighting factor and release weighting factor.

Attack Time Constant Calculation: α_ATK = (64 x 2¹⁶) / (f_{S_DF} x t_{DRC_ATK} + 1)

Release Time Constant Calculation: α_RLS = (64 x 2¹⁶) / (f_{S_DF} x t_{DRC_RLS} + 1)

The digital filter channel DRC/limiter stage also supports instant attack and release responses. The DF1_DRC_INST_ATK and DF2_DRC_INST_ATK bits are used to enable instant attack mode (by channel), while the DF1_DRC_INST_RLS and DF2_DRC_INST_RLS bits are used to enable instant release mode (by channel).

DF1/DF2 Channel DRC and Limiter Stage RMS Level Calculations

Each time a new data sample enters the digital filter channel DRC/limiter stage, the block must determine whether to attack or release. To do this, it must calculate the next RMS level value (V_RMS(N)) and this is done in multiple steps as follows.

Step 1:

The attack calculation is made using the attack weighting factor:

V_{RMS_ATK}(N) = (V_ABSOLUTE(N) x α_ATK) + (V_{RMS_ATK}(N-1) x (1- α_ATK))

If instant attack mode is enabled, the absolute value is used directly instead of the above calculation:

V_{RMS_ATK}(N) = V_ABSOLUTE(N)

Step 2:

If V_{RMS_ATK}(N) is greater than the previous RMS level value (V_RMS(N-1)), then attack is selected and V_{RMS_ATK}(N) is used as the next RMS level value (V_RMS(N)).

V_RMS(N) = V_{RMS_ATK}(N)

If V_{RMS_ATK}(N) is not greater than V_RMS(N-1), then release is selected and the calculation proceeds to step 3.

Step 3:

The release calculation is made using the release weighting factor:

V_{RMS_RLS}(N) = (V_{RMS_ATK}(N) x α_RLS) + (V_RMS(N-1) x (1- α_RLS))

Note that the release calculation uses the result of the attack calculation. If instant attack mode is enabled, then the attack weighting factor must be set to the maximum value (0xFFFF) to allow for accurate release calculations.

If instant release mode is enabled, the result of the attack calculation is used directly instead of the release calculation:

V_{RMS_RLS}(N) = V_{RMS_ATK}(N)

The next RMS level value is defined as equal to the result:

V_RMS(N) = V_{RMS_RLS}(N)

Playback Compensation (PBC) Digital Filter Channel

The playback compensation (PBC) digital filter channel is part of the playback channel, and can be dynamically enabled with the PBC_EN bit. The playback compensation channel enable is in the same register as the low-latency digital filter channel 1 and 2 enables (DF1_EN and DF2_EN), and if any of these enable bits are changed simultaneously with a single write command the start of the enable or disable action is synchronized across all active channels (that are affected by the command).

The playback compensation channel only accepts data from the playback channel, and as a result it operates at the same sample rate as the playback channel (as configured with the PCM_PB_SR bit field).

The playback compensation channel provides two banks (bank A and bank B) that can be dynamically swapped, and all channel functional blocks and register settings are duplicated in each bank. The PBC_BK_SEL bit is used to either select the active bank (prior to enabling the channel) or to dynamically switch the active bank (while the channel is active). A dynamic bank switch temporarily requires additional processing, and as a result the maximum number of active playback compensation biquad channels is limited at the highest playback sample rate of 192kHz (as set by the PCM_PB_SR bit). Attempting a dynamic bank swap when the limits are exceeded (as shown in Table 32) could result in an audible glitch. Instead, in this case a bank swap can still be accomplished by first muting and disabling the channel (and active bank), then selecting the inactive bank, and finally by re-enabling and unmuting the channel.

Table 32. Playback Compensation Channel Dynamic Bank Select Restrictions
FILTER PARAMETER	FILTER CONFIGURATION
Sample Rate (PCM_PB_SR)	f_S ≤ 96kHz	f_S = 176.4kHz or 192kHz
5-Band Playback Equalizer Enabled	N/A	Yes	No
Number of Active PBC Biquad Bands	All 10 Bands	7 Bands Maximum	9 Bands Maximum

The playback compensation channel bank select control is in the same register as the low-latency digital filter channel 1 and 2 bank select controls (DF1_BQ_BK_SEL and DF2_BQ_BK_SEL). If any of these bank select bits are dynamically changed simultaneously with a single write command, the start of the bank switch action is synchronized across all active channels (that are affected by the command).

While some playback compensation channel bank specific register controls are restricted and cannot be changed for the currently active bank, the inactive bank controls can be programmed fully at any time.

Figure 30. Playback Compensation Channel Detailed Block Diagram

PBC Channel 10-Band Biquad Filter

The playback compensation digital filter channel features a banked 10-band filter where each band is a full, individually programmable digital biquad filter. The biquad filter can be configured by bank with the PBC_BQ_EN_BKA and PBC_BQ_EN_BKB bit fields. Each bank can be configured to have from 0 to 10 bands active, and inactive bands do not consume additional quiescent power. The gain (A), quality factor (Q), and frequency (f₀) limitations by biquad band vary by implemented filter type, and are described in the Electrical Characteristics Table.

The transfer function for each biquad band is defined as:

$H (z) = \frac{(B_{0} + B_{1} Z^{-1} + B_{2} Z^{-2})}{(A_{0} + A_{1} Z^{-1} + A_{2} Z^{-2})}$

The biquad filter in each band has five user-programmable coefficients (B0, B1, B2, A1, and A2 with A0 fixed at 1), and each individual coefficient is 3 bytes (24 bits) long. Each set of three registers (per coefficient) must be programmed consecutively for the settings to take effect. The coefficients are stored using a signed two’s complement format where the first 2 bits are the integer portion and the last 22 bits are the decimal portion (which results in an approximate +2 to -2 range for each coefficient). This coefficient range and resolution allows for the implementation of several common filter types including peaking filters, high and low pass filters, and high and low shelving filters. The 2.22 format is a fixed point coefficient implementation that results in some range and resolution boundary limits for filter parameters (see the Biquad Filter Characteristics in the Electrical Characteristics Table).

The biquad filter coefficient register bits are uninitialized when the device first powers up, and the coefficients for any given bank and biquad band should be fully programmed before that band is enabled. The biquad filter coefficients can be freely written and read back when the device is in software shutdown (AUDIO_EN = 0) or when the playback channel is disabled (PB_EN = 0). However, once the playback channel is enabled, only the inactive bank and bands can be safely written (for example PBC bank B can be written freely while PBC bank A is enabled). Readback is restricted by the overall playback channel enable, and attempting to read back the coefficients for the playback compensation channel while the playback channel is enabled and active may return all zero values.

PBC Channel Biquad Filter Coefficient Registers

The playback compensation (PBC) digital filter channel contains a 10-band biquad filter. Each of the filter bands and coefficients are duplicated over two banks to allow for the inactive bank to be dynamically updated (prior to initiating a bank swap for smooth filter profile transitions). The register structure for each band (and the 5 coefficients within each) is identical and repeated.

The coefficients in each band are sequentially placed in the same order in the register map (B0, B1, B2, A1, A2) for a total of 20 addresses per filter band. Within this structure, each coefficient spans four addresses, the first of which is blank followed by the three addresses that make up the 24-bit coefficient (lowest bits, middle bits, and highest bits in order). Coefficient segments must be consecutively written for the new settings to take effect, but blank addresses may be skipped or written with any value as needed (when creating a programming sequence). All coefficients can be programmed when the device is in software shutdown, but only the inactive bank can be safely programmed while the playback compensation channel is active.

Table 33 shows the address space where the coefficients for the channel are placed in the device register space.

Table 33. Playback Compensation Channel Biquad Filter Register Addresses
CHANNEL	BANK	START ADDRESS	END ADDRESS
Playback Compensation Channel	A	0x2264	0x232B
Playback Compensation Channel	B	0x232C	0x23F3

Table 34 shows how each filter band and coefficient is structured in the register space for the playback compensation channel bank A.

Table 34. Playback Compensation Channel Biquad Filter Bank A Coefficient Register Addresses
FILTER BAND	FILTER COEFFICIENT	BLANK REGISTER	BITS [7:0] REGISTER	BITS [15:8] REGISTER	BITS [23:16] REGISTER
1	B0	0x2264	0x2265	0x2266	0x2267
	B1	0x2268	0x2269	0x226A	0x226B
	B2	0x226C	0x226D	0x226E	0x226F
	A1	0x2270	0x2271	0x2272	0x2273
	A2	0x2274	0x2275	0x2276	0x2277
2	B0	0x2278	0x2279	0x227A	0x227B
	B1	0x227C	0x227D	0x227E	0x227F
	B2	0x2280	0x2281	0x2282	0x2283
	A1	0x2284	0x2285	0x2286	0x2287
	A2	0x2288	0x2289	0x228A	0x228B
3	B0	0x228C	0x228D	0x228E	0x228F
	B1	0x2290	0x2291	0x2292	0x2293
	B2	0x2294	0x2295	0x2296	0x2297
	A1	0x2298	0x2299	0x229A	0x229B
	A2	0x229C	0x229D	0x229E	0x229F
4	B0	0x22A0	0x22A1	0x22A2	0x22A3
	B1	0x22A4	0x22A5	0x22A6	0x22A7
	B2	0x22A8	0x22A9	0x22AA	0x22AB
	A1	0x22AC	0x22AD	0x22AE	0x22AF
	A2	0x22B0	0x22B1	0x22B2	0x22B3
5	B0	0x22B4	0x22B5	0x22B6	0x22B7
	B1	0x22B8	0x22B9	0x22BA	0x22BB
	B2	0x22BC	0x22BD	0x22BE	0x22BF
	A1	0x22C0	0x22C1	0x22C2	0x22C3
	A2	0x22C4	0x22C5	0x22C6	0x22C7
6	B0	0x22C8	0x22C9	0x22CA	0x22CB
	B1	0x22CC	0x22CD	0x22CE	0x22CF
	B2	0x22D0	0x22D1	0x22D2	0x22D3
	A1	0x22D4	0x22D5	0x22D6	0x22D7
	A2	0x22D8	0x22D9	0x22DA	0x22DB
7	B0	0x22DC	0x22DD	0x22DE	0x22DF
	B1	0x22E0	0x22E1	0x22E2	0x22E3
	B2	0x22E4	0x22E5	0x22E6	0x22E7
	A1	0x22E8	0x22E9	0x22EA	0x22EB
	A2	0x22EC	0x22ED	0x22EE	0x22EF
8	B0	0x22F0	0x22F1	0x22F2	0x22F3
	B1	0x22F4	0x22F5	0x22F6	0x22F7
	B2	0x22F8	0x22F9	0x22FA	0x22FB
	A1	0x22FC	0x22FD	0x22FE	0x22FF
	A2	0x2300	0x2301	0x2302	0x2303
9	B0	0x2304	0x2305	0x2306	0x2307
	B1	0x2308	0x2309	0x230A	0x230B
	B2	0x230C	0x230D	0x230E	0x230F
	A1	0x2310	0x2311	0x2312	0x2313
	A2	0x2314	0x2315	0x2316	0x2317
10	B0	0x2318	0x2319	0x231A	0x231B
	B1	0x231C	0x231D	0x231E	0x231F
	B2	0x2320	0x2321	0x2322	0x2323
	A1	0x2324	0x2325	0x2326	0x2327
	A2	0x2328	0x2329	0x232A	0x232B

Table 35 shows how each filter band and coefficient is structured in the register space for the playback compensation channel bank B.

Table 35. Playback Compensation Channel Biquad Filter Bank B Coefficient Register Addresses
FILTER BAND	FILTER COEFFICIENT	BLANK REGISTER	BITS [7:0] REGISTER	BITS [15:8] REGISTER	BITS [23:16] REGISTER
1	B0	0x232C	0x232D	0x232E	0x232F
	B1	0x2330	0x2331	0x2332	0x2333
	B2	0x2334	0x2335	0x2336	0x2337
	A1	0x2338	0x2339	0x233A	0x233B
	A2	0x233C	0x233D	0x233E	0x233F
2	B0	0x2340	0x2341	0x2342	0x2343
	B1	0x2344	0x2345	0x2346	0x2347
	B2	0x2348	0x2349	0x234A	0x234B
	A1	0x234C	0x234D	0x234E	0x234F
	A2	0x2350	0x2351	0x2352	0x2353
3	B0	0x2354	0x2355	0x2356	0x2357
	B1	0x2358	0x2359	0x235A	0x235B
	B2	0x235C	0x235D	0x235E	0x235F
	A1	0x2360	0x2361	0x2362	0x2363
	A2	0x2364	0x2365	0x2366	0x2367
4	B0	0x2368	0x2369	0x236A	0x236B
	B1	0x236C	0x236D	0x236E	0x236F
	B2	0x2370	0x2371	0x2372	0x2373
	A1	0x2374	0x2375	0x2376	0x2377
	A2	0x2378	0x2379	0x237A	0x237B
5	B0	0x237C	0x237D	0x237E	0x237F
	B1	0x2380	0x2381	0x2382	0x2383
	B2	0x2384	0x2385	0x2386	0x2387
	A1	0x2388	0x2389	0x238A	0x238B
	A2	0x238C	0x238D	0x238E	0x238F
6	B0	0x2390	0x2391	0x2392	0x2393
	B1	0x2394	0x2395	0x2396	0x2397
	B2	0x2398	0x2399	0x239A	0x239B
	A1	0x239C	0x239D	0x239E	0x239F
	A2	0x23A0	0x23A1	0x23A2	0x23A3
7	B0	0x23A4	0x23A5	0x23A6	0x23A7
	B1	0x23A8	0x23A9	0x23AA	0x23AB
	B2	0x23AC	0x23AD	0x23AE	0x23AF
	A1	0x23B0	0x23B1	0x23B2	0x23B3
	A2	0x23B4	0x23B5	0x23B6	0x23B7
8	B0	0x23B8	0x23B9	0x23BA	0x23BB
	B1	0x23BC	0x23BD	0x23BE	0x23BF
	B2	0x23C0	0x23C1	0x23C2	0x23C3
	A1	0x23C4	0x23C5	0x23C6	0x23C7
	A2	0x23C8	0x23C9	0x23CA	0x23CB
9	B0	0x23CC	0x23CD	0x23CE	0x23CF
	B1	0x23D0	0x23D1	0x23D2	0x23D3
	B2	0x23D4	0x23D5	0x23D6	0x23D7
	A1	0x23D8	0x23D9	0x23DA	0x23DB
	A2	0x23DC	0x23DD	0x23DE	0x23DF
10	B0	0x23E0	0x23E1	0x23E2	0x23E3
	B1	0x23E4	0x23E5	0x23E6	0x23E7
	B2	0x23E8	0x23E9	0x23EA	0x23EB
	A1	0x23EC	0x23ED	0x23EE	0x23EF
	A2	0x23F0	0x23F1	0x23F2	0x23F3

PBC Channel Digital Gain Adjust

The playback compensation channel includes a banked, programmable coarse digital gain adjustment. The channel digital gain adjustment provides a gain range of 0dB to +42dB in 6dB steps, and is programmed individually by bank with the PBC_GAIN_BKA and PBC_GAIN_BKB bit fields. The channel gain adjust is provided for use cases where a large positive gain offset is required, and should not be changed while the respective playback compensation channel bank is active.

PBC Channel Digital Volume Control

The playback compensation channel includes a banked, dynamically programmable digital volume control. The digital volume control provides an attenuation range of 0dB to -31.5dB in 0.5dB steps, and is configured individually by bank with the PBC_VOL_BKA and PBC_VOL_BKB bit fields.

A digital mute is also provided for the playback compensation channel, and is enabled with the PBC_VOL_MUTE bit. The playback compensation mute is in the same register as the low-latency digital filter channel 1 and 2 mute controls (DF1_VOL_MUTE and DF2_VOL_MUTE), and if any of these mute bits are changed simultaneously with a single write command the start of the mute or unmute action (and volume ramp if enabled) is synchronized across the active channels (that are affected by the write).

When enabled, digital volume ramping occurs during playback compensation channel startup, shutdown, volume changes, and digital mute toggling. Channel volume ramping can be dynamically enabled and disabled with the PBC_VOL_RMP_EN bit, however the setting should never be changed while a volume ramp is in progress. When a volume ramp is complete, the device generates the playback compensation ramp done interrupt (PBC_RMP_DONE_*). The duration of a given volume ramp is selected with the PBC_VOL_RMP_RATE bit field. Depending on the type of audio content and the characteristics of the speaker load, selecting faster ramp rates (typically those less than 32ms) or disabling ramping entirely can potentially result in audible glitches during volume changes.

Internal Digital Filter Channel Sequencing

The playback compensation and low-latency digital filter channels can all be either statically enabled (prior to the device exiting software shutdown) or dynamically enabled at any time without disrupting audio playback. To avoid audible glitches on channel enable, it is recommended that the channels should only be enabled (statically or dynamically) with the respective channel mute enabled (PBC_VOL_MUTE, DF1_VOL_MUTE, and DF2_VOL_MUTE respectively). This allows for the channel to power up, for data to propagate, and for the filter response to settle (duration required depends on filter implementation) prior to deactivating the channel mute. The channel mute(s) can be disabled with a single write command to ensure a synchronized response across active channels. The channel(s) then smoothly ramp up into the configured active state without creating an audible glitch.

To avoid audible glitches on channel disable, the appropriate channel mutes should be activated first (with a single write command and with volume ramping enabled). When the volume ramp down is complete, the appropriate channel volume ramp done interrupt(s) (PBC_RMP_DONE_*, DF1_RMP_DONE_*, and/or DF2_RMP_DONE_*) trigger. Once the interrupt (or interrupts) have asserted (or after the configured ramp time has expired), the channel (or channels) can be safely disabled without disrupting playback or causing an audible glitch. If the recommended sequencing is not followed and the digital filter channels are disabled (with volume ramping enabled) without first muting them, then no ramp down occurs, audible glitches are possible, and an erroneous ramp done interrupt can be produced.

Playback Channel Configuration

The playback amplifier channel accepts input data from the PCM interface receiver (DIN). The data is then routed through the playback channel filters and signal processing and is mixed with the playback compensation channel and low-latency digital filter channels before reaching the DAC and hybrid class-AB/D headphone amplifier. The output digital data from the end of the playback channel can also be routed back to the PCM interface transmitter through record channel 4.

The playback channel digital stages and amplifier can only be active when the device is in the audio state. The playback channel is enabled and disabled with the playback enable bit (PB_EN). The playback enable can be programmed in either the software shutdown state or dynamically in the audio state, but should not be changed while playback activation or deactivation is in progress. If the PB_EN bit is set high while the device is in the software shutdown state, the playback channel is not enabled until the device transitions to the audio state. Once the playback channel is enabled, the device generates a PB_PWRUP_DONE interrupt event when the channel is active and ready for use.

Figure 31. Playback Channel Detailed Block Diagram

Playback Channel Dither

The input data to the playback channel can optionally have dither (±1 LSB peak-to-peak) applied if PB_DITH_EN is set to 1. No dither is applied when PB_DITH_EN is set to 0.

Playback Channel Data Inversion

The input data to the playback channel can optionally be inverted by setting the PB_INVERT bit to 1.

Playback Channel DC Blocking Filter

A DC blocking filter can be enabled on the playback channel by setting the PB_DCBLK_EN bit to 1. The DC blocking filter corner frequency is selected with the PB_DCBLK bit field. The corner frequency scales with the playback sample rate from 8kHz to 48kHz, and is constant for sample rates above 48kHz. The higher corner frequency setting reduces audio band flatness but results in faster settling times for playback channel enable.

Playback Channel Digital Volume Control

The playback channel includes a dynamically programmable digital volume control. The digital volume control provides an attenuation range of 0dB to -63.5dB in 0.5dB steps, and is configured with the PB_VOL bit field. A digital mute is also provided and is enabled with the PB_VOL_MUTE bit.

When enabled, digital volume ramping occurs during playback channel startup, shutdown, volume changes, and digital mute toggling. Playback volume ramping can be dynamically enabled and disabled with the playback volume ramping enable bit (PB_VOL_RMP_EN), however the setting should never be changed while a volume ramp is in progress. When a volume ramp is complete, the device generates a playback ramp done interrupt (PB_RMP_DONE_*). When volume ramping is enabled, the playback turn-on and turn-off times are extended based on the configured playback volume ramp rates.

The duration of a given playback volume ramp is selected with the PB_VOL_RMP_RATE bit field. The only exception is for playback channel shutdown, where the shutdown volume ramp duration is instead selected with the PB_SHDN_RMP_RATE bit field. Depending on the type of audio content and the characteristics of the speaker load, selecting faster ramp rates (typically those less than 32ms) or disabling ramping entirely can potentially result in audible glitches during volume changes.

Playback Channel 5-Band Equalizer

The playback channel features a 5-band equalizer where each band is a full, individually programmable digital biquad filter. The biquad equalizer can be configured with the PB_BQ_EN bit field to have 0 to 5 bands active, and inactive bands do not consume additional quiescent power. The gain (A), quality factor (Q), and frequency (f₀) limitations by equalizer band vary by implemented filter type, and are described in the Electrical Characteristics Table.

The transfer function for each equalizer band is defined as:

$H (z) = \frac{(B_{0} + B_{1} \times Z^{- 1} + B_{2} \times Z^{- 2})}{(A_{0} + A_{1} \times Z^{- 1} + A_{2} \times Z^{- 2})}$

The biquad filter in each equalizer band has five user-programmable coefficients (B0, B1, B2, A1, and A2 with A0 fixed at 1), and each individual coefficient is 3 bytes (24 bits) long. Each set of three registers (per coefficient) must be programmed consecutively for the settings to take effect. The coefficients are stored using a signed two’s complement format where the first 2 bits are the integer portion and the last 22 bits are the decimal portion (which results in an approximate +2 to -2 range for each coefficient). This coefficient range and resolution allows for the implementation of several common filter types including peaking filters, high and low pass filters, and high and low shelving filters. The 2.22 format is a fixed point coefficient implementation that results in some range and resolution boundary limits for filter parameters (see the Biquad Filter Characteristics in the Electrical Characteristics Table).

The playback biquad equalizer coefficient register bits are uninitialized when the device first powers up, and the coefficients for any given biquad band should be fully programmed before being enabled. The biquad filter coefficients can be freely written and read back when the device is in software shutdown (AUDIO_EN = 0) or when playback is disabled (PB_EN = 0). However, once the playback biquad equalizer is enabled only inactive bands can be safely written. Readback is restricted by playback enable, and attempting to read back the coefficients while the playback channel is enabled and active may return all zero values.

Playback Channel Equalizer Coefficient Registers

The playback channel contains a 5-band biquad filter for playback response equalization. The register structure for each band (and the 5 coefficients within each) is identical and repeated.

The coefficients in each band are sequentially placed in the same order in the register map (B0, B1, B2, A1, A2) for a total of 20 addresses per filter band. Within this structure, each coefficient spans four addresses, the first of which is blank followed by the three addresses that make up the 24-bit coefficient (lowest bits, middle bits, and highest bits in order). Coefficient segments must be consecutively written for the new settings to take effect, but blank addresses may be skipped or written with any value as needed (when creating a programming sequence). The coefficients should only be programmed when the device is in software shutdown or when the playback channel equalizer is completely disabled.

Table 36 shows how each playback equalizer band and the coefficients are structured in the register space.

Table 36. Playback Channel Equalizer Coefficient Register Addresses
FILTER BAND	FILTER COEFFICIENT	BLANK REGISTER	BITS [7:0] REGISTER	BITS [15:8] REGISTER	BITS [23:16] REGISTER
1	B0	0x2200	0x2201	0x2202	0x2203
	B1	0x2204	0x2205	0x2206	0x2207
	B2	0x2208	0x2209	0x220A	0x220B
	A1	0x220C	0x220D	0x220E	0x220F
	A2	0x2210	0x2211	0x2212	0x2213
2	B0	0x2214	0x2215	0x2216	0x2217
	B1	0x2218	0x2219	0x221A	0x221B
	B2	0x221C	0x221D	0x221E	0x221F
	A1	0x2220	0x2221	0x2222	0x2223
	A2	0x2224	0x2225	0x2226	0x2227
3	B0	0x2228	0x2229	0x222A	0x222B
	B1	0x222C	0x222D	0x222E	0x222F
	B2	0x2230	0x2231	0x2232	0x2233
	A1	0x2234	0x2235	0x2236	0x2237
	A2	0x2238	0x2239	0x223A	0x223B
4	B0	0x223C	0x223D	0x223E	0x223F
	B1	0x2240	0x2241	0x2242	0x2243
	B2	0x2244	0x2245	0x2246	0x2247
	A1	0x2248	0x2249	0x224A	0x224B
	A2	0x224C	0x224D	0x224E	0x224F
5	B0	0x2250	0x2251	0x2252	0x2253
	B1	0x2254	0x2255	0x2256	0x2257
	B2	0x2258	0x2259	0x225A	0x225B
	A1	0x225C	0x225D	0x225E	0x225F
	A2	0x2260	0x2261	0x2262	0x2263

Playback Channel Delay Stage

The playback channel programmable delay stage can add 0 to 7 samples of delay to the playback channel, and is configured with the PB_DELAY bit field. The playback delay stage is positioned after the first stage of playback channel interpolation filters, and as a result, delay in terms of number of samples is at a 384kHz sample rate (regardless of the selected PCM playback channel sample rate).

Playback Channel Digital Gain Adjust

The playback channel includes a programmable digital gain adjustment that is positioned at the end of the playback channel DSP. The playback channel digital gain adjustment is configured with the PB_GAIN bit field, and provides a range of -6dB to +6dB in 0.25dB steps. The digital gain is provided to allow for adjustment of the playback channel full-scale output (for example to compensate for the sensitivity of the attached headphone transducer). The selected digital gain level should not be changed while the playback channel is active.

Playback Channel Wide Band Mode

For sample rates above 48kHz, the playback channel bandwidth is normally limited by the digital filters to approximately 20kHz. However, if the PB_HBW_EN bit is set high, playback high bandwidth mode is enabled and the playback channel bandwidth is extended to approximately 40kHz. This mode can result in increased quiescent power consumption due to additional out of band energy at the playback amplifier output.

Playback Channel Digital Headroom Adjustment

The headroom of the digital sections of the playback channel and playback compensation channel can be increased with the PB_HR_SEL bit field. Selecting higher digital headroom reduces the overall data channel resolution (truncates lower bits), but can be used to prevent clipping in the intermediate digital processing and filter stages. If the total signal response is still above the full-scale output (at the point where the digital filter channels are summed into the playback channel), then playback channel digital clipping may still occur.

Playback Channel Noise Gate

The playback channel noise gate function is enabled when the device is in the audio state and the noise gate enable (PB_NG_EN) is set to 1. When the noise gate is enabled, the noise gate begins activation whenever the amplitude of the input audio data to the playback channel (from the PCM interface) is below the configured noise gate mute threshold (PB_NG_MUTE_THRESH) for more than 1024 consecutive data samples. Noise gate activation is not instant, as it must first ramp down the playback channel (and playback compensation channel) into a digital mute state and wait for signal propagation before idling in a reduced power state. The amplifier output remains active however, and data (such as ambient or anti-noise signals) from the low-latency digital filter channels is still played back.

The playback noise gate deactivates immediately if the amplitude of even a single playback channel input audio data sample exceeds the configured unmute threshold (PB_NG_UNMUTE_THRESH). When the noise gate deactivates, the playback channel (and playback compensation channel) is unmuted and returns to normal operation before the input audio data (that triggered deactivation) reaches the output.

The noise gate mute and unmute threshold settings are selected in terms of the number of bits (starting from the LSB) that must be toggling (or active) in order for the input signal amplitude to exceed the thresholds. It is invalid to set the noise gate unmute threshold such that it is less than the configured mute threshold. The location of the audio data LSB within the PCM input data channel is determined by the configured PCM data word size (PCM_CHANSZ). The supported combinations are shown in Table 37.

Table 37. Noise Gate Threshold LSB Location
INPUT DATA WORD SIZE	NOISE GATE FUNCTION LSB LOCATION
16	16
24	24
32	24

Playback Amplifier

The playback channel features a fully differential hybrid Class-AB/Class-D mode amplifier output stage. To minimize quiescent power and maximize output efficiency, the device monitors the playback signal level and then (based on the selected amplifier configuration) selects the optimal amplifier operating mode, reference supply level, and gain structure. If no faults are present, the playback amplifier is enabled whenever the playback channel is enabled (PB_EN bit) and the device is in the audio state (AUDIO_EN bit).

By default, the playback amplifier operates in high-performance mode. For use cases where minimizing quiescent power consumption is critical, the amplifier can be configured to operate in low-power mode by setting the PB_POWER_MODE bit to 0 (prior to enabling playback). Low-power mode operation marginally increases playback amplifier THD+N and output noise.

Playback Amplifier Mode Configuration

Based on the playback signal level, the device automatically determines whether the amplifier output operates in class-AB mode or class-D mode. When the input signal level is small, the amplifier output operates in class-AB mode from the AVDD2 (1.2V) supply. Class-AB mode operation minimizes quiescent power consumption and the output noise level.

As the signal level increases, the amplifier output transitions to class-D mode operation to maximize efficiency. Once the amplifier output is in class-D mode, the device continues to monitor the playback signal level. To avoid clipping, by default the amplifier output automatically selects whether to operate from the lower power AVDD3 (1.2V) supply or the high swing AVDD1 (1.8V) supply. Alternatively, if the PB_AMP_MODE bit is set to 0x1 (prior to enabling playback) when the amplifier output is operating in class-D mode, it is restricted to using the lower power AVDD3 (1.2V) supply. This limits the amplifier full-scale output swing, but optimizes amplifier efficiency and limits peak output noise levels.

Table 38. Playback Amplifier Output Operating Mode and Supply Configuration
SIGNAL LEVEL	LESS THAN -30dBFS	-30dBFS TO -5dBFS	GREATER THAN -5dBFS
PB_AMP_MODE = 0x0	Class-AB Mode (AVDD2)	Class-D Mode (AVDD3)	Class-D Mode (AVDD1)
PB_AMP_MODE = 0x1	Class-AB Mode (AVDD2)	Class-D Mode (AVDD3)	Class-D Mode (AVDD3)

Playback Amplifier Class-D Mode Settings

For typical headphone loads placed near the playback amplifier, the amplifier output does not require the use of external LC filters or shielding to meet electromagnetic-interference (EMI) regulation standards. In addition, the playback amplifier supports two slightly different class-D mode output switching frequencies (PB_AMP_PWM_SEL). The secondary switching frequency setting can be used in cases where the default switching frequency could potentially result in system level interference.

The device also features emissions limiting circuitry that reduces the output switching harmonics that can directly contribute to EMI and radiated emissions. The programmable playback amplifier slew rate control bits are used to adjust the class-D mode output switching edge rate. Faster slew rates can slightly improve the amplifier performance and efficiency, while reducing the slew rate decreases active emissions. The playback amplifier rising edge slew rate is selected with the PB_AMP_SLEW_RISE bit field and the falling edge slew rate is selected with the PB_AMP_SLEW_FALL bit field.

The playback amplifier output also supports spread spectrum modulation (SSM). SSM is enabled with the PB_AMP_SSM_EN bit, and when active it optimizes the suppression and control of the output switching harmonics that can contribute to EMI and radiated emissions. The clock period variation in spread-spectrum mode is controlled by the PB_AMP_SSM_VAL bit field. Higher clock period variation settings spread out-of-band energy across a wider bandwidth. Above 10MHz, the wideband spectrum looks like noise for EMI purposes.

Playback Amplifier Overcurrent Limit Protection

The amplifier features overcurrent protection (OCP) monitoring that can protect the amplifier output from both high current and short circuit events (OUTP/OUTN shorted to AVDD1/2/3, AGND, or each other).

If the PB_AMP_OCP_AUTORESTART_EN bit is set to 1, the device is in automatic overcurrent protection (OCP) mode. In auto mode, if the amplifier output current exceeds the current limit threshold (120mA), the device generates an AMP_OCP_* interrupt and disables the amplifier output internally (without changing the control bit states). After the OCP restart time (t_{OCP_RETRY}), the amplifier output is automatically re-enabled. If the overcurrent condition still exists, the device continues to disable and re-enable the amplifier output automatically until the fault condition is removed. This could continue indefinitely if the fault condition persists and the software driver does not intervene. The values of PB_EN and AUDIO_EN (or any other control bit field) are not changed in auto OVC mode and remain in their previous states throughout the process.

If the PB_AMP_OCP_AUTORESTART_EN bit is set to 0, the device is in manual OCP mode. In manual mode, if an amplifier overcurrent event occurs, the device generates an AMP_OCP_* interrupt, disables the amplifier output, and disables the amplifier by setting the PB_EN bit to 0. As a result, the host must manually re-enable the amplifier output (PB_EN bit) after an overcurrent event.

Clock and Data Monitors

The device provides input data and external clock monitors that detect host and system level faults. The data monitor detects persistent stuck and high amplitude input signals, while the clock monitor detects external clock failures and invalid clock configurations.

Clock Monitor

The device provides an optional clock monitor that is enabled by setting CMON_EN to 1. Once enabled, it actively monitors the input BCLK and LRCLK anytime the device exits software shutdown (AUDIO_EN = 1). When active, the clock monitor detects clock activity, clock frequency, and frame timing (clock ratio). If faults are detected, the clock monitor automatically places the device into software shutdown and generates a clock error interrupt (CLOCK_ERR_*).

The clock monitor operates in automatic mode when CMON_AUTORESTART_EN = 1 and manual mode when CMON_AUTORESTART_EN = 0. Manual mode may be used with any device configuration (any combination of record, playback, and internal digital filter channels). However, automatic mode is only recommended for use with either playback only or playback with internal digital filter channel use cases (and not with any use cases that include active record channels to the host).

Table 39. Recommended Clock Monitor Modes
USE CASE ENABLED CHANNELS	RECOMMENDED CLOCK MONITOR MODE
Playback Channel	Manual or Automatic Mode
Digital Filter Channels 1/2	Manual or Automatic Mode
Record Channels 1/2/3	Manual Mode

In automatic mode, when a clock error places the device into software shutdown, the audio enable bit is not changed (AUDIO_EN remains 1), and the device automatically recovers from all clock errors. In automatic mode, both clock error (CLOCK_ERR_*) and clock recovery (CLOCK_REC_*) interrupts are generated in pairs (a clock recovery interrupt is not possible until after clock errors have occurred, and all clock errors have recovered).

In manual mode, when a clock error places the device into software shutdown, the audio enable bit (AUDIO_EN) is set to 0. Clock recovery (CLK_REC_*) interrupts are never generated in manual mode, and the device remains in software shutdown until the host sets AUDIO_EN back to 1. Once the device is re-enabled (AUDIO_EN set to 1 with one or more audio channel enabled), the clock monitor is reactivated and detects any new (or persisting) clock errors. If a clock error is detected, the device returns to software shutdown (AUDIO_EN = 0), and a new clock error interrupt (CLOCK_ERR_*) is generated.

Clock errors are fault conditions, and audible glitches may occur on clock monitor based transitions into and out of software shutdown. When the clock monitor is enabled, no false clock error or clock recovery interrupts are generated when the host software transitions the device normally into and out of software shutdown.

Clock Activity and Frequency Detection

When the clock monitor is enabled, the bit clock (BCLK) and frame clock (LRCLK) frequencies are monitored. The expected LRCLK frequency is equal to the PCM sample rate (PCM_SR). The expected BCLK frequency is based on the BCLK to LRCLK ratio (PCM_BSEL) relative to the PCM sample rate (PCM_SR).

The current frequency of each clock is measured relative to (and once per interval of) the programmed frame period (as set by PCM_SR). A clock frequency error is detected when the measured clock frequencies differ from programmed clock frequencies (faster or slower) by more than the frequency error threshold (45% typical). If either clock stops high or low, the frequency measurement result allows detection of the clock stop event.

The CMON_ERRTOL bit field sets the clock frequency error tolerance. The tolerance is the required number of consecutive frame clock periods (PCM_PB_SR) with an incorrect clock frequency before a clock error is generated. If the error persists for the selected number of frame periods, a clock error interrupt (CLOCK_ERR_*) is generated, and the device is placed into software shutdown.

In automatic mode, the CMON_ERRTOL bit field also sets the number of consecutive correct frame clock periods (with no clock frequency errors) that are required for error recovery before automatic restart occurs. Once the selected number of consecutive error free frames are detected, the clock error is cleared. Once all clock errors are cleared, a clock recovery interrupt (CLOCK_REC_*) is generated and the device automatically exits software shutdown.

In manual mode, no clock recovery interrupts are generated. The clock monitor remains disabled and the device remains in software shutdown until the host software sets AUDIO_EN back to 1.

Figure 32. Clock Monitor Frame Clock (LRCLK) Frequency Error Example with CMON_ERRTOL = 0x1

Clock Frame Error Detection

When the clock monitor is enabled, the bit clock (BCLK) to frame clock (LRCLK) ratio is monitored. The clock monitor counts the number of BCLK periods per frame (LRCLK period), and then compares the count to the configured clock ratio (PCM_BSEL). In addition, in I²S and left-justified (LJ) modes the clock monitor verifies the LRCLK duty cycle by checking that the number of BCLK periods per channel is equal. In TDM mode, data transport is synchronized to the active frame clock (LRCLK) edge, so no duty cycle restrictions are enforced (only the clock ratio is monitored).

A frame error is detected in each frame where the monitored bit clock (BCLK) to frame clock (LRCLK) ratio (and duty cycle in I²S and LJ Modes) differs from the configured settings. The CMON_BSELTOL bit field sets the number of consecutive frames with frame errors that are required before a clock error interrupt (CLOCK_ERR_*) is generated and the device is placed into software shutdown.

In automatic mode, the CMON_BSELTOL bit field also sets the number of consecutive frames (with no frame errors) that are required for the frame error to recover (so automatic restart can occur). Once the selected number of consecutive error free frames are detected, the frame error recovers, a clock recover interrupt (CLOCK_REC_*) is generated (if all clock errors have been cleared), and the device automatically exits software shutdown.

In manual mode, no clock recovery interrupts are generated. The clock monitor remains disabled and the device remains in software shutdown until the host software sets AUDIO_EN back to 1.

Figure 33. Clock Monitor Clock Ratio Frame Error Example with TDM Mode 0 Timing

Input Data Monitor

The device provides an optional input data monitor that is enabled by setting the DMON_MAG_EN bit to 1 (for the data magnitude monitor) and the DMON_STUCK_EN bit to 1 (for the data stuck monitor). When at least one data monitor function is enabled, it actively monitors the selected input data channel (from DIN) to the playback channel whenever the device exits software shutdown (AUDIO_EN = 1) and playback is enabled (PB_EN = 1).

When active, the data monitor checks the input playback data for the enabled data error types (data magnitude, data stuck, or both). The DMON_DURATION bit field selects the duration that a data stuck or magnitude error must persist for before a data error is detected. Once a data error is detected, the data monitor automatically places the device into software shutdown (sets AUDIO_EN to 0) and generates a data monitor error interrupt (DMON_ERR_*).

Data errors are fault conditions, and audible glitches may occur on data monitor based transitions into and out of software shutdown. When the data monitor is enabled, no false data error interrupts (DATA_ERR_*) are generated when the host software transitions the device normally into and out of software shutdown.

Data Stuck Error Detection

A data stuck error is detected if the input signal repeats a fixed value with a magnitude (positive or negative) that is beyond the data stuck threshold (DMON_STUCK_THRES) for longer than the data error duration (DMON_DURATION). If the input signal repeats a fixed value for any duration with a magnitude that is within the data stuck threshold limits (such as a zero or near zero code), no data stuck error is detected.

Data Magnitude Error Detection

A data magnitude error is detected if the input signal magnitude (positive or negative) is beyond the data magnitude threshold (set by DMON_MAG_THRES) for longer than the data error duration (set by DMON_DURATION).

Device and Revision Identification Number

The device provides two registers that contain the device identification number (DEV_ID). The device identification number is equivalent to the last 4 digits in the device part number (0x8050).

The device also provides a register containing the device revision identification number (REV_ID). The revision identification number reflects the current physical hardware version, and is updated with any hardware revision. The current revision identification number is 0x41.

Device Register Map Description

Table 40. Control Register Map Bit Field Types
Bit Field Type	Functional Description
Read-Only Bit Field	Writes to read-only bit fields have no effect.
Write-Only Bit Field	Write 1 to activate. Writing 0 has no effect. Readback always returns 0.
Read/Write Bit Field	Read and write these bit fields normally (May have write access restrictions)

Read-only bit fields (R) are used to indicate an internal device state, and cannot be changed directly by the host. Writing to these registers has no effect.

Write-only bit fields (W) are single-bit push-button controls. Writing a 1 to these bit fields performs an action (i.e., software reset, interrupt clear, etc.). Writing a 0 has no effect, and a read back always returns a 0.

Read/Write bit fields (RW) can be both read and written by the host, and the last written value is the value returned on readback.

Reserved bit fields are not used to program or control the device. When writing a register that contains reserved bit fields, always write a 0 to the reserved bit field segments.

Control Bit Write Access Restrictions

The device control bits fall into one of three basic types: read (R), write (W), or read and write (RW). There are no direct read restrictions (though some biquad filter coefficients may return zeroes if read when active), and any read enabled bit field can be read back anytime the I²C control interface is active. There are however write restrictions, and every write enabled bit field falls into one of two write access subtypes.

The first write access subtype is dynamic. Dynamic bit fields effectively have no write access restrictions, and can be safely changed (written) in any device state where the I²C control interface is active. The second bit field access subtype is restricted. Restricted bit fields should only be changed (written) when the related functional block (as shown in Table 41) is powered down. If the write access is restricted to the global enable (restriction EN), then the restricted bit field should only be changed (written) when the device is in software shutdown.

The bit field type and write access subtype is provided for every bit field in the detailed register description tables. For all bit fields with the restricted subtype, the dependency is also denoted in the "RES" column.

Table 41 provides a detailed description of all device register types, access subtypes, and restriction dependencies that are used by this device. The write access restrictions describe the specific device condition(s) that should be met (and the corresponding bit field settings) before the system attempts to change (write to) bit fields with that restriction type.

Table 41. Control Bit Types and Write Access Restrictions
REGISTER TYPE	WRITE ACCESS	DESCRIPTION	CONDITION	"RES" SYMBOL
REGISTER TYPE	WRITE ACCESS	WRITE ACCESS RESTRICTIONS		"RES" SYMBOL
Read	Read-Only	None	—	—
Write or Write/Read	Dynamic	None	—	—
	Restricted	Device Held in Software Shutdown	AUDIO_EN = 0	EN
		IRQ Output Disabled	IRQ_EN = 0	IRQ
		PCM Interface Disabled	PCM_TX_EN = 0 and PCM_RX_EN = 0	PCM
		Playback Channel Disabled	PB_EN = 0	PB
		Record Channel n Disabled	Respective RECn_EN = 0	RECn
		Analog Microphone Input n Disabled	Respective AMICn_EN = 0	AMICn
		Analog Microphone Bias Disabled	AMIC_BIAS_EN = 0	MBIAS
		All Digital Microphone Interfaces Disabled	ALL 3 DMICn_EN = 0	DMIC
		Digital Filter Channel 1 Disabled	DF1_EN = 0	DF1
		Digital Filter Channel 2 Disabled	DF2_EN = 0	DF2
		Both Digital Filter Channels Disabled	DF1_EN = 0 and DF2_EN = 0	DF
		Playback Compensation Channel Disabled	PBC_EN = 0	PBC