Pin Specifications

Pin Description
PIN	NAME	FUNCTION MODE	FUNCTION
POWER (See the Applications Information section for bypass capacitor recommendations.)
A10	V_BAT	—	—	—	Battery Power Supply. Bypass device pin A10 with a 1μF capacitor placed as close as possible to this pin and the V_SSPWR pin. This pin must be connected to V_REGIand V_DDIOH at the circuit board level.
C13	V_REGI	—	—	—	Battery Power Supply for the SIMO Switch-Mode Power Supply (SMPS). Bypass this pin with 2 x 47μF capacitors placed as close as possible to this pin and the V_SSPWR pin. This pin must be connected to V_BAT and V_DDIOH. If the power to the device is cycled, the voltage applied to this pin must reach V_{REGI_POR}.
B10	V_DDA	—	—	—	1.8V Analog Power Supply. Bypass this pin with a 1μF capacitor placed as close as possible to this pin and V_SSA. This device pin must be connected to V_DDIO.
D12	V_DDB	—	—	—	USB Transceiver Supply Voltage. Bypass this pin to V_SSB with a 1.0μF capacitor as close as possible to the package.
A4	V_REF	—	—	—	ADC External Reference Input. Bypass this pin with a 1μF capacitor placed as close as possible to this pin and V_SSA as possible. This is the reference input for the analog-to-digital converter (ADC). If the external reference is not used, tie this pin to V_SSA through a 500Ω resistor.
A8	V_COREA	—	—	—	Digital Core Supply Voltage A. Bypass this pin to V_SS with a 1μF capacitor placed as close to this pin as possible.
B8	V_COREB	—	—	—	Digital Core Supply Voltage B. Bypass this pin to V_SS with a 1μF capacitor placed as close to this pin as possible.
B12	V_BST	—	—	—	Boosted Supply Voltage for the Gate Drive of High-Side Switches. Bypass V_BST to LXB with a 3.3nF capacitor.
B11	V_{REGO_A}	—	—	—	Buck Converter A Voltage Output. Bypass this pin with a 22μF capacitor to V_SS placed as close as possible to this pin.
C11	V_{REGO_B}	—	—	—	Buck Converter B Voltage Output. Bypass this pin with a 22μF capacitor to V_SS placed as close as possible to this pin.
A11	V_{REGO_C}	—	—	—	Buck Converter C Voltage Output. Bypass this pin with a 22μF capacitor to V_SS placed as close as possible to this pin.
D1	V_DDIO	—	—	—	GPIO Supply Voltage. Bypass this pin to V_SS with a 1.0μF capacitor placed as close as possible to the package.
E1	V_DDIOH	—	—	—	GPIO Supply Voltage, High. V_DDIOH ≥ V_DDIO. Bypass this pin to V_SS with a 1.0μF capacitor placed as close as possible to the package. This device pin must be connected to V_REGI and V_BAT.
E12	V_USB0P9	—	—	—	Bypass with 1μF capacitor to V_SSB. Do not connect this device pin to any other external circuitry.
C8	V_CSI2P5	—	—	—	Bypass with 1μF capacitor to V_SS. Do not connect this device pin to any other external circuitry.
F1, G1, A2, G2, G3, G4, A5, B5, C5, D5, M6, N6, K7, L7, M7, N7, C9, F10, F11, F12, G12, F13, G13	V_SS	—	—	—	Digital Ground.
B4	V_SSA	—	—	—	Analog Ground. This pin is the return path for V_REF and V_DDA.
A13	V_SSPWR	—	—	—	Ground for the SIMO Switch-Mode Power Supply (SMPS). This device pin is the return path for the V_REG.
C12	V_SSB	—	—	—	USB Transceiver Ground.
B13	LXA	—	—	—	Switching Inductor Input A. Connect a 2.2μH inductor between LXA and LXB.
A12	LXB	—	—	—	Switching Inductor Input B. Connect a 2.2μH inductor between LXA and LXB.
N1, N2, N3	V_CNN0	—	—	—	Voltage Supply for CNN x16 Processor Quadrant 0. Bypass this pin with 3 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.
H1, H2, H3	V_CNN1	—	—	—	Voltage Supply for CNN x16 Processor Quadrant 1. Bypass this pin with 3 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.
N11, N12, N13	V_CNN2	—	—	—	Voltage Supply for CNN x16 Processor Quadrant 2. Bypass this pin with 3 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.
H11, H12, H13	V_CNN3	—	—	—	Voltage Supply for CNN x16 Processor Quadrant 3. Bypass this pin with 3 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.
M1, M2	V_CNN0RAM	—	—	—	Voltage Supply for the RAM for the CNN x16 Processor Quadrant 0. Bypass this pin with 2 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.
J1, J2	V_CNN1RAM	—	—	—	Voltage Supply for the RAM for the CNN x16 Processor Quadrant 1. Bypass this pin with 2 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.
M12, M13	V_CNN2RAM	—	—	—	Voltage Supply for the RAM for the CNN x16 Processor Quadrant 2. Bypass this pin with 2 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.
J12, J13	V_CNN3RAM	—	—	—	Voltage Supply for the RAM for the CNN x16 Processor Quadrant 3. Bypass this pin with 2 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.
K9	V_{CNN0_EN}	—	—	—	Enable Output for the Voltage Supply for CNN x16 Processor Quadrant 0.
M9	V_{CNN1_EN}	—	—	—	Enable Output for the Voltage Supply for CNN x16 Processor Quadrant 1.
L10	V_{CNN2_EN}	—	—	—	Enable Output for the Voltage Supply for CNN x16 Processor Quadrant 2.
N10	V_{CNN3_EN}	—	—	—	Enable Output for the Voltage Supply for CNN x16 Processor Quadrant 3.
L9	V_{CNN0RAM_EN}	—	—	—	Enable Output for the Voltage Supply for the RAM for the CNN x16 Processor Quadrant 0.
N9	V_{CNN1RAM_EN}	—	—	—	Enable Output for the Voltage Supply for the RAM for the CNN x16 Processor Quadrant 1.
K10	V_{CNN2RAM_EN}	—	—	—	Enable Output for the Voltage Supply for the RAM for the CNN x16 Processor Quadrant 2.
M10	V_{CNN3RAM_EN}	—	—	—	Enable Output for the Voltage Supply for the RAM for the CNN x16 Processor Quadrant 3.
RESET AND CONTROL
C10	RSTN	—	—	—	Active-Low, External System Reset Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR reset (resetting all logic on all supplies except for RTC circuitry) and begins execution. This pin has an internal pull-up to the V_DDIOH supply.
CLOCK
B9	32KOUT	—	—	—	32kHz Crystal Oscillator Output.
A9	32KIN	—	—	—	32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Optionally, this pin can be configured as the input for an external CMOS-level clock source.
A3	HFXIN	—	—	—	25MHz Crystal Oscillator Input. Connect a 25MHz crystal between HFXIN and HFXOUT. Optionally, this pin can be configured as the input for an external CMOS-level clock source.
B3	HFXOUT	—	—	—	25MHz Crystal Oscillator Output.
GPIO AND ALTERNATE FUNCTION (See the Applications Information section for GPIO and Alternate Function Matrices.)
K6	P0.0	P0.0	UART0A_RX	—	UART0 Receive Port Map A. See Bootloader Activation for details on this pin's usage and suggested pull-up.
L6	P0.1	P0.1	UART0A_TX	—	UART0 Transmit Port Map A.
E11	P0.2	P0.2	TMR0A__IOA	UART0B_CTS	Timer0 I/O 32 Bits or Lower 16 Bits Port Map A; UART0 Clear to Send Port Map B.
E10	P0.3	P0.3/EXT_CLK	TMR0A_IOB	UART0B_RTS	External Clock for Use as SYS_OSC/Timer0 I/O Upper 16 Bits Port Map A; UART0 Request to Send Port Map B.
H4	P0.4	P0.4	SPI0A_SS0	TMR0B_IOAN	SPI0 Port Map A Target Select 0; Timer0 Inverted Output Port Map B.
B2	P0.5	P0.5	SPI0A_MOSI	TMR0B_IOBN	SPI0 Port Map A Controller-Out Target-In Serial Data 0; Timer0 Inverted Output Upper 16 Bits Port Map B.
C2	P0.6	P0.6	SPI0A_MISO	OWM_IO	SPI0 Port Map A Controller-In Target-Out Serial Data 1; 1-Wire Controller Data I/O.
D2	P0.7	P0.7	SPI0A_SCK	OWM_PE	SPI0 Port Map A Clock; 1-Wire Controller Pull-up Enable Output.
E2	P0.8	P0.8	SPI0A_SDIO2	TMR0B_IOA	SPI0 Port Map A Data 2 I/O; Timer0 I/O 32 Bits or Lower 16 Bits Port Map B.
F2	P0.9	P0.9	SPI0A_SDIO3	TMR0B_IOB	SPI0 Port Map A Data 3 I/O; Timer0 I/O Upper 16 Bits Port Map B.
D9	P0.10	P0.10	I2C0A_SCL	SPI0_SS2	I2C0 Port Map A Clock; SPI0 Target Select 2.
D8	P0.11	P0.11	I2C0A_SDA	SPI0_SS1	I2C0 Port Map A Serial Data; SPI0 Target Select 1.
J3	P0.12	P0.12	UART1A_RX	TMR1B_IOAN	UART1 Receive Port Map A; Timer1 Inverted Output Port Map B.
K3	P0.13	P0.13	UART1A_TX	TMR1B_IOBN	UART1 Transmit Port Map A; Timer1 Inverted Output Upper 16 Bits Port Map B.
G11	P0.14	P0.14	TMR1A_IOA	I2S_CLKEXT	Timer1 I/O 32 Bits or Lower 16 Bits Port Map A; I²S External Clock Input.
G10	P0.15	P0.15	TMR1A_IOB	PCIF_VSYNC	Timer1 I/O Upper 16 Bits Port Map A; Parallel Camera Interface Vertical Sync.
D7	P0.16	P0.16	I2C1A_SCL	PT2	I2C1 Port Map A Clock; Pulse Train 2.
D6	P0.17	P0.17	I2C1A_SDA	PT3	I2C1 Port Map A Serial Data; Pulse Train 3.
H10	P0.18	P0.18	PT0	OWM_IO	Pulse Train 0; 1-Wire Controller Data I/O.
J10	P0.19	P0.19	PT1	OWM_PE	Pulse Train 1; 1-Wire Controller Pull-up Enable Output.
J4	P0.20	P0.20	SPI1A_SS0	PCIF_D0	SPI1 Port Map A Target Select 0; Parallel Camera Interface Data 0.
A1	P0.21	P0.21	SPI1A_MOSI	PCIF_D1	SPI1 Port Map A Controller-Out Target-In Serial Data 0; Parallel Camera Interface Data 1.
B1	P0.22	P0.22	SPI1A_MISO	PCIF_D2	SPI1 Port Map A Controller-In Target-Out Serial Data 1; Parallel Camera Interface Data 2.
C1	P0.23	P0.23	SPI1A_SCK	PCIF_D3	SPI1 Port Map A Clock; Parallel Camera Interface Data 3.
K1	P0.24	P0.24	SPI1A_SDIO2	PCIF_D4	SPI1 Port Map A Data 2; Parallel Camera Interface Data 4.
L1	P0.25	P0.25	SPI1A_SDIO3	PCIF_D5	SPI1 Port Map A Data 3; Parallel Camera Interface Data 5.
M5	P0.26	P0.26	TMR2A_IOA	PCIF_D6	Timer2 I/O 32 Bits or Lower 16 Bits Port Map A; Parallel Camera Interface Data 6.
N5	P0.27	P0.27/USB_EXTCLK	TMR2A_IOB	PCIF_D7	USB External Clock/Timer2 I/O Upper 16 Bits Port Map A; Parallel Camera Interface Data 7.
M8	P0.28	P0.28/SWDIO	—	—	Serial Wire Debug Data I/O. Following any reset, this device pin defaults to AF1 SWDIO.
N8	P0.29	P0.29/SWDCLK	—	—	Serial Wire Debug Clock. Following any reset, this device pin defaults to AF1 SWDCLK. See Bootloader Activation for details on this pin's usage and suggested pullup.
K5	P0.30	P0.30	I2C2A_SCL	PCIF_D8	I2C2 Port Map A Clock; Parallel Camera Interface Data 8.
L5	P0.31	P0.31	I2C2A_SDA	PCIF_D9	I2C2 Port Map A Serial Data; Parallel Camera Interface Data 9.
K2	P1.0	P1.0	UART2A_RX	RV_TCK	UART2 Receive Port Map A; 32-bit RISC-V Test Port Clock.
L2	P1.1	P1.1	UART2A_TX	RV_TMS	UART2 Transmit Port Map A; 32-bit RISC-V Test Port Select.
L3	P1.2	P1.2	I2S0A_SCK	RV_TDI	I2S0 Port Map A Bit Clock; 32-bit RISC-V Test Port Data Input.
M3	P1.3	P1.3	I2S0A_WS	RV_TDO	I2S0 Port Map A Left/Right Clock; 32-bit RISC-V Test Port Data Output.
M4	P1.4	P1.4	I2S0A_SDI	TMR3B_IOA	I2S0 Port Map A Serial Data Input; Timer3 I/O 32 Bits or Lower 16 Bits Port Map B.
N4	P1.5	P1.5	I2S0A_SDO	TMR3B_IOB	I2S0 Port Map A Serial Data Output; Timer3 I/O Upper 16 Bits Port Map B.
K8	P1.6	P1.6	TMR3A_IOA	PCIF_D10	Timer3 I/O 32 Bits or Lower 16 Bits Port Map A; Parallel Camera Interface Data 10.
L8	P1.7	P1.7	TMR3A_IOB	PCIF_D11	Timer3 I/O Upper 16 Bits Port Map A; Parallel Camera Interface Data 11.
K4	P1.8	P1.8	PCIF_HSYNC	RXEV0	Parallel Camera Interface Horizontal Sync; CM4 Rx Event Input.
L4	P1.9	P1.9	PCIF_PCLK	TXEV0	Parallel Camera Interface Pixel Clock; CM4 Tx Event Output.
K13	P1.10	P1.10	SDHC_CDN	ADC_CLK_EXT	Secure Digital Interface Card Present; ADC External Clock Input.
K11	P1.11	P1.11	SDHC_DAT3	—	Secure Digital Interface Data Bus Bit 3.
L11	P1.12	P1.12	SDHC_DAT2	ADC_HW_TRIG_A	Secure Digital Interface Data Bus Bit 2; ADC Trigger Input A.
K12	P1.13	P1.13	SDHC_DAT1	ADC_HW_TRIG_B	Secure Digital Interface Data Bus Bit 1; ADC Trigger Input B.
L12	P1.14	P1.14	SDHC_DAT0	ADC_HW_TRIG_C	Secure Digital Interface Data Bus Bit 0; ADC Trigger Input C.
J11	P1.15	P1.15	SDHC_WP	—	Secure Digital Interface Write Protect.
M11	P1.16	P1.16	SDHC_CMD	—	Secure Digital Interface Bus Command.
L13	P1.17	P1.17	SDHC_CLK	—	Secure Digital Interface Clock.
F4	P2.0	P2.0	AIN0/AIN0N	—	ADC Input 0/Comparator 0 Negative Input.
E4	P2.1	P2.1	AIN1/AIN0P	—	ADC Input 1/Comparator 0 Positive Input.
D4	P2.2	P2.2	AIN2/AIN1N	—	ADC Input 2/Comparator 1 Negative Input.
C4	P2.3	P2.3	AIN3/AIN1P	—	ADC Input 3/Comparator 1 Positive Input.
F3	P2.4	P2.4	AIN4/AIN2N	LPTMR0B_IOA	ADC Input 4/Comparator 2 Negative Input; Low-Power Timer0 I/O Port Map B.
E3	P2.5	P2.5	AIN5/AIN2P	LPTMR1B_IOA	ADC Input 5/Comparator 2 Positive Input; Low-Power Timer1 I/O Port Map B.
D3	P2.6	P2.6/LPTMR0_CLK	AIN6/AIN3N	LPUARTB_RX	Low-Power Timer0 External Clock Input/ADC Input 6/Comparator 3 Negative Input; Low-Power UART0 Receive Port Map B.
C3	P2.7	P2.7/LPTMR1_CLK	AIN7/AIN3P	LPUARTB_TX	Low-Power Timer1 External Clock Input/ADC Input 7/Comparator 3 Positive Input; Low-Power UART Transmit Port Map B.
D11	P3.0	P3.0/PDOWN/WAKEUP	—	—	Power-Down Output; Wakeup Input. This device pin can only be powered by V_DDIOH.
D10	P3.1	P3.1/SQWOUT/WAKEUP	—	—	RTC Square-Wave Output; Wakeup Input. This device pin can only be powered by V_DDIOH.
USB
E13	DP	—	—	—	USB DP Signal. This bidirectional pin carries the positive differential data or single-ended data. This pin is weakly pulled high internally when the USB is disabled.
D13	DM	—	—	—	USB DM Signal. This bidirectional pin carries the negative differential data or single-ended data. This pin is weakly pulled high internally when the USB is disabled.
MIPI CSI-2
B6	CSI_CKP	—	—	—	MIPI CSI-2 receiver differential clock positive input.
A6	CSI_CKN	—	—	—	MIPI CSI-2 receiver differential clock negative input.
C7	CSI_D0P	—	—	—	MIPI CSI-2 receiver differential data lane 0 positive input.
C6	CSI_D0N	—	—	—	MIPI CSI-2 receiver differential data lane 0 negative input.
B7	CSI_D1P	—	—	—	MIPI CSI-2 receiver differential data lane 1 positive input.
A7	CSI_D1N	—	—	—	MIPI CSI-2 receiver differential data lane 1 negative input.

A10

V_BAT

—

Battery Power Supply. Bypass device pin A10 with a 1μF capacitor placed as close as possible to this pin and the V_SSPWR pin. This pin must be connected to V_REGIand V_DDIOH at the circuit board level.

C13

V_REGI

—

Battery Power Supply for the SIMO Switch-Mode Power Supply (SMPS). Bypass this pin with 2 x 47μF capacitors placed as close as possible to this pin and the V_SSPWR pin. This pin must be connected to V_BAT and V_DDIOH. If the power to the device is cycled, the voltage applied to this pin must reach V_{REGI_POR}.

B10

V_DDA

—

1.8V Analog Power Supply. Bypass this pin with a 1μF capacitor placed as close as possible to this pin and V_SSA. This device pin must be connected to V_DDIO.

D12

V_DDB

—

USB Transceiver Supply Voltage. Bypass this pin to V_SSB with a 1.0μF capacitor as close as possible to the package.

A4

V_REF

—

ADC External Reference Input. Bypass this pin with a 1μF capacitor placed as close as possible to this pin and V_SSA as possible. This is the reference input for the analog-to-digital converter (ADC). If the external reference is not used, tie this pin to V_SSA through a 500Ω resistor.

A8

V_COREA

—

Digital Core Supply Voltage A. Bypass this pin to V_SS with a 1μF capacitor placed as close to this pin as possible.

B8

V_COREB

—

Digital Core Supply Voltage B. Bypass this pin to V_SS with a 1μF capacitor placed as close to this pin as possible.

B12

V_BST

—

Boosted Supply Voltage for the Gate Drive of High-Side Switches. Bypass V_BST to LXB with a 3.3nF capacitor.

B11

V_{REGO_A}

—

Buck Converter A Voltage Output. Bypass this pin with a 22μF capacitor to V_SS placed as close as possible to this pin.

C11

V_{REGO_B}

—

Buck Converter B Voltage Output. Bypass this pin with a 22μF capacitor to V_SS placed as close as possible to this pin.

A11

V_{REGO_C}

—

Buck Converter C Voltage Output. Bypass this pin with a 22μF capacitor to V_SS placed as close as possible to this pin.

D1

V_DDIO

—

GPIO Supply Voltage. Bypass this pin to V_SS with a 1.0μF capacitor placed as close as possible to the package.

E1

V_DDIOH

—

GPIO Supply Voltage, High. V_DDIOH ≥ V_DDIO. Bypass this pin to V_SS with a 1.0μF capacitor placed as close as possible to the package. This device pin must be connected to V_REGI and V_BAT.

E12

V_USB0P9

—

Bypass with 1μF capacitor to V_SSB. Do not connect this device pin to any other external circuitry.

C8

V_CSI2P5

—

Bypass with 1μF capacitor to V_SS. Do not connect this device pin to any other external circuitry.

F1, G1, A2, G2, G3, G4, A5, B5, C5, D5, M6, N6, K7, L7, M7, N7, C9, F10, F11, F12, G12, F13, G13

V_SS

—

Digital Ground.

B4

V_SSA

—

Analog Ground. This pin is the return path for V_REF and V_DDA.

A13

V_SSPWR

—

Ground for the SIMO Switch-Mode Power Supply (SMPS). This device pin is the return path for the V_REG.

C12

V_SSB

—

USB Transceiver Ground.

B13

LXA

—

Switching Inductor Input A. Connect a 2.2μH inductor between LXA and LXB.

A12

LXB

—

Switching Inductor Input B. Connect a 2.2μH inductor between LXA and LXB.

N1, N2, N3

V_CNN0

—

Voltage Supply for CNN x16 Processor Quadrant 0. Bypass this pin with 3 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.

H1, H2, H3

V_CNN1

—

Voltage Supply for CNN x16 Processor Quadrant 1. Bypass this pin with 3 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.

N11, N12, N13

V_CNN2

—

Voltage Supply for CNN x16 Processor Quadrant 2. Bypass this pin with 3 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.

H11, H12, H13

V_CNN3

—

Voltage Supply for CNN x16 Processor Quadrant 3. Bypass this pin with 3 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.

M1, M2

V_CNN0RAM

—

Voltage Supply for the RAM for the CNN x16 Processor Quadrant 0. Bypass this pin with 2 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.

J1, J2

V_CNN1RAM

—

Voltage Supply for the RAM for the CNN x16 Processor Quadrant 1. Bypass this pin with 2 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.

M12, M13

V_CNN2RAM

—

Voltage Supply for the RAM for the CNN x16 Processor Quadrant 2. Bypass this pin with 2 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.

J12, J13

V_CNN3RAM

—

Voltage Supply for the RAM for the CNN x16 Processor Quadrant 3. Bypass this pin with 2 x 1μF capacitors as close to this pin as possible and a 22μF capacitor as close as possible to the package.

K9

V_{CNN0_EN}

—

Enable Output for the Voltage Supply for CNN x16 Processor Quadrant 0.

M9

V_{CNN1_EN}

—

Enable Output for the Voltage Supply for CNN x16 Processor Quadrant 1.

L10

V_{CNN2_EN}

—

Enable Output for the Voltage Supply for CNN x16 Processor Quadrant 2.

N10

V_{CNN3_EN}

—

Enable Output for the Voltage Supply for CNN x16 Processor Quadrant 3.

L9

V_{CNN0RAM_EN}

—

Enable Output for the Voltage Supply for the RAM for the CNN x16 Processor Quadrant 0.

N9

V_{CNN1RAM_EN}

—

Enable Output for the Voltage Supply for the RAM for the CNN x16 Processor Quadrant 1.

K10

V_{CNN2RAM_EN}

—

Enable Output for the Voltage Supply for the RAM for the CNN x16 Processor Quadrant 2.

M10

V_{CNN3RAM_EN}

—

Enable Output for the Voltage Supply for the RAM for the CNN x16 Processor Quadrant 3.

C10

RSTN

—

Active-Low, External System Reset Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR reset (resetting all logic on all supplies except for RTC circuitry) and begins execution. This pin has an internal pull-up to the V_DDIOH supply.

B9

32KOUT

—

32kHz Crystal Oscillator Output.

A9

32KIN

—

32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Optionally, this pin can be configured as the input for an external CMOS-level clock source.

A3

HFXIN

—

25MHz Crystal Oscillator Input. Connect a 25MHz crystal between HFXIN and HFXOUT. Optionally, this pin can be configured as the input for an external CMOS-level clock source.

B3

HFXOUT

—

25MHz Crystal Oscillator Output.

K6

P0.0

UART0A_RX

—

UART0 Receive Port Map A. See Bootloader Activation for details on this pin's usage and suggested pull-up.

L6

P0.1

UART0A_TX

—

UART0 Transmit Port Map A.

E11

P0.2

TMR0A__IOA

UART0B_CTS

Timer0 I/O 32 Bits or Lower 16 Bits Port Map A; UART0 Clear to Send Port Map B.

E10

P0.3

P0.3/EXT_CLK

TMR0A_IOB

UART0B_RTS

External Clock for Use as SYS_OSC/Timer0 I/O Upper 16 Bits Port Map A; UART0 Request to Send Port Map B.

H4

P0.4

SPI0A_SS0

TMR0B_IOAN

SPI0 Port Map A Target Select 0; Timer0 Inverted Output Port Map B.

B2

P0.5

SPI0A_MOSI

TMR0B_IOBN

SPI0 Port Map A Controller-Out Target-In Serial Data 0; Timer0 Inverted Output Upper 16 Bits Port Map B.

C2

P0.6

SPI0A_MISO

OWM_IO

SPI0 Port Map A Controller-In Target-Out Serial Data 1; 1-Wire Controller Data I/O.

D2

P0.7

SPI0A_SCK

OWM_PE

SPI0 Port Map A Clock; 1-Wire Controller Pull-up Enable Output.

E2

P0.8

SPI0A_SDIO2

TMR0B_IOA

SPI0 Port Map A Data 2 I/O; Timer0 I/O 32 Bits or Lower 16 Bits Port Map B.

F2

P0.9

SPI0A_SDIO3

TMR0B_IOB

SPI0 Port Map A Data 3 I/O; Timer0 I/O Upper 16 Bits Port Map B.

D9

P0.10

I2C0A_SCL

SPI0_SS2

I2C0 Port Map A Clock; SPI0 Target Select 2.

D8

P0.11

I2C0A_SDA

SPI0_SS1

I2C0 Port Map A Serial Data; SPI0 Target Select 1.

J3

P0.12

UART1A_RX

TMR1B_IOAN

UART1 Receive Port Map A; Timer1 Inverted Output Port Map B.

K3

P0.13

UART1A_TX

TMR1B_IOBN

UART1 Transmit Port Map A; Timer1 Inverted Output Upper 16 Bits Port Map B.

G11

P0.14

TMR1A_IOA

I2S_CLKEXT

Timer1 I/O 32 Bits or Lower 16 Bits Port Map A; I²S External Clock Input.

G10

P0.15

TMR1A_IOB

PCIF_VSYNC

Timer1 I/O Upper 16 Bits Port Map A; Parallel Camera Interface Vertical Sync.

D7

P0.16

I2C1A_SCL

PT2

I2C1 Port Map A Clock; Pulse Train 2.

D6

P0.17

I2C1A_SDA

PT3

I2C1 Port Map A Serial Data; Pulse Train 3.

H10

P0.18

PT0

OWM_IO

Pulse Train 0; 1-Wire Controller Data I/O.

J10

P0.19

PT1

OWM_PE

Pulse Train 1; 1-Wire Controller Pull-up Enable Output.

J4

P0.20

SPI1A_SS0

PCIF_D0

SPI1 Port Map A Target Select 0; Parallel Camera Interface Data 0.

A1

P0.21

SPI1A_MOSI

PCIF_D1

SPI1 Port Map A Controller-Out Target-In Serial Data 0; Parallel Camera Interface Data 1.

B1

P0.22

SPI1A_MISO

PCIF_D2

SPI1 Port Map A Controller-In Target-Out Serial Data 1; Parallel Camera Interface Data 2.

C1

P0.23

SPI1A_SCK

PCIF_D3

SPI1 Port Map A Clock; Parallel Camera Interface Data 3.

K1

P0.24

SPI1A_SDIO2

PCIF_D4

SPI1 Port Map A Data 2; Parallel Camera Interface Data 4.

L1

P0.25

SPI1A_SDIO3

PCIF_D5

SPI1 Port Map A Data 3; Parallel Camera Interface Data 5.

M5

P0.26

TMR2A_IOA

PCIF_D6

Timer2 I/O 32 Bits or Lower 16 Bits Port Map A; Parallel Camera Interface Data 6.

N5

P0.27

P0.27/USB_EXTCLK

TMR2A_IOB

PCIF_D7

USB External Clock/Timer2 I/O Upper 16 Bits Port Map A; Parallel Camera Interface Data 7.

M8

P0.28

P0.28/SWDIO

—

Serial Wire Debug Data I/O. Following any reset, this device pin defaults to AF1 SWDIO.

N8

P0.29

P0.29/SWDCLK

—

Serial Wire Debug Clock. Following any reset, this device pin defaults to AF1 SWDCLK. See Bootloader Activation for details on this pin's usage and suggested pullup.

K5

P0.30

I2C2A_SCL

PCIF_D8

I2C2 Port Map A Clock; Parallel Camera Interface Data 8.

L5

P0.31

I2C2A_SDA

PCIF_D9

I2C2 Port Map A Serial Data; Parallel Camera Interface Data 9.

K2

P1.0

UART2A_RX

RV_TCK

UART2 Receive Port Map A; 32-bit RISC-V Test Port Clock.

L2

P1.1

UART2A_TX

RV_TMS

UART2 Transmit Port Map A; 32-bit RISC-V Test Port Select.

L3

P1.2

I2S0A_SCK

RV_TDI

I2S0 Port Map A Bit Clock; 32-bit RISC-V Test Port Data Input.

M3

P1.3

I2S0A_WS

RV_TDO

I2S0 Port Map A Left/Right Clock; 32-bit RISC-V Test Port Data Output.

M4

P1.4

I2S0A_SDI

TMR3B_IOA

I2S0 Port Map A Serial Data Input; Timer3 I/O 32 Bits or Lower 16 Bits Port Map B.

N4

P1.5

I2S0A_SDO

TMR3B_IOB

I2S0 Port Map A Serial Data Output; Timer3 I/O Upper 16 Bits Port Map B.

K8

P1.6

TMR3A_IOA

PCIF_D10

Timer3 I/O 32 Bits or Lower 16 Bits Port Map A; Parallel Camera Interface Data 10.

L8

P1.7

TMR3A_IOB

PCIF_D11

Timer3 I/O Upper 16 Bits Port Map A; Parallel Camera Interface Data 11.

K4

P1.8

PCIF_HSYNC

RXEV0

Parallel Camera Interface Horizontal Sync; CM4 Rx Event Input.

L4

P1.9

PCIF_PCLK

TXEV0

Parallel Camera Interface Pixel Clock; CM4 Tx Event Output.

K13

P1.10

SDHC_CDN

ADC_CLK_EXT

Secure Digital Interface Card Present; ADC External Clock Input.

K11

P1.11

SDHC_DAT3

—

Secure Digital Interface Data Bus Bit 3.

L11

P1.12

SDHC_DAT2

ADC_HW_TRIG_A

Secure Digital Interface Data Bus Bit 2; ADC Trigger Input A.

K12

P1.13

SDHC_DAT1

ADC_HW_TRIG_B

Secure Digital Interface Data Bus Bit 1; ADC Trigger Input B.

L12

P1.14

SDHC_DAT0

ADC_HW_TRIG_C

Secure Digital Interface Data Bus Bit 0; ADC Trigger Input C.

J11

P1.15

SDHC_WP

—

Secure Digital Interface Write Protect.

M11

P1.16

SDHC_CMD

—

Secure Digital Interface Bus Command.

L13

P1.17

SDHC_CLK

—

Secure Digital Interface Clock.

F4

P2.0

AIN0/AIN0N

—

ADC Input 0/Comparator 0 Negative Input.

E4

P2.1

AIN1/AIN0P

—

ADC Input 1/Comparator 0 Positive Input.

D4

P2.2

AIN2/AIN1N

—

ADC Input 2/Comparator 1 Negative Input.

C4

P2.3

AIN3/AIN1P

—

ADC Input 3/Comparator 1 Positive Input.

F3

P2.4

AIN4/AIN2N

LPTMR0B_IOA

ADC Input 4/Comparator 2 Negative Input; Low-Power Timer0 I/O Port Map B.

E3

P2.5

AIN5/AIN2P

LPTMR1B_IOA

ADC Input 5/Comparator 2 Positive Input; Low-Power Timer1 I/O Port Map B.

D3

P2.6

P2.6/LPTMR0_CLK

AIN6/AIN3N

LPUARTB_RX

Low-Power Timer0 External Clock Input/ADC Input 6/Comparator 3 Negative Input; Low-Power UART0 Receive Port Map B.

C3

P2.7

P2.7/LPTMR1_CLK

AIN7/AIN3P

LPUARTB_TX

Low-Power Timer1 External Clock Input/ADC Input 7/Comparator 3 Positive Input; Low-Power UART Transmit Port Map B.

D11

P3.0

P3.0/PDOWN/WAKEUP

—

Power-Down Output; Wakeup Input. This device pin can only be powered by V_DDIOH.

D10

P3.1

P3.1/SQWOUT/WAKEUP

—

RTC Square-Wave Output; Wakeup Input. This device pin can only be powered by V_DDIOH.

E13

DP

—

USB DP Signal. This bidirectional pin carries the positive differential data or single-ended data. This pin is weakly pulled high internally when the USB is disabled.

D13

DM

—

USB DM Signal. This bidirectional pin carries the negative differential data or single-ended data. This pin is weakly pulled high internally when the USB is disabled.

B6

CSI_CKP

—

MIPI CSI-2 receiver differential clock positive input.

A6

CSI_CKN

—

MIPI CSI-2 receiver differential clock negative input.

C7

CSI_D0P

—

MIPI CSI-2 receiver differential data lane 0 positive input.

C6

CSI_D0N

—

MIPI CSI-2 receiver differential data lane 0 negative input.

B7

CSI_D1P

—

MIPI CSI-2 receiver differential data lane 1 positive input.

A7

CSI_D1N

—

MIPI CSI-2 receiver differential data lane 1 negative input.