Electrical Characteristics

Electrical Characteristics
(Limits are 100% tested at T_A = +25°C and T_A = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at T_A = +105°C.)
PARAMETER	SYMBOL	CONDITIONS		MIN	TYP	MAX	UNITS
POWER SUPPLIES
Input Supply Voltage, Battery	V_BAT	V_REGI, V_BAT, and V_DDIOH must be connected together at the circuit-board level.		2.85	3.3	3.6	V
Input Supply Voltage, SIMO	V_REGI	V_REGI, V_BAT, and V_DDIOH must be connected together at the circuit-board level.		2.85	3.3	3.6	V
Input Supply Voltage Core A	V_COREA			0.9	1.1	1.21	V
Input Supply Voltage Core B	V_COREB			0.9	1.1	1.21	V
Input Supply Voltage, Analog	V_DDA	V_DDA and V_DDIO must be connected at the circuit-board level.		1.71	1.8	1.89	V
Input Supply Voltage, GPIO	V_DDIO	V_DDA and V_DDIO must be connected at the circuit-board level.		1.71	1.8	1.89	V
Input Supply Voltage, GPIO (High)	V_DDIOH	V_REGI, V_BAT, and V_DDIOH must be connected together at the circuit-board level.		2.85	3.3	3.6	V
Input Supply Voltage, CNN	V_CNNX	Switched off by V_{CNNX_EN}. When switched on, the voltage applied must be the same as V_COREA.		0.99	1.1	1.21	V
Input Supply Voltage, CNN RAM	V_CNNXRAM	Switched off by V_{CNNXRAM_EN}. When switched on, the voltage applied must be the same as V_COREA.		0.99	1.1	1.21	V
Power-Fail Reset Voltage	V_RST	Monitors V_COREA			0.76		V
		Monitors V_COREB		0.72	0.76
		Monitors V_DDA		1.56	1.64	1.69
		Monitors V_DDIO		1.56	1.64	1.69
		Monitors V_DDIOH		1.56	1.64	1.69
		Monitors V_BAT			2.74
Power-On Reset Voltage	V_POR	Monitors V_COREA			0.63		V
Power-On Reset Voltage	V_POR	Monitors V_DDA			1.25		V
V_REGI Current, ACTIVE Mode	I_{REGI_DACT}	Dynamic, IPO enabled, f_{SYS_CLK(MAX)} = 120MHz, total current into V_REGI pin, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, CM4 in Active mode executing CoreMark^®, RV32 in ACTIVE mode executing While(1), ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			32		μA/MHz
		Dynamic, IPO enabled, f_{SYS_CLK(MAX)} = 120MHz, total current into V_REGI pin, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, CM4, and RV32 in ACTIVE mode executing While(1), ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			27.7
		Dynamic, IPO enabled, f_{SYS_CLK(MAX)} = 120MHz, total current into V_REGI pin, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, CM4 in ACTIVE mode executing While(1), RV32 in SLEEP mode, ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			23.9
		Dynamic, total current into V_REGI pin, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, f_{SYS_CLK} = ISO; CM4 in SLEEP mode, RV32 in ACTIVE mode running from PCLK executing While(1), ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			20.9
	I_{REGI_FACT}	Fixed, IPO enabled, ISO enabled, total current into V_REGI, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, CM4 in ACTIVE mode 0MHz, RV32 in ACTIVE mode 0MHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			823		μA
V_REGI Current, SLEEP Mode	I_{REGI_DSLP}	Dynamic, IPO enabled, f_{SYS_CLK(MAX)} = 120MHz, ISO enabled, total current into V_REGI pins, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, CM4 in SLEEP mode, RV32 in SLEEP mode, ECC disabled, all CNN quadrants disabled, all CNN memory disabled, standard DMA with 2 channels active; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			11.8		μA/MHz
V_REGI Current, SLEEP Mode	I_{REGI_FSLP}	Fixed, IPO enabled, ISO enabled, total current into V_REGI pins, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, CM4 in SLEEP mode, RV32 in SLEEP mode, ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			1.3		mA
V_REGI Current, LOW POWER Mode	I_{REGI_DLP}	Dynamic, ISO enabled, total current into V_REGI pins, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, CM4 powered off, RV32 in ACTIVE mode executing While(1), f_{SYS_CLK(MAX)} = 60MHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			18.9		μA/MHz
V_REGI Current, LOW POWER Mode	I_{REGI_FLP}	Fixed, ISO enabled, total current into V_REGI pins, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, CM4 powered off, RV32 in ACTIVE mode 0MHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			393		μA
V_REGI Current, MICRO POWER Mode	I_{REGI_DMP}	Dynamic, ERTCO enabled, IBRO enabled, total current into V_REGI pins, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, LPUART active, f_LPUART = 32.768kHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			230		μA
V_REGI Current, STANDBY Mode	I_{REGI_STBY}	Fixed, total current into V_REGI pins, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			9.8		μA
V_REGI Current, BACKUP Mode	I_{REGI_BK}	Total current into V_REGI pins, V_REGI = 3.3V, V_COREA = V_COREB = 1.1V, RTC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA	All SRAM retained		8.2		μA
			No SRAM retention		3
			SRAM0 retained		3.5
			SRAM0 and SRAM1 retained		4
			SRAM0, SRAM1, and SRAM2 retained		4.8
V_REGI Current, POWER DOWN Mode	I_{REGI_PDM}	Total current into V_REGI pins, V_REGI = 3.3V; inputs tied to V_SS, V_DDIO, or V_DDIOH; outputs source/sink 0mA			0.76		μA
V_{REGO_A} Output Voltage Range	V_{REGO_A_RANGE}	V_REGI ≥ V_{REGO_A} + 200mV		0.5	1.8	1.85	V
V_{REGO_B} Output Voltage Range	V_{REGO_B_RANGE}	V_REGI ≥ V_{REGO_B} + 200mV		0.5	1.0	1.25	V
V_{REGO_C} Output Voltage Range	V_{REGO_C_RANGE}	V_REGI ≥ V_{REGO_C} + 200mV		0.5	1.0	1.25	V
V_{REGO_A} Output Current	V_{REGO_A_IOUT}	V_{REGO_A} output current			5	50	mA
V_{REGO_B} Output Current	V_{REGO_B_IOUT}	V_{REGO_B} output current			5	50	mA
V_{REGO_C} Output Current	V_{REGO_C_IOUT}	V_{REGO_C} output current			10	100	mA
V_{REGO_X} Output Current Combined	V_{REGO_X_IOUT_TOT}	All three V_{REGO_X} outputs combined			20	100	mA
V_{REGO_X} Efficiency	V_{REGO_X_EFF}	V_REGI= 3.3V, V_{REGO_X}= 1.1V, load = 30mA			90		%
SLEEP Mode Resume Time	t_{SLP_ON}	Time from power mode exit to execution of first user instruction			0.74		μs
LOW-POWER Mode Resume Time	t_{LP_ON}	Time from power mode exit to execution of first user instruction			1.62		μs
MICROPOWER Mode Resume Time	t_{MP_ON}	Time from power mode exit to execution of first user instruction			17.4		μs
STANDBY Mode Resume Time	t_{STBY_ON}	Time from power mode exit to execution of first user instruction			29.6		μs
BACKUP Mode Resume Time	t_{BKU_ON}	Time from power mode exit to execution of first user instruction			1.9		ms
POWER-DOWN Mode Resume Time	t_{PDM_ON}	Time from power mode exit to execution of first user instruction			5		ms
CLOCKS
System Clock Frequency	f_{SYS_CLK}			0		120	MHz
Internal Phase Locked Loop (IPLL)	f_IPLL	External 25MHz crystal connected to HFXIN and HFXOUT			100		MHz
Internal Phase Locked Loop (IPLL)	f_{IPLL_CNN}	External 25MHz crystal connected to HFXIN and HFXOUT			200		MHz
Internal Primary Oscillator (IPO)	f_IPO				120		MHz
Internal Secondary Oscillator (ISO)	f_ISO				60		MHz
Internal Baud Rate Oscillator (IBRO)	f_IBRO				7.3728		MHz
Internal Nanoring Oscillator (INRO)	f_INRO	8kHz selected			8		kHz
		16kHz selected			16
		30kHz selected			30
External RTC Oscillator (ERTCO)	f_ERTCO	32kHz watch crystal, C_L = 6pF, ESR < 90kΩ, C₀ ≤ 2pF			32.768		kHz
RTC Operating Current	I_RTC	All power modes			0.3		μA
RTC Power-Up Time	t_{RTC_ ON}				250		ms
External I²S Clock Input Frequency	f_{EXT_I2S_CLK}	I2S_CLKEXT selected				25	MHz
External System Clock Input Frequency	f_{EXT_CLK}	EXT_CLK selected				80	MHz
External Low Power Timer1 Clock Input Frequency	f_{EXT_LPTMR1_CLK}	LPTMR1_CLK selected				8	MHz
External Low Power Timer2 Clock Input Frequency	f_{EXT_LPTMR2_CLK}	LPTMR2_CLK selected				8	MHz
CONVOLUTIONAL NEURAL NETWORK
CNN Current Mode A	I_{VCNN_ALL_A}	CNN inactive current, CNN enabled/inactive, CNN clocks disabled, all CNN quadrants and SRAMs powered			15.3		mA
	I_{CNN0RAM_A}				0.12
	I_{CNN1RAM_A}				0.12
	I_{CNN2RAM_A}				0.12
	I_{CNN3RAM_A}				0.12
	I_{COREA_A}				8.4
	I_{CNN_TOTAL_A}				24.4
CNN Current Mode B	I_{VCNN_ALL_B}	50MHz clock rate, CNN active current, max power network, random data and random mask configuration, CNN quadrant 0 enabled, CNN quadrant 1/2/3 disabled, all CNN quadrants and SRAMs powered			59.5		mA
	I_{CNN0RAM_B}				11.9
	I_{CNN1RAM_B}				0.13
	I_{CNN2RAM_B}				0.13
	I_{CNN3RAM_B}				0.13
	I_{COREA_B}				4.5
	I_{CNN_TOTAL_B}				76.2
CNN Current Mode C	I_{VCNN_ALL_C}	50MHz clock rate, CNN active current, all CNN quadrants and SRAMs powered, unet_v5 functional test			89.1		mA
	I_{CNN0RAM_C}				7.5
	I_{CNN1RAM_C}				4.9
	I_{CNN2RAM_C}				4.5
	I_{CNN3RAM_C}				4.5
	I_{COREA_C}				4.5
	I_{CNN_TOTAL_C}				115
CNN Current Mode D	I_{VCNN_ALL_D}	50MHz clock rate, CNN active current, max power network, random data and random mask configuration, all CNN quadrants and SRAMs powered			187		mA
	I_{CNN0RAM_D}				13
	I_{CNN1RAM_D}				13
	I_{CNN2RAM_D}				13
	I_{CNN3RAM_D}				13
	I_{COREA_D}				4.5
	I_{CNN_TOTAL_D}				243
CNN Current Mode E	I_{VCNN_ALL_E}	50MHz clock rate, CNN active current, max power network, data, mask configuration, all CNN quadrants and SRAMs powered			254		mA
	I_{CNN0RAM_E}				13.8
	I_{CNN1RAM_E}				13.9
	I_{CNN2RAM_E}				13.8
	I_{CNN3RAM_E}				13.8
	I_{COREA_E}				4.5
	I_{CNN_TOTAL_E}				313
CNN Current Mode F	I_{VCNN_ALL_F}	200MHz clock rate, CNN active current, max power network, random data, and random mask configuration, CNN quadrant 0 enabled, CNN quadrant 1/2/3 disabled, all CNN quadrants and SRAMs powered			117		mA
	I_{CNN0RAM_F}				24.5
	I_{CNN1RAM_F}				0.132
	I_{CNN2RAM_F}				0.131
	I_{CNN3RAM_F}				0.128
	I_{COREA_F}				7.9
	I_{CNN_TOTAL_F}				150
CNN Current Mode G	I_{VCNN_ALL_G}	200MHz clock rate, CNN active current, all CNN quadrants and SRAMs powered, unet_v5 functional test			242		mA
	I_{CNN0RAM_G}				16
	I_{CNN1RAM_G}				10.4
	I_{CNN2RAM_G}				9.5
	I_{CNN3RAM_G}				9.5
	I_{COREA_G}				7.9
	I_{CNN_TOTAL_G}				295
CNN Current Mode H	I_{VCNN_ALL_H}	200MHz clock rate, CNN active current, max processing configuration, max power network, random data, and random mask configuration, all CNN quadrants and SRAMs powered			1060		mA
	I_{CNN0RAM_H}				94
	I_{CNN1RAM_H}				94
	I_{CNN2RAM_H}				94
	I_{CNN3RAM_H}				94
	I_{COREA_H}				8.2
	HI_{CNN_TOTAL_7}				1440
CNN Current Mode J	I_{VCNN_ALL_J}	200MHz clock rate, CNN active current, max processing configuration, max power network, data, mask configuration, all CNN quadrants and SRAMs powered			1450		mA
	I_{CNN0RAM_J}				99
	I_{CNN1RAM_J}				99
	I_{CNN2RAM_J}				99
	I_{CNN3RAM_J}				99
	I_{COREA_J}				8.4
	I_{CNN_TOTAL_J}				1852
GENERAL-PURPOSE I/O
Input Low Voltage for All GPIOs Except P3.0 and P3.1	V_{IL_VDDIO}	V_DDIO selected as I/O supply; P3.0 and P3.1 can only use V_DDIOH as I/O supply				0.3 × V_DDIO	V
Input Low Voltage for All GPIOs	V_{IL_VDDIOH}	V_DDIOH selected as I/O supply				0.3 × V_DDIOH	V
Input Low Voltage for RSTN	V_{IL_RSTN}				0.5 x V_DDIOH		V
Input High Voltage for All GPIOs Except P3.0 and P3.1	V_{IH_VDDIO}	V_DDIO selected as I/O supply; P3.0 and P3.1 can only use V_DDIOH as I/O supply		0.7 × V_DDIO			V
Input High Voltage for All GPIOs	V_{IH_VDDIOH}	V_DDIOH selected as I/O supply		0.7 × V_DDIOH			V
Input High Voltage for RSTN	V_{IH_RSTN}				0.5 x V_DDIOH		V
Output Low Voltage for All GPIOs Except P3.0 and P3.1	V_{OL_VDDIO}	P3.0 and P3.1 can only use V_DDIOH as I/O supply	V_DDIO selected as I/O supply, V_DDIO = 1.71V, GPIOn_DS_SEL[1:0] = 00, I_OL = 1mA		0.2	0.4	V
			V_DDIO selected as I/O supply, V_DDIO = 1.71V, GPIOn_DS_SEL[1:0] = 01, I_OL = 2mA		0.2	0.4
			V_DDIO selected as I/O supply, V_DDIO = 1.71V, GPIOn_DS_SEL[1:0] = 10, I_OL = 4mA		0.2	0.4
			V_DDIO selected as I/O supply, V_DDIO = 1.71V, GPIOn_DS_SEL[1:0] = 11, I_OL = 8mA		0.2	0.4
Output Low Voltage for All GPIOs	V_{OL_VDDIOH}	V_DDIOH selected as I/O supply, V_DDIOH = 2.85V, GPIOn_DS_SEL[1:0] = 00, I_OL = 1mA			0.2	0.4	V
		V_DDIOH selected as I/O supply, V_DDIOH = 2.85V, GPIOn_DS_SEL[1:0] = 01, I_OL = 2mA			0.2	0.4
		V_DDIOH selected as I/O supply, V_DDIOH = 2.85V, GPIOn_DS_SEL[1:0] = 10, I_OL = 4mA			0.2	0.4
		V_DDIOH selected as I/O supply, V_DDIOH = 2.85V, GPIOn_DS_SEL[1:0] = 11, I_OL = 8mA			0.2	0.4
Combined I_OL, All GPIOs	I_{OL_TOTAL}					48	mA
Output High Voltage for All GPIOs Except P3.0 and P3.1	V_{OH_VDDIO}	P3.0 and P3.1 can only use V_DDIOH as I/O supply	V_DDIO selected as I/O supply, V_DDIO = 1.71V, GPIOn_DS_SEL[1:0] = 00, I_OL = -1mA	V_DDIO - 0.4			V
			V_DDIO selected as I/O supply, V_DDIO = 1.71V, GPIOn_DS_SEL[1:0] = 01, I_OL = -2mA	V_DDIO - 0.4
			V_DDIO selected as I/O supply, V_DDIO = 1.71V, GPIOn_DS_SEL[1:0] = 10, I_OL = -4mA	V_DDIO - 0.4
			V_DDIO selected as I/O supply, V_DDIO = 1.71V, GPIOn_DS_SEL[1:0] = 11, I_OL = -8mA	V_DDIO - 0.4
Output High Voltage for All GPIOs Except P3.0 and P3.1	V_{OH_VDDIOH}	V_DDIOH selected as I/O supply, V_DDIOH = 2.85V, GPIOn_DS_SEL[1:0] = 00, I_OL = -1mA		V_DDIOH - 0.4			V
		V_DDIOH selected as I/O supply, V_DDIOH = 2.85V, GPIOn_DS_SEL[1:0] = 01, I_OL = -2mA		V_DDIOH - 0.4
		V_DDIOH selected as I/O supply, V_DDIOH = 2.85V, GPIOn_DS_SEL[1:0] = 10, I_OL = -4mA		V_DDIOH - 0.4
		V_DDIOH selected as I/O supply, V_DDIOH = 2.85V, GPIOn_DS_SEL[1:0] = 11, I_OL = -8mA		V_DDIOH - 0.4
Output High Voltage for P3.0 and P3.1	V_{OH_VDDIOH}	V_DDIOH = 2.85V, GPIOn_DS_SEL[1:0] fixed at 00, I_OL = -1mA		V_DDIOH - 0.4			V
Combined I_OH, All GPIOs	I_{OH_TOTAL}					-48	mA
Input Hysteresis (Schmitt)	V_HYS				300		mV
Input Leakage Current Low	I_IL	V_DDIO = 1.89V, V_DDIOH = 3.6V, V_DDIOHselected as I/O supply, V_IN = 0V, internal pull-up disabled		-200		+200	nA
Input Leakage Current High	I_IH	V_DDIO = 1.89V, V_DDIOH = 3.6V, V_DDIOH selected as I/O supply, V_IN = 3.6V, internal pull-down disabled		-1000		+1000	nA
	I_OFF	V_DDIO = 0V, V_DDIOH = 0V, V_DDIO selected as I/O supply, V_IN < 1.89V		-1		+1	μA
	I_IH3V	V_DDIO = 1.71V, V_DDIOH = 2.85V, V_DDIO selected as I/O supply, V_IN = 3.6V		-2		+2	μA
Input Pull-up Resistor RSTN	R_{PU_R}	Pull-up to V_DDIOH			25		kΩ
Input Pull-up/Pull-down Resistor for All GPIO	R_PU1	Normal resistance, P1M = 0			25		kΩ
Input Pull-up/Pull-down Resistor for All GPIO	R_PU2	Highest resistance, P1M = 1			1		MΩ
12-BIT SAR ADC
Resolution					12		bits
Effective Number of Bits	ENOB	ADC_CLKCTRL.clksel = 11; AINx input pk--pk = V_REF - 10mV			10		bits
External Reference Voltage	V_REF	V_REF ≤ V_DDIOH		2.048		V_DDIOH	V
Internal Reference Voltage	V_{INT_REF}	MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 0			1.25		V
Internal Reference Voltage	V_{INT_REF}	MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 1			2.048		V
ADC Clock Rate	f_ACLK				1		MHz
ADC Clock Period	t_ACLK				1/f_ACLK		μs
Input Voltage Range	V_AIN	AIN[7:0], ADC_DATA.chan = [7:0]	MCR_ADCCFG2.chX = 00	V_SSA+ 0.05		V_REF	V
			MCR_ADCCFG2.chX = 01	V_SSA+ 0.05		MIN(2 x V_REF,V_DDIOH)
			MCR_ADCCFG2.chX = 10	V_SSA+ 0.05		MIN(2 x V_REF,V_DDIOH)
Input Impedance	R_AIN	MCR_ADCCFG2.chX = 01			5		kΩ
Input Impedance	R_AIN	MCR_ADCCFG2.chX = 10			50		kΩ
Analog Input Capacitance	C_AIN	Fixed capacitance to V_SSA			2		pF
Analog Input Capacitance	C_AIN	Dynamically switched capacitance			1.2		pF
Integral Nonlinearity	INL				±1.5		LSb
Differential Nonlinearity	DNL				±0.75		LSb
Offset Error	V_OS	Chopping disabled			±9		LSb
Offset Error	V_OS	Chopping enabled			±0.2		LSb
ADC Active Current	I_ADC	ADC active, reference buffer enabled, ADC_CLKCTRL.clksel = 11, ADC_CLKCTRL.clkdiv = 100	MCR_ADCCFG0.ext_ref = 0, MCR_ADCCFG0.ref_sel = 0, V_BAT = 3.3V		361		µA
			MCR_ADCCFG0.ext_ref = 0, MCR_ADCCFG0.ref_sel = 1, V_BAT = 3.3V		361
			MCR_ADC_CFG0.ext_ref = 0, MCR_ADC_CFG0.ref_sel = 0, V_BAT = 3.3V		229
			MCR_ADCCFG0.ext_ref = 0, MCR_ADCCFG0.ref_sel = 1, V_BAT = 3.3V		229
			MCR_ADCCFG0.ext_ref = 0, MCR_ADCCFG0.ref_sel = 0, V_BAT = 3.3V		162
			MCR_ADCCFG0.ext_ref = 0, MCR_ADCCFG0.ref_sel = 1, V_BAT = 3.3V		162
ADC Sample Rate	f_ADC	ADC_CLKCTRL.clkdiv = 0bX00				1	Msps
		ADC_CLKCTRL.clkdiv = 0bX01				0.625
		ADC_CLKCTRL.clkdiv = 0bX10				0.125
ADC Setup Time	t_{ADC_SU}	Any power-up of ADC clock or ADC bias to ADC_STATUS.ready = 1				500	µs
ADC Input Leakage	I_{ADC_LEAK}	ADC inactive or channel not selected			1.5		nA
Bandgap Temperature Coefficient	V_TEMPCO	Box method			± 45		ppm
COMPARATORS
Input Offset Voltage	V_OFFSET				±7		mV
Input Hysteresis	V_HYST	AINCOMPHYST[1:0] = 00			22		mV
		AINCOMPHYST[1:0] = 01			50
		AINCOMPHYST[1:0] = 10			2
		AINCOMPHYST[1:0] = 11			7
Input Voltage Range	V_{IN_CMP}	Common-mode range		0.6		1.35	V
USB
USB Transceiver Supply Voltage	V_DDB			3.0	3.3	3.6	V
Pin Capacitance (DP, DM)	C_{IN_USB}	Pin to V_SSB			8		pF
Driver Output Resistance	R_DRV	Steady state drive			44 ±10%		Ω
USB / FULL SPEED
Single-Ended Input High Voltage (DP, DM)	V_{IH_USB}			2.1			V
Single-Ended Input Low Voltage (DP, DM)	V_{IL_USB}					0.5	V
Output High Voltage (DP, DM)	V_{OH_USB}	R_L= 1.5kΩ from DP and DM to V_SSB, I_OH= -4mA		2.8		V_DDB	V
Output Low Voltage (DP, DM)	V_{OL_USB}	R_L= 1.5kΩ from DP to V_DDB, I_OL= 4mA		V_SS		0.3	V
Differential Input Sensitivity	V_DI	\|DP to DM\|		0.2			V
Common-Mode Voltage Range	V_CM	Includes V_DI range		0.8		2.5	V
Transition Time (Rise/Fall) DP, DM	t_RF	C_L= 50pF		4		20	ns
Pull-up Resistor on Upstream Ports	R_PU			1.05	1.5	1.95	kΩ
USB / HI-SPEED
Hi-Speed Data Signaling Common-Mode Voltage Range	V_HSCM			-50		+500	mV
Hi-Speed Squelch Detection Threshold	V_HSSQ	Squelch detected			100		mV
Hi-Speed Squelch Detection Threshold	V_HSSQ	No squelch detected			200		mV
Hi-Speed Idle Level Output Voltage	V_HSOI			-10		+10	mV
Hi-Speed Low-Level Output Voltage	V_HSOL			-10		+10	mV
Hi-Speed High-Level Output Voltage	V_HSOH				400 ±40		mV
Chirp-J Output Voltage (Differential)	V_CHIRPJ				900 ±200		mV
Chirp-K Output Voltage (Differential)	V_CHIRPK				-700 ±200		mV
FLASH MEMORY
Flash Erase Time	t_{M_ERASE}	Mass erase			20		ms
Flash Erase Time	t_{P_ERASE}	Page erase			20		ms
Flash Programming Time per Word	t_PROG	32-bit programming mode, f_{FLC_CLK} = 1MHz			42		μs
Flash Endurance				10			kcycles
Data Retention	t_RET	T_A = +105°C		10			years
MIPI CSI-2
Data Rate per CSI-2 Lane						600	Mbps
Frequency (CSI_CKP, CSI_CKN)	f_CK					300	MHz
MIPI CSI-2 / HIGH-SPEED DC SPECIFICATIONS
DC Common-Mode Voltage (CSI_D0P, CSI_D0N, CSI_D1P, CSI_D1N, CSI_CKP, CSI_CKN)	V_CMDC			70		330	mV
Differential Input High Threshold (CSI_D0P, CSI_D0N, CSI_D1P, CSI_D1N, CSI_CKP, CSI_CKN)	V_DIHT				40		mV
Differential Input Low Threshold (CSI_D0P, CSI_D0N, CSI_D1P, CSI_D1N, CSI_CKP, CSI_CKN)	V_DILT				-40		mV
Differential Input Impedance (CSI_D0P, CSI_D0N, CSI_D1P, CSI_D1N, CSI_CKP, CSI_CKN)	Z_DI			80	100	120	Ω
MIPI CSI-2 / HIGH-SPEED AC SPECIFICATIONS
Data to Clock Setup Time (CSI_D0P, CSI_D0N, CSI_D1P, CSI_D1N, CSI_CKP, CSI_CKN)	t_SETUP			$0.15 \times \frac{1}{f_{CK}}$			ns
Data to Clock Hold Time (CSI_D0P, CSI_D0N, CSI_D1P, CSI_D1N, CSI_CKP, CSI_CKN)	t_HOLD			$0.15 \times \frac{1}{f_{CK}}$			ns
MIPI CSI-2 / LOW-POWER DC SPECIFICATIONS
Input High Voltage (CSI_D0P, CSI_D0N, CSI_D1P, CSI_D1N, CSI_CKP, CSI_CKN)	V_IH			850			mV
Input Low Threshold (CSI_D0P, CSI_D0N, CSI_D1P, CSI_D1N, CSI_CKP, CSI_CKN)	V_IL					550	mV
Input Hysteresis (CSI_D0P, CSI_D0N, CSI_D1P, CSI_D1N, CSI_CKP, CSI_CKN)	V_HYS			25			mV

Electrical Characteristics—I²C
(TIming specifications are guaranteed by design and not production tested.)
PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
STANDARD-MODE
Output Fall Time	t_OF	Standard-mode, from V_IH(MIN) to V_IL(MAX)		150		ns
SCL Clock Frequency	f_SCL		0		100	kHz
Low Period SCL Clock	t_LOW		4.7			μs
High Time SCL Clock	t_HIGH		4.0			μs
Setup Time for Repeated Start Condition	t_SU;STA		4.7			μs
Hold Time for Repeated Start Condition	t_HD;STA		4.0			μs
Data Setup Time	t_SU;DAT			300		ns
Data Hold Time	t_HD;DAT			10		ns
Rise Time for SDA and SCL	t_R			800		ns
Fall Time for SDA and SCL	t_F			200		ns
Setup Time for a Stop Condition	t_SU;STO		4.0			μs
Bus Free Time Between a Stop and Start Condition	t_BUS		4.7			μs
Data Valid Time	t_VD;DAT		3.45			μs
Data Valid Acknowledge Time	t_VD;ACK		3.45			μs
FAST-MODE
Output Fall Time	t_OF	From V_IH(MIN) to V_IL(MAX)		150		ns
Pulse Width Suppressed by Input Filter	t_SP			75		ns
SCL Clock Frequency	f_SCL		0		400	kHz
Low Period SCL Clock	t_LOW		1.3			μs
High Time SCL Clock	t_HIGH		0.6			μs
Setup Time for Repeated Start Condition	t_SU;STA		0.6			μs
Hold Time for Repeated Start Condition	t_HD;STA		0.6			μs
Data Setup Time	t_SU;DAT			125		ns
Data Hold Time	t_HD;DAT			10		ns
Rise Time for SDA and SCL	t_R			30		ns
Fall Time for SDA and SCL	t_F			30		ns
Setup Time for a Stop Condition	t_SU;STO		0.6			μs
Bus Free Time Between a Stop and Start Condition	t_BUS		1.3			μs
Data Valid Time	t_VD;DAT		0.9			μs
Data Valid Acknowledge Time	t_VD;ACK		0.9			μs
FAST-MODE PLUS
Output Fall Time	t_OF	From V_IH(MIN) to V_IL(MAX)		80		ns
Pulse Width Suppressed by Input Filter	t_SP			75		ns
SCL Clock Frequency	f_SCL		0		1000	kHz
Low Period SCL Clock	t_LOW		0.5			μs
High Time SCL Clock	t_HIGH		0.26			μs
Setup Time for Repeated Start Condition	t_SU;STA		0.26			μs
Hold Time for Repeated Start Condition	t_HD;STA		0.26			μs
Data Setup Time	t_SU;DAT			50		ns
Data Hold Time	t_HD;DAT			10		ns
Rise Time for SDA and SCL	t_R			50		ns
Fall Time for SDA and SCL	t_F			30		ns
Setup Time for a Stop Condition	t_SU;STO		0.26			μs
Bus Free Time Between a Stop and Start Condition	t_BUS		0.5			μs
Data Valid Time	t_VD;DAT		0.45			μs
Data Valid Acknowledge Time	t_VD;ACK		0.45			μs

Electrical Characteristics—SD/SDIO/SDHC/MMC
(TIming specifications are guaranteed by design and not production tested.)
PARAMETER	SYMBOL	MIN	TYP	MAX	UNITS
Clock Frequency in Data Transfer Mode	f_{SDHC_CLK}	0		f_PCLK	MHz
Clock Period	t_CLK		1/f_{SDHC_CLK}		ns
Clock Low Time	t_WCL		7		ns
Clock High Time	t_WCH		7		ns
Input Setup Time	t_ISU		5		ns
Input Hold Time	t_IHLD		1		ns
Output Valid Time	t_OVLD		5		ns
Output Hold Time	t_OHLD		6		ns

Electrical Characteristics—SPI
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
CONTROLLER MODE
SPI Controller Operating Frequency for SPI0	f_MCK0	f_{SYS_CLK}= 120MHz, f_MCK0(MAX)= f_{SYS_CLK}/2			60	MHz
SPI Controller Operating Frequency for SPI1	f_MCK1	f_{SYS_CLK}= 120MHz, f_MCK1(MAX)= f_{SYS_CLK}/4			30	MHz
SPI Controller SCK Period	t_MCKX			1/f_MCKX		ns
SCK Output Pulse-Width High/Low	t_MCH, t_MCL		t_MCKX/2			ns
MOSI Output Hold Time After SCK Sample Edge	t_MOH		t_MCKX/2			ns
MOSI Output Valid to Sample Edge	t_MOV		t_MCKX/2			ns
MOSI Output Hold Time After SCK Low Idle	t_MLH			t_MCKX/2		ns
MISO Input Valid to SCK Sample Edge Setup	t_MIS			5		ns
MISO Input to SCK Sample Edge Hold	t_MIH			t_MCKX/2		ns
TARGET MODE
SPI Target Operating Frequency	f_SCK				60	MHz
SPI Target SCK Period	t_SCK			1/f_SCK		ns
SCK Input Pulse-Width High/Low	t_SCH, t_SCL			t_SCK/2		ns
SSx Active to First Shift Edge	t_SSE			10		ns
MOSI Input to SCK Sample Edge Rise/Fall Setup	t_SIS			3		ns
MOSI Input from SCK Sample Edge Transition Hold	t_SIH			3		ns
MISO Output Valid After SCLK Shift Edge Transition	t_SOV			10		ns
SCK Inactive to SSx Inactive	t_SSD			10		ns
SSx Inactive Time	t_SSH			1/f_SCK		ns
MISO Hold Time After SSx Deassertion	t_SLH			10		ns

Electrical Characteristics—I²S
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER	SYMBOL	CONDITIONS	MIN	TYP	MAX	UNITS
TARGET
Bit Clock Frequency	f_BCLKS				25	MHz
Bit Clock Period	t_BCLKS		1/f_BCLKS			μs
BCLK High Time	t_WBCLKHS			$0.5 \times \frac{1}{f_{BCLKS}}$		μs
BCLK Low Time	t_WBCLKLS			$0.5 \times \frac{1}{f_{BCLKS}}$		μs
Setup Time for LRCLK	t_{LRCLK_BLCKS}			20		ns
Delay Time, BCLK to SD (Output) Valid	t_{BCLK_SDOS}			20		ns
Setup Time for SD (Input)	t_{SU_SDIS}			10		ns
Hold Time SD (Input)	t_{HD_SDIS}			10		ns
CONTROLLER
Bit Clock Frequency	f_BCLKM	Source only from I2S_EXTCLK (P0.14 Alternate Function 2)			80	MHz
Bit Clock Period	t_BCLKM		1/f_BCLKM			μs
BCLK High Time	t_WBCLKHM			$0.5 \times \frac{1}{f_{BCLKM}}$		μs
BCLK Low Time	t_WBCLKLM			$0.5 \times \frac{1}{f_{BCLKM}}$		μs
Delay Time BCLK to LRCLK Valid	t_{BLCK_LRCLKM}			20		ns
Delay Time, BCLK to SD (Output) Valid	t_{BCLK_SDOM}			20		ns
Setup Time for SD (Input)	t_{SU_SDIM}			10		ns
Hold Time SD (Input)	t_{HD_SDIM}			10		ns

Electrical Characteristics—PCIF
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER	SYMBOL	MIN	TYP	MAX	UNITS
PCIF
PCIF Operating Frequency	f_CLK			10	MHz
PCIF Clock Period	t_CLK		1/f_CLK		ns
PCIF_PCLK Output Pulse-Width High/Low	t_WCH, t_WCL	t_CLK/2			ns
PCIF_VSYNC, PCIF_HSYNC Setup Time	t_SSU		5		ns
PCIF_VSYNC, PCIF_HSYNC Hold Time	t_SHLD		5		ns
PCIF_D0-PCIF_D11 Setup TIme	t_DSU		5		ns
PCIF_D0-PCIF_D11 Hold Time	t_DHLD		5		ns

Electrical Characteristics—1-Wire Controller
(Timing specifications are guaranteed by design and not production tested.)
PARAMETER	SYMBOL	CONDITIONS	TYP	UNITS
Write 0 Low Time	t_W0L	Standard	60	μs
Write 0 Low Time	t_W0L	Overdrive	8	μs
Write 1 Low Time	t_W1L	Standard	6	μs
		Standard, Long Line mode	8
		Overdrive	1
Presence Detect Sample	t_MSP	Standard	70	μs
		Standard, Long Line mode	85
		Overdrive	9
Read Data Value	t_MSR	Standard	15	μs
		Standard, Long Line mode	24
		Overdrive	3
Recovery Time	t_REC0	Standard	10	μs
		Standard, Long Line mode	20
		Overdrive	4
Reset Time High	t_RSTH	Standard	480	μs
Reset Time High	t_RSTH	Overdrive	58	μs
Reset Time Low	t_RSTL	Standard	600	μs
Reset Time Low	t_RSTL	Overdrive	70	μs
Time Slot	t_SLOT	Standard	70	μs
Time Slot	t_SLOT	Overdrive	12	μs

Figure 1. I²C Timing Diagram
Figure 2. SD/SDIO/SDHC/MMC Timing Diagram
Figure 3. SPI Controller Mode Timing Diagram
Figure 4. SPI Target Mode Timing Diagram
Figure 5. I²S Target ModeTiming Diagram
Figure 6. I²S Controller Timing Diagram
Figure 7. Parallel Camera Interface Timing Diagram
Figure 8. 1-Wire Controller Data Timing Diagram