| Package Code | X8188+3C |
| Outline Number | 21-0735 |
| Land Pattern Number | 90-0460 |
| Thermal Resistance, Four-Layer Board | |
| Junction to Ambient (θJA) | 33.55°C/W |
| Junction to Case (θJC) | 6.73°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opMAX78000EXG%2B
Battery Power Supply for the SIMO Switch-Mode Power Supply (SMPS). Bypass device pin C9 with 2 x 47μF capacitors placed as close as possible to the device pin C9 and VSSPWR pins for applications using a coin cell as the battery. See Bypass Capacitors for more information. If power to the device is cycled, the voltage applied to this device pin must reach VREGI_POR.1.8V Analog Power SupplyDigital Core Supply Voltage ADigital Core Supply Voltage BBoosted Supply Voltage for the Gate Drive of High-Side Switches. Bypass VBST to LXB with a 3.3nF capacitor.Buck Converter A Voltage Output. Bypass VREGO_A with a 22μF capacitor to VSS placed as close as possible to the VDDA device pin.Buck Converter B Voltage Output. Bypass VREGO_B with a 22μF capacitor to VSS placed as close as possible to the closest VCOREB device pin.Buck Converter C Voltage Output. Bypass VREGO_C with a 22μF capacitor to VSS placed as close as possible to the closest VCOREA device pin.GPIO Supply Voltage. Bypass this pin to VSS with a 1.0μF capacitor placed as close as possible to the package.GPIO Supply Voltage, High. VDDIOH ≥ VDDIO. Bypass this pin to VSS with a 1.0μF capacitor placed as close as possible to the package.Digital GroundAnalog GroundGround for the SIMO Switch-Mode Power Supply (SMPS). This device pin is the return path for the VREGI device pins C6 and C9.Switching Inductor Input A. Connect a 2.2μH inductor between LXA and LXB.Switching Inductor Input B. Connect a 2.2μH inductor between LXA and LXB.Active-Low, External System Reset Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR reset (resetting all logic on all supplies except for RTC circuitry) and begins execution.
This pin has an internal pullup to the VDDIOH supply.32kHz Crystal Oscillator Output32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Optionally, this pin can be configured as the input for an external CMOS-level clock source.UART0 Receive Port Map AUART0 Transmit Port Map ATimer 0 I/O 32 Bits or Lower 16 Bits Port Map A; UART0 Clear to Send Port Map BExternal Clock for Use as SYS_OSC/Timer 0 I/O Upper 16 Bits Port Map A; UART0 Request to Send Port Map BSPI0 Slave Select 0; Timer 0 Inverted Output Port Map BSP0 Master-Out Slave-In Serial Data 0; Timer 0 Inverted Output Upper 16 Bits Port Map BSPI0 Master-In Slave-Out Serial Data 1; 1-Wire Master Data I/OSPI0 Clock; 1-Wire Master Pullup Enable OutputSPI0 Data 2 I/O; Timer 0 I/O 32 Bits or Lower 16 Bits Port Map BSPI0 Data 3 I/O; Timer 0 I/O Upper 16 Bits Port Map BI2C0 Clock; SPI0 Slave Select 2I2C0 Serial Data; SPI0 Slave Select 1UART1 Receive Port Map A; Timer 1 Inverted Output Port Map BUART1 Transmit Port Map A; Timer 1 Inverted Output Upper 16 Bits Port Map BTimer 1 I/O 32 Bits or Lower 16 Bits Port Map A; I2S External Clock InputTimer 1 I/O Upper 16 Bits Port Map A; Parallel Camera Interface Vertical SyncI2C1 Clock; Pulse Train 2I2C1 Serial Data; Pulse Train 3Pule Train 0; 1-Wire Master Data I/OPulse Train 1; 1-Wire Master Pullup Enable OutputSPI1 Slave Select 0; Parallel Camera Interface Data 0SPI1_Master Out Slave In Serial Data 0; Parallel Camera Interface Data 1SPI1 Master In Slave Out Serial Data 1; Parallel Camera Interface Data 2SPI1 Clock; Parallel Camera Interface Data 3SPI1 Data 2; Parallel Camera Interface Data 4SPI1 Data 3; Parallel Camera Interface Data 5Timer 2 I/O 32 Bits or Lower 16 Bits Port Map A; Parallel Camera Interface Data 6Timer 2 I/O Upper 16 Bits Port Map A; Parallel Camera Interface Data 7Serial Wire Debug Data I/OSerial Wire Debug ClockI2C2 Clock; Parallel Camera Interface Data 8I2C2 Serial Data; Parallel Camera Interface Data 9UART2 Receive Port Map A; 32-bit RISC-V Test Port ClockUART2 Transmit Port Map A; 32-bit RISC-V Test Port SelectI2S Bit Clock; 32-bit RISC-V Test Port Data InputI2S Left/Right Clock; 32-bit RISC-V Test Port Data OutputI2S Serial Data Input; Timer 3 I/O 32 Bits or Lower 16 Bits Port Map BI2S Serial Data Output; Timer 3 I/O Upper 16 Bits Port Map BTimer 3 I/O 32 Bits or Lower 16 Bits Port Map A; Parallel Camera Interface Data 10Timer 3 I/O Upper 16 Bits Port Map A; Parallel Camera Interface Data 11Parallel Camera Interface Horizontal Sync; CM4 RX Event InputParallel Camera Interface Pixel Clock; CM4 TX Event OutputAnalog to Digital Converter Input 0/Comparator 0 Negative InputAnalog to Digital Converter Input 1/Comparator 0 Positive InputAnalog to Digital Converter Input 2/Comparator 1 Negative InputAnalog to Digital Converter Input 3/Comparator 1 Positive InputAnalog to Digital Converter Input 4/Comparator 2 Negative Input; Low-Power Timer 0 I/O Port Map BAnalog to Digital Converter Input 5/Comparator 2 Positive Input; Low-Power Timer 1 I/O Port Map BLow-Power Timer 0 External Clock Input/Analog to Digital Converter Input 6/Comparator 3 Negative Input; Low-Power UART 0 Receive Port Map BLow-Power Timer 1 External Clock Input/Analog to Digital Converter Input 7/Comparator 3 Positive Input; Low-Power UART Transmit Port Map BPower-Down Output; Wakeup Input. This device pin can only be powered by VDDIOH.Square-Wave Output; Wakeup Input. This device pin can only be powered by VDDIOH.