Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics

(Limits are 100% tested at TA = +25°C and TA = +105°C. TYP specifications are provided for TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested. GPIO are only tested at TA = +105°C.)

POWER SUPPLIES
Core Input Supply Voltage A VCOREA Falling VCOREA VRST 1.1 1.21 V
Rising 0.9 1.1 1.21
Core Input Supply Voltage B VCOREB Falling VCOREB VRST 1.1 1.21 V
Rising 0.9 1.1 1.21
Input Supply Voltage, Battery VREGI Falling VREGI VRST 3.0 3.6 V
Rising 2.45 3.0 3.6
Input Supply Voltage, Analog VDDA 1.71 1.8 1.89 V
Input Supply Voltage, GPIO VDDIO 1.71 1.8 1.89 V
Input Supply Voltage, GPIO (High) VDDIOH 1.71 3.0 3.6 V
Power-Fail Reset Voltage VRST Monitors VCOREA 0.76 V
Monitors VCOREB 0.72 0.77
Monitors VDDA 1.58 1.64 1.69
Monitors VDDIO 1.58 1.64 1.69
Monitors VDDIOH 1.58 1.64 1.69
Monitors VREGI 1.91 1.98 2.08
Power-On Reset Voltage VPOR Monitors VCOREA 0.63 V
Monitors VDDA 1.25
VREGI Current, ACTIVE Mode IREGI_DACT Dynamic, IPO enabled, fSYS_CLK(MAX) = 100MHz, total current into VREGI pin, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 in Active mode executing CoreMark®, RV32 in ACTIVE mode executing While(1), ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA 41.9 μA/MHz
Dynamic, IPO enabled, fSYS_CLK(MAX) = 100MHz, total current into VREGI pin, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 and RV32 in ACTIVE mode executing While(1), ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA   38
Dynamic, IPO enabled, fSYS_CLK(MAX) = 100MHz, total current into VREGI pin, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 in ACTIVE mode executing While(1), RV32 in SLEEP mode, ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA  22.2
Dynamic, total current into VREGI pin, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 in SLEEP mode, RV32 in ACTIVE mode running from ISO, ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA  22.9
IREGI_FACT Fixed, IPO enabled, ISO enabled, total current into VREGI, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 in ACTIVE mode 0MHz, RV32 in ACTIVE mode 0MHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA   744 μA
VREGI Current, SLEEP Mode IREGI_DSLP Dynamic, IPO enabled, fSYS_CLK(MAX) = 100MHz, ISO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 in SLEEP mode, RV32 in SLEEP mode, ECC disabled, all CNN quadrants disabled, all CNN memory disabled, standard DMA with 2 channels active; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA 22.5 μA/MHz
IREGI_FSLP Fixed, IPO enabled, ISO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 in SLEEP mode, RV32 in SLEEP mode, ECC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA 1.5 mA
VREGI Current, LOW POWER Mode IREGI_DLP Dynamic, ISO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 powered off, RV32 in ACTIVE mode, fSYS_CLK(MAX) = 60MHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA 18.3 μA/MHz
IREGI_FLP Fixed, ISO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, CM4 powered off, RV32 in ACTIVE mode 0MHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA 0.64 mA
VREGI Current, MICRO POWER Mode IREGI_DMP Dynamic, ERTCO enabled, IBRO enabled, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, LPUART active, fLPUART = 32.768kHz, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA 230 μA
VREGI Current, STANDBY Mode IREGI_STBY Fixed, total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA 11.3 μA
VREGI Current, BACKUP Mode IREGI_BK Total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V, RTC disabled, all CNN quadrants disabled, all CNN memory disabled; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA All SRAM retained 11.1 μA
No SRAM retention 9
SRAM0 retained 9.6
SRAM0 and SRAM1 retained 10.1
SRAM0, SRAM1, and SRAM2 retained 10.6
VREGI Current, POWER DOWN Mode IREGI_PDM Total current into VREGI pins, VREGI = 3.0V, VCOREA = VCOREB = 1.1V; inputs tied to VSS, VDDIO, or VDDIOH; outputs source/sink 0mA 0.17 μA
VREGO_X Output Current VREGO_A_IOUT VREGO_A output current 5 50 mA
VREGO_B_IOUT VREGO_B output current 5 50
VREGO_C_IOUT VREGO_C output current 10 100
VREGO_X Output Current Combined VREGO_X_IOUT_TOT All three VREGO_X outputs combined 20 100 mA
VREGO_X Output Voltage Range VREGO_X_RANGE VREGI ≥ VREGO_X + 200mV 0.5 1.0 1.85 V
VREGO_X Efficiency VREGO_X_EFF VREGI = 2.7V, VREGO_X = 1.1 V, load = 30mA 90 %
SLEEP Mode Resume Time tSLP_ON Time from power mode exit to execution of first user instruction 0.67 μs
LOW-POWER Mode Resume Time tLP_ON Time from power mode exit to execution of first user instruction 9.5 μs
MICROPOWER Mode Resume Time tMP_ON Time from power mode exit to execution of first user instruction 31 us
STANDBY Mode Resume Time tSTBY_ON Time from power mode exit to execution of first user instruction 35 μs
BACKUP Mode Resume Time tBKU_ON Time from power mode exit to execution of first user instruction 0.14 ms
POWER-DOWN Mode Resume Time tPDM_ON Time from power mode exit to execution of first user instruction. Includes bootloader execution time. 5 ms
CLOCKS
System Clock Frequency fSYS_CLK 0.0625 100,000 kHz
System Clock Period tSYS_CLK 1/fSYS_CLK ns
Internal Primary Oscillator (IPO) fIPO 100 MHz
Internal Secondary Oscillator (ISO) fISO 60 MHz
Internal Baud Rate Oscillator (IBRO) fIBRO 7.3728 MHz
Internal Nano-Ring Oscillator (INRO) fINRO 8kHz selected 8 kHz
16kHz selected 16
30kHz selected 32
External RTC Oscillator (ERTCO) fERTCO 32kHz watch crystal, CL = 6pF, ESR < 90kΩ, C0 ≤ 2pF 32.768 kHz
RTC Operating Current IRTC All power modes, RTC enabled 0.3 μA
RTC Power-Up Time tRTC_ ON 250 ms
External I2S Clock Input Frequency fEXT_I2S_CLK I2S_CLKEXT selected 25 MHz
External System Clock Input Frequency fEXT_CLK EXT_CLK selected 80 MHz
External Low Power Timer 1 Clock Input Frequency fEXT_LPTMR1_CLK LPTMR1_CLK selected 8 MHz
External Low Power Timer 2 Clock Input Frequency fEXT_LPTMR2_CLK LPTMR2_CLK selected 8 MHz
CONVOLUTIONAL NEURAL NETWORK
CNN Active Energy ΕJ_CNN Max power network, random data, and random mask configuration x16 Quadrant 0, 1, 2, and 3 enabled 4.02 pJ/MAC
VCOREA CNN Active Current ICOREA_CNN_MNISTA MNIST Standard dataset, optimized network x16 Quadrant 0 enabled; x16 Quadrant 1, 2, and 3 powered down and isolated 10.1 mA
ICOREA_CNN_MNISTB x16 Quadrant 0, 1, 2, and 3 enabled 29
ICOREA_CNNMPRA Max power network, random data, and random mask configuration x16 Quadrant 0 enabled; x16 Quadrant 1, 2, and 3 powered down and isolated 31.7
ICOREA_CNNMPRB x16 Quadrant 0, 1, 2, and 3 enabled. External power supply must be used for VCOREA since the on-board SIMO will not supply above 100mA. 118
ICOREA_CNNMPA Max power network, data, mask configuration x16 Quadrant 0 enabled; x16 Quadrant 1, 2, and 3 powered down and isolated 38.5
ICOREA_CNNMPB x16 Quadrant 0, 1, 2, and 3 enabled. External power supply must be used for VCOREA since the on-board SIMO will not supply above 100mA. 146
VREGI Mask Memory Retention Current IREGI_CNNMR VCOREB = 1.0V x16 Quadrant 0 only; x16 Quadrant 1, 2, and 3 powered down and isolated 6.625 μA
x16 Quadrant 0, 1, 2, and 3 enabled 26.5
VREGI CNN Inactive Current IREGI_CNNIA CNN enabled/inactive, clocks disabled x16 Quadrant 0 enabled; x16 Quadrant 1, 2, and 3 powered down and isolated 264 μA
x16 Quadrant 0, 1, 2, and 3 enabled 790.4
GENERAL-PURPOSE I/O
Input Low Voltage for All GPIO Except P3.0 and P3.1 VIL_VDDIO P3.0 and P3.1 can only use VDDIOH as I/O supply and cannot use VDDIO as I/O supply VDDIO selected as I/O supply 0.3 × VDDIO V
Input Low Voltage for All GPIO VIL_VDDIOH VDDIOH selected as I/O supply 0.3 × VDDIOH V
Input Low Voltage for RSTN VIL_RSTN 0.5 x VDDIOH V
Input High Voltage for All GPIO Except P3.0 and P3.1 VIH_VDDIO P3.0 and P3.1 can only use VDDIOH as I/O supply and cannot use VDDIO as I/O supply VDDIO selected as I/O supply 0.7 × VDDIO V
Input High Voltage for All GPIO VIH_VDDIOH VDDIOH selected as I/O supply 0.7 × VDDIOH V
Input High Voltage for RSTN VIH_RSTN 0.5 x VDDIOH V
Output Low Voltage for All GPIO Except P3.0 and P3.1 VOL_VDDIO P3.0 and P3.1 can only use VDDIOH as I/O supply and cannot use VDDIO as I/O supply VDDIO selected as I/O supply, VDDIO = 1.71V, GPIOn_DS_SEL[1:0] = 00, IOL = 1mA 0.2 0.4 V
VDDIO selected as I/O supply, VDDIO = 1.71V, GPIOn_DS_SEL[1:0] = 01, IOL = 2mA 0.2 0.4
VDDIO selected as I/O supply, VDDIO = 1.71V, GPIOn_DS_SEL[1:0] = 10, IOL = 4mA 0.2 0.4
VDDIO selected as I/O supply, VDDIO = 1.71V, GPIOn_DS_SEL[1:0] = 11, IOL = 8mA 0.2 0.4
Output Low Voltage for All GPIO VOL_VDDIOH VDDIOH selected as I/O supply, VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] = 00, IOL = 1mA 0.2 0.4 V
VDDIOH selected as I/O supply, VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] = 01, IOL = 2mA 0.2 0.4
VDDIOH selected as I/O supply, VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] = 10, IOL = 4mA 0.2 0.4
VDDIOH selected as I/O supply, VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] = 11, IOL = 8mA 0.2 0.4
Combined IOL, All GPIO IOL_TOTAL 48 mA
Output High Voltage for All GPIO Except P3.0 and P3.1 VOH_VDDIO P3.0 and P3.1 can only use VDDIOH as I/O supply and cannot use VDDIO as I/O supply VDDIO selected as I/O supply, VDDIO = 1.71V, GPIOn_DS_SEL[1:0] = 00, IOL = -1mA VDDIO - 0.4 V
VDDIO selected as I/O supply, VDDIO = 1.71V, GPIOn_DS_SEL[1:0] = 01, IOL = -2mA VDDIO - 0.4
VDDIO selected as I/O supply, VDDIO = 1.71V, GPIOn_DS_SEL[1:0] = 10, IOL = -4mA VDDIO - 0.4
VDDIO selected as I/O supply, VDDIO = 1.71V, GPIOn_DS_SEL[1:0] = 11, IOL = -8mA VDDIO - 0.4
Output High Voltage for All GPIO Except P3.0 and P3.1 VOH_VDDIOH VDDIOH selected as I/O supply, VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] = 00, IOL = -1mA VDDIOH - 0.4 V
VDDIOH selected as I/O supply, VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] = 01, IOL = -2mA VDDIOH - 0.4
VDDIOH selected as I/O supply, VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] = 10, IOL = -4mA VDDIOH - 0.4
VDDIOH selected as I/O supply, VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] = 11, IOL = -8mA VDDIOH - 0.4
Output High Voltage for P3.0 and P3.1 VOH_VDDIOH VDDIOH = 1.71V, GPIOn_DS_SEL[1:0] fixed at 00, IOL = -1mA VDDIOH - 0.4 V
Combined IOH, All GPIO IOH_TOTAL -48 mA
Input Hysteresis (Schmitt) VIHYS 300 mV
Input Leakage Current Low IIL VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH selected as I/O supply, VIN = 0V, internal pullup disabled -100 +100 nA
Input Leakage Current High IIH VDDIO = 1.89V, VDDIOH = 3.6V, VDDIOH selected as I/O supply, VIN = 3.6V, internal pulldown disabled -800 +800 nA
IOFF VDDIO = 0V, VDDIOH = 0V, VDDIO selected as I/O supply, VIN < 1.89V -1 +1 μA
IIH3V VDDIO = VDDIOH = 1.71V, VDDIO selected as I/O supply, VIN = 3.6V -2 +2
Input Pullup Resistor RSTN RPU_R Pullup to VDDIOH 25 kΩ
Input Pullup/Pulldown Resistor for All GPIO RPU1 Normal resistance, P1M = 0 25 kΩ
RPU2 Highest resistance, P1M = 1 1 MΩ
ADC (SIGMA-DELTA)
Resolution 10 Bits
ADC Clock Rate fACLK 0.1 8 MHz
ADC Clock Period tACLK 1/fACLK μs
Input Voltage Range VAIN AIN[7:0], ADC_DIVSEL = [00], ADC_CH_SEL = [7:0] REF_SEL = 0, INPUT_SCALE = 0 VSSA  + 0.05 VBG V
AIN[7:0], ADC_DIVSEL = [01], ADC_CH_SEL = [7:0] REF_SCALE = 0, INPUT_SCALE = 0 VSSA + 0.05 2 x VBG
AIN[7:0], ADC_DIVSEL = [10], ADC_CH_SEL = [7:0] REF_SCALE = 0, INPUT_SCALE = 0, VDDIOH selected as the I/O supply VSSA + 0.05 VDDIOH
AIN[7:0], ADC_DIVSEL = [11], ADC_CH_SEL = [7:0] REF_SEL = 0, INPUT_SCALE = 0, VDDIOH selected as the I/O supply VSSA + 0.05 VDDIOH
Input Impedance RAIN 30 kΩ
Analog Input Capacitance CAIN Fixed capacitance to VSSA 1 pF
Dynamically switched capacitance 250 fF
Integral Nonlinearity INL Measured at +25°C ±2 LSb
Differential Nonlinearity DNL Measured at +25°C ±1 LSb
Offset Error VOS ±1 LSb
ADC Active Current IADC ADC active, reference buffer enabled, input buffer disabled 102 µA
ADC Setup Time tADC_SU Any power-up of ADC clock or ADC bias to CpuAdcStart 10 µs
ADC Output Latency tADC 1067 tACLK
ADC Sample Rate fADC 7.8 ksps
ADC Input Leakage IADC_LEAK ADC inactive or channel not selected 10 nA
Full-Scale Voltage VFS ADC code = 0x3FF 1.2 V
Bandgap Temperature Coefficient VTEMPCO Box method 30 ppm
COMPARATORS
Input Offset Voltage VOFFSET ±1 mV
Input Hysteresis VHYST AINCOMPHYST[1:0] = 00 ±23 mV
AINCOMPHYST[1:0] = 01 ±50
AINCOMPHYST[1:0] = 10 ±2
AINCOMPHYST[1:0] = 11 ±7
Input Voltage Range VIN_CMP Common-mode range 0.6 1.35 V
FLASH MEMORY
Flash Erase Time tM_ERASE Mass erase 20 ms
tP_ERASE Page erase 20
Flash Programming Time per Word tPROG 32-bit programming mode, fFLC_CLK = 1MHz 42 μs
Flash Endurance 10 kcycles
Data Retention tRET TA = +105°C 10 years
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—SPI

(Timing specifications are guaranteed by design and not production tested.)

MASTER MODE
SPI Master Operating Frequency for SPI0 fMCK0 fSYS_CLK = 100MHz, fMCK0(MAX) = fSYS_CLK/2 50 MHz
SPI Master Operating Frequency for SPI1 fMCK1 fSYS_CLK = 100MHz, fMCK1(MAX) = fSYS_CLK/4 25 MHz
SPI Master SCK Period tMCKX 1/fMCKX ns
SCK Output Pulse-Width High/Low tMCH, tMCL tMCKX/2 ns
MOSI Output Hold Time After SCK Sample Edge tMOH tMCX/2 ns
MOSI Output Valid to Sample Edge tMOV tMCKX/2 ns
MOSI Output Hold Time After SCK Low Idle tMLH tMCKX/2 ns
MISO Input Valid to SCK Sample Edge Setup tMIS 5 ns
MISO Input to SCK Sample Edge Hold tMIH tMCKX/2 ns
SLAVE MODE
SPI Slave Operating Frequency fSCK 50 MHz
SPI Slave SCK Period tSCK 1/fSCK ns
SCK Input Pulse-Width High/Low tSCH, tSCL tSCK/2
SSx Active to First Shift Edge tSSE 10 ns
MOSI Input to SCK Sample Edge Rise/Fall Setup tSIS 5 ns
MOSI Input from SCK Sample Edge Transition Hold tSIH 1 ns
MISO Output Valid After SCLK Shift Edge Transition tSOV 5 ns
SCK Inactive to SSx Inactive tSSD 10 ns
SSx Inactive Time tSSH 1/fSCK μs
MISO Hold Time After SSx Deassertion tSLH 10 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—I2C

(Timing specifications are guaranteed by design and not production tested.)

STANDARD MODE
Output Fall Time tOF Standard mode, from VIH(MIN) to VIL(MAX) 150 ns
SCL Clock Frequency fSCL 0 100 kHz
Low Period SCL Clock tLOW 4.7 μs
High Time SCL Clock tHIGH 4.0 μs
Setup Time for Repeated Start Condition tSU;STA 4.7 μs
Hold Time for Repeated Start Condition tHD;STA 4.0 μs
Data Setup Time tSU;DAT 300 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and SCL tR 800 ns
Fall Time for SDA and SCL tF 200 ns
Setup Time for a Stop Condition tSU;STO 4.0 μs
Bus Free Time Between a Stop and Start Condition tBUS 4.7 μs
Data Valid Time tVD;DAT 3.45 μs
Data Valid Acknowledge Time tVD;ACK 3.45 μs
FAST MODE
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 150 ns
Pulse Width Suppressed by Input Filter tSP 75 ns
SCL Clock Frequency fSCL 0 400 kHz
Low Period SCL Clock tLOW 1.3 μs
High Time SCL Clock tHIGH 0.6 μs
Setup Time for Repeated Start Condition tSU;STA 0.6 μs
Hold Time for Repeated Start Condition tHD;STA 0.6 μs
Data Setup Time tSU;DAT 125 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and SCL tR 30 ns
Fall Time for SDA and SCL tF 30 ns
Setup Time for a Stop Condition tSU;STO 0.6 μs
Bus Free Time Between a Stop and Start Condition tBUS 1.3 μs
Data Valid Time tVD;DAT 0.9 μs
Data Valid Acknowledge Time tVD;ACK 0.9 μs
FAST MODE PLUS
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 80 ns
Pulse Width Suppressed by Input Filter tSP 75 ns
SCL Clock Frequency fSCL 0 1000 kHz
Low Period SCL Clock tLOW 0.5 μs
High Time SCL clock tHIGH 0.26 μs
Setup Time for Repeated Start Condition tSU;STA 0.26 μs
Hold Time for Repeated Start Condition tHD;STA 0.26 μs
Data Setup Time tSU;DAT 50 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and SCL tR 50 ns
Fall Time for SDA and SCL tF 30 ns
Setup Time for a Stop Condition tSU;STO 0.26 μs
Bus Free Time Between a Stop and Start Condition tBUS 0.5
  		μs
Data Valid Time tVD;DAT 0.45 μs
Data Valid Acknowledge Time tVD;ACK 0.45 μs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—I2S

(Timing specifications are guaranteed by design and not production tested.)

Bit Clock Frequency fBCLKS 25 MHz
Bit Clock Period tBCLKS 1/fBCLKS ns
BCLK High Time tWBCLKHS 0.5 1/fBCLKS
BCLK Low Time tWBCLKLS 0.5 1/fBCLKS
LRCLK Setup Time tLRCLK_BCLKS 25 ns
Delay Time, BCLK to SD (Output) Valid tBCLK_SDOS 12 ns
Setup Time for SD (Input) tSU_SDIS 6 ns
Hold Time SD (Input) tHD_SDIS 3 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—PCIF

(Timing specifications are guaranteed by design and not production tested.)

PCIF
PCIF Operating Frequency fCLK 10 MHz
PCIF Clock Period tCLK 1/fCLK ns
PCIF_PCLK Output Pulse-Width High/Low tWCH, tWCL tCLK/2 ns
PCIF_VSYNC, PCIF_HSYNC Setup Time tSSU 5 ns
PCIF_VSYNC, PCIF_HSYNC Hold Time tSHLD 5 ns
PCIF_D0-PCIF_D11 Setup TIme tDSU 5 ns
PCIF_D0_PCIF_D11 Hold Time tDHLD 5 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—1-Wire Master

(Timing specifications are guaranteed by design and not production tested.)

Write 0 Low Time tW0L Standard 60 μs
Overdrive 8
Write 1 Low Time tW1L Standard 6 μs
Standard, Long Line mode 8
Overdrive 1
Presence Detect Sample tMSP Standard 70 μs
Standard, Long Line mode 85
Overdrive 9
Read Data Value tMSR Standard 15 μs
Standard, Long Line mode 24
Overdrive 3
Recovery Time tREC0 Standard 10 μs
Standard, Long Line mode 20
Overdrive 4
Reset Time High tRSTH Standard 480 μs
Overdrive 58
Reset Time Low tRSTL Standard 600 μs
Overdrive 70
Time Slot tSLOT Standard 70 μs
Overdrive 12
Figure 1. SPI Master Mode Timing Diagram
Figure 2. SPI Slave Mode Timing Diagram
 
Figure 3. I2C Timing Diagram
   
Figure 4. I2S Timing Diagram
Figure 5. Parallel Camera Interface Timing Diagram
 
Figure 6. 1-Wire Master Data Timing Diagram