Detailed Description

The MAX78000 is the first of a new breed of low-power microcontrollers built to thrive in the rapidly evolving AI at the edge market. These products include Maxim's proven ultra-low power MCU IP along with deep neural network AI acceleration.

The MAX78000 is an advanced system-on-chip featuring an Arm Cortex-M4 with FPU CPU for efficient computation of complex functions and algorithms with integrated power management. It also includes a 442KB-weight CNN accelerator. The devices offer large on-chip memory with 512KB flash and up to 128KB SRAM. Multiple high-speed and low-power communication interfaces are supported including high-speed SPI, high-speed I²C serial interface, and LPUART. Additional low-power peripherals include flexible LPTIMER and analog comparators. A PCIF is included for capturing images from an image sensor for processing by the CNN. An I²S interface is included for interfacing to an audio codec for capturing audio samples also for processing by the CNN.

The Arm Cortex-M4 with FPU processor CM4 is ideal for the artificial intelligence system control. The architecture combines high-efficiency signal processing functionality with low power, low cost, and ease of use.

The Arm Cortex-M4 with FPU DSP supports single instruction, multiple data (SIMD) path DSP extensions, providing:

• Four parallel 8-bit add/sub
• Floating point single precision
• Two parallel 16-bit add/sub
• Two parallel MACs
• 32- or 64-bit accumulate
• Signed, unsigned, data with or without saturation

The addition of a 32-bit RISC-V coprocessor RV32 provides the system with ultra-low power consumption signal processing.

The CNN accelerator consists of 64 parallel processors with 512KB of SRAM-based storage. Each processor includes a pooling unit and a convolutional engine with dedicated weight memory. Four processors share one data memory. These are further organized into groups of 16 processors that share common controls. A group of 16 processors operates as a slave to another group or independently. Data is read from SRAM associated with each processor and written to any data memory located within the accelerator. Any given processor has visibility of its dedicated weight memory and to the data memory instance it shares with the three others.

The features of the CNN accelerator include:

• 512KB SRAM data storage
  • Configured as 8Kx8-bit integers x64 channels or 32Kx8-bit integers x4 channels for input layers
  • Hardware load and unload assist
• 64 parallel physical channel processors
  • Organized as 4x16 processors
  • 8-bit integer data path with option for 32-bit integers on the output layer
  • Per-channel processor enable/disable
  • Expandable to 1024 parallel logical channel processors
• 1x1 or 3x3 2D kernel sizes
• Configurable 1D kernel size to 1x9
• Full resolution sum-of-product arithmetic for 1024 8-bit integer channels
• Operating frequency up to 50MHz
• Nominal 1 output channel per clock, maximum 4 output channels per clock (passthru)
• Configurable input layer image size
  • 32K pixels, 16 channels, non-streaming
  • 8K pixels, 4 channels, non-streaming
  • 1024 x 1024 pixels, 4 channels, streaming
• Hidden layers
  • Up to 8K 8-bit integer data per channel, x64 channels, non-streaming
  • 8K bytes can be split equally across 1 to 16 logical channels, non-streaming
  • 1M 8-bit integer data per channel, x64 channels, streaming
  • 1M bytes can be split equally across eight layers, streaming
• Optional interrupt on CNN completion
• User-accessible BIST on all SRAM storage
• User-accessible zeroization of all SRAM storage
• Single-step operation with full data SRAM access for CNN operation debug
• Flexible power management
  • Independent x16 processor supply enables
  • Independent x16 processor mask retention enables
  • Independent x16 data path clock enables
  • Active Arm peripheral bus clock gating with per x16 processor override
  • CNN clock frequency scaling (divide by 2, 4, 8, 16)
  • Chip-level voltage control for performance power optimization
• Configurable weight storage
  • SRAM-based weight storage with selectable data retention
  • Configurable from 442K 8-bit integer weights to 3.456M 1-bit logical weights
    • Organized as 768X9X64 8-bit integer weights to 768x72x64 1-bit logical weights
    • Can be configured on a per-layer basis
  • Programmable per x16 processor weight RAM start address, start pointer, and mask count
  • Optional weight load hardware assist for packed weight storage
• 32 independently configurable layer groups
  • Each group can contain element-wise, and/or pooling, and/or convolution operations for a minimum of 32 and a maximum of 96 layers
  • Processor and mask enables (16 channels)
  • Input data format
  • Per-layer data streaming
    • Stream start - relative to prior stream
    • Dual-stream processing delay counters - 1 column, 1 row delta counter
    • Data SRAM circular buffer size
  • Input data size (row, column)
  • Row and column padding 0 to 4 bytes
  • Number of input channels 1 to 1024
  • Kernel bit width size (1, 2, 4, 8)
  • Kernel SRAM start pointer and count
  • Inflight input image pooling
    • Pool mode - none, maximum or average
    • Pool size - 1x1 to 16x16
  • Stride - 1 row, 1 column to 4 rows, 4 columns
  • Data SRAM read pointer base address
  • Data SRAM write pointer configuration
    • Base address
    • Independent offsets for output channel storage in SRAM
    • Programmable stride increment offset
  • Bias - 2048 8-bit integers with option for 512 32-bit integers
  • Pre-activation output scaling from 0 to 8 bits
  • Output activation - none, ReLU, absolute value
  • Passthru - 8-bit or 32-bit integers
  • Element-wise operations (add, subtract, xor, or) with optional convolution - up to 16 elements
  • Deconvolution (upscaling)
  • Flattening for MLP processing
  • 1x1 convolution

The eight AIN[7:0] inputs can be configured as four pairs and deployed as four independent comparators with the following features:

• Comparison events can trigger interrupts
• Events can wake the CM4 from SLEEP, LOW POWER, MICRO POWER, STANDBY, or BACKUP operating modes
• Can be active in all power modes

The DVS controller works using the fixed high-speed oscillator and the V_COREA supply  voltage to optimally operate the Arm core at the lowest practical voltage. The ability to adaptively adjust the voltage provides a significant reduction in dynamic power consumption.

The DVS controller provides the following features:

• Controls DVS monitoring and adjustment functions
• Continuous monitoring with programmable monitor sample period
• Controlled transition to a programmable operating point
• Independent high and low operating limits for safe, bounded operation
• Independent high, center, and low operating range delay line delay monitors
• Programmable adjustment rate – when an adjustment is required
• Single clock operation
• Arm peripheral bus interface provides control and status access
• Interrupt capability during error

Multiple clock sources can be selected as the system clock:

• Internal primary oscillator (IPO) at a nominal frequency of 100MHz
• Internal secondary oscillator (ISO) at a nominal frequency of 60MHz
• Configurable internal nano-ring oscillator (INRO) at 8kHz, 16kHz, or 30kHz
• External RTC oscillator at 32.768kHz (ERTCO) (external crystal required)
• Internal baud rate oscillator at 7.3728MHz (IBRO)
• External square-wave clock up to 80MHz

There are multiple external clock inputs:

• LPTMR0 and LPTMR1 can be clocked from unique external sources.
• I²S can be clocked from its own external source.

Most general-purpose I/O (GPIO) pins share both a firmware-controlled I/O function and one or more alternate functions associated with peripheral modules. Pins can be individually enabled for GPIO or peripheral special function use. Configuring a pin as a special function usually supersedes its use as a firmware-controlled I/O. Although this multiplexing between peripheral and GPIO functions is usually static, it can also be done dynamically. The electrical characteristics of a GPIO pin are identical whether the pin is configured as an I/O or special function, except where explicitly noted in the Electrical Characteristics tables.

In GPIO mode, pins are logically divided into ports of 32 pins. Each pin of a port has an interrupt function that can be independently enabled, and configured as a level- or edge-sensitive interrupt. All GPIOs of a given port share the same interrupt vector.

When configured as GPIO, the following features are provided. The features can be independently enabled or disabled on a per-pin basis.

• Configurable as input, output, bidirectional, or high impedance
• Optional internal pullup resistor or internal pulldown resistor when configured as input
• Exit from low-power modes on rising or falling edge
• Selectable standard- or high-drive modes

The MAX78000 provides up to 52 GPIO pins. Caution is needed since Port 3 (P3.0 and P3.1 device pins) are configured in a different manner from the above description.

The 10-bit sigma-delta ADC provides an integrated reference generator and a single-ended input multiplexer. The multiplexer selects an input channel from one of the eight external analog input signals (AIN0–AIN7) or the internal power supply inputs.

The reference for the ADC can be:

• Internal 1.22V bandgap
• V_DDA analog supply

An optional feature allows samples captured by the ADC to be automatically compared against user-programmable high and low limits. Up to four channel limit pairs can be configured in this way. The comparison allows the ADC to trigger an interrupt (and potentially wake the CPU from a power mode) when a captured sample goes outside the preprogrammed limit range. Since this comparison is performed directly by the sample limit monitors, it can be performed even while the CPU is in SLEEP, LOW POWER or MICRO POWER mode. The eight AIN[7:0] inputs can be configured as four pairs and deployed as four independent comparators.

​The ADC measures the following voltages:

• AIN[7:0] up to 3.3V
• V_REGI
• V_DDA
• V_COREA
• V_COREB
• V_DDIOH
• V_DDIO

The power management unit (PMU) provides high-performance operation while minimizing power consumption. It exercises intelligent, precise control of power distribution to the CPUs and peripheral circuitry.

The PMU provides the following features:

• User-configurable system clock
• Automatic enabling and disabling of crystal oscillators based on power mode
• Multiple power domains
• Fast wake-up of powered-down peripherals when activity detected

This mode consumes less power, but wakes faster because the clocks can optionally be enabled.

The device status is as follows:

• CM4 is asleep.
• RV32 is asleep.
• CNN quadrants and memory are configurable.
• Peripherals are on.
• Standard DMA is available for optional use.

This mode is suitable for running the RV32 processor to collect and move data from enabled peripherals.

The device status is as follows:

• The CM4, SRAM0, SRAM1 are in state retention.
• CNN quadrants and memory are configurable and active.
• The RV32 can access the SPI, all UARTS, all timers, I²C, 1-Wire, pulse train engines, I²S, CRC, AES, TRNG, PCIF, and comparators, as well as SRAM2 and SRAM3. SRAM3 can be configured to operate as RV32 instruction cache.
• The transition from LOW POWER mode to ACTIVE mode is faster than the transition from BACKUP mode because system initialization is not required.
• The DMA can access flash.
• IPO can be optionally powered down.
• The following oscillators are enabled:
  • IBRO
  • ERTCO
  • INRO
  • ISO

This mode is used for extremely low power consumption while using a minimal set of peripherals to provide wakeup capability.

The device status is as follows:

• Both CM4 and RV32 are state retained. System state and all SRAM is retained.
• CNN quadrants are powered off.
• CNN memory provides selectable retention.
• The GPIO pins retain their state.
• All non-MICRO POWER peripherals are state retained.
• The following oscillators are powered down:
  • IPO
  • ISO
• The following oscillators are enabled:
  • IBRO
  • ERTCO
  • INRO
• The following MICRO POWER mode peripherals are available to wake up the device:
  • LPUART0, LPUART1
  • WWDT1
  • All four low-power analog comparators

This mode is used to maintain the system operation while keeping time with the RTC.

The device status is as follows:

• Both CM4 and RV32 are state retained. System state and all SRAM are retained.
• CNN quadrants are powered off.
• CNN memory provides selectable retention.
• GPIO pins retain their state.
• All peripherals are state retained.
• The following oscillators are powered down:
  • IPO
  • ISO
  • IBRO
• The following oscillators are enabled:
  • ERTCO
  • INRO

This mode is used to maintain the system RAM. The device status is as follows:

• CM4 and RV32 are powered off.
• SRAM0, SRAM1, SRAM2, and SRAM3 can be configured to be state retained as per Table 1.
• CNN memory provides selectable retention.
• All peripherals are powered off.

The following oscillators are powered down:

• IPO
• ISO
• IBRO

The following oscillators are enabled:

• ERTCO
• INRO

This mode is used during product level distribution and storage. The device status is as follows:

• CM4 and RV32 are powered off.
• All peripherals and SRAM are powered down.
• All oscillators are powered down.
• There is no data retention in this mode, but values in flash memory are preserved.
• Voltage monitors are operational.

The sources of wakeup from the SLEEP, LOW POWER, MICRO POWER, STANDBY, BACKUP, and POWER DOWN operating modes are summarized in Table 2.

An RTC keeps the time of day in absolute seconds. The 32-bit seconds register can count up to approximately 136 years and be translated to calendar format by application software.

The RTC provides a time-of-day alarm that can be programmed to any future value between 1 second and 12 days. When configured for long intervals, the time-of-day alarm can be used as a power-saving timer, allowing the device to remain in an extremely low-power mode, but still awaken periodically to perform assigned tasks. A second independent 32-bit 1/4096 subsecond alarm can be programmed with a tick resolution of 244μs. Both can be configured as recurring alarms. When enabled, either alarm can cause an interrupt or wake the device from most low-power modes.

The time base is generated by a 32.768kHz crystal or an external clock source that must meet the electrical/timing requirements in the Electrical Characteristics table.

The RTC calibration feature provides the ability for user software to compensate for minor variations in the RTC oscillator, crystal, temperature, and board layout. Enabling the SQWOUT alternate function outputs a timing signal derived from the RTC. External hardware can measure the frequency and adjust the RTC frequency in increments of ±127ppm with 1ppm resolution. Under most circumstances, the oscillator does not require any calibration.

General-purpose, 32-bit timers provide timing, capture/compare, or generation of pulse-width modulated (PWM) signals with minimal software interaction.

The timer provides the following features:

• 32-bit up/down autoreload
• Programmable prescaler
• PWM output generation
• Capture, compare, and capture/compare capability
• External pin multiplexed with GPIO for timer input, clock gating, or capture
• Timer output pin
• TMR0–TMR3 can be configured as 2 × 16-bit general-purpose timers
• Timer interrupt

The MAX78000 provides six 32-bit timers (TMR0, TMR1, TMR2, TMR3, LPTMR0, and LPTMR1). LPTMR0 and LPTMR1 are capable of operation in the SLEEP, LOW POWER, and MICRO POWER modes.

I/O functionality is supported for all of the timers. Note that the function of a port can be multiplexed with other functions on the GPIO pins, so it might not be possible to use all of the ports depending on the device configuration. See Table 3 for individual timer features.

Microcontrollers are often used in harsh environments where electrical noise and electromagnetic interference (EMI) are abundant. Without proper safeguards, these hazards can disturb device operation and corrupt program execution. One of the most effective countermeasures is the windowed watchdog timer (WDT), which detects runaway code or system unresponsiveness.

The WDT is a 32-bit, free-running counter with a configurable prescaler. When enabled, the WDT must be periodically reset by the application software. Failure to reset the WDT within the user-configurable timeout period indicates that the application software is not operating correctly and results in a WDT timeout. A WDT timeout can trigger an interrupt, system reset, or both. Either response forces the instruction pointer to a known good location before resuming instruction execution. The windowed timeout period feature provides more detailed monitoring of system operation, requiring the WDT to be reset within a specific window of time. See Table 4 for individual timer features.

The MAX78000 provides two instances of the watchdog timer—WDT0 and LPWDT0.

Multiple, independent pulse train generators can provide either a square-wave or a repeating pattern from 2 to 32 bits in length. Any single pulse train generator or any desired group of pulse train generators can be synchronized at the bit level, allowing for multibit patterns. Each pulse train generator is independently configurable.

The pulse train generators provide the following features:

• Independently enabled
• Safe enable and disable for pulse trains without bit banding
• Multiple pin configurations allow for flexible layout
• Pulse trains can be started/synchronized independently or as a group
• Frequency of each enabled pulse train generator is also set separately, based on a divide down (such as divide by 2, divide by 4, and divide by 8) of the input pulse train module clock
• Input pulse train module clock can be optionally configured to be independent from the system AHB clock
• Multiple repetition options
  • Single shot (nonrepeating pattern of 2 to 32 bits)
  • Pattern repeats user-configurable number of times or indefinitely
  • Termination of one pulse train loop count can restart one or more other pulse trains

The pulse train engine feature is an alternate function associated with a GPIO pin. In most cases, enabling the pulse train engine function supersedes the GPIO function.

The MAX78000 provides up to four instances of the pulse train engine peripheral (PT[3:0]).

The I²C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can operate as a one-to-one, one-to-many, or many-to-many communications medium. These engines support standard-mode, fast-mode, fast-mode plus, and high-speed mode I²C speeds. It provides the following features:

• Master or slave mode operation
  • Supports up to four different slave addresses in slave mode
• Supports standard 7-bit addressing or 10-bit addressing
• RESTART condition
• Interactive receive mode
• Tx FIFO preloading
• Support for clock stretching to allow slower slave devices to operate on higher speed busses
• Multiple transfer rates
  • Standard mode: 100kbps
  • Fast mode: 400kbps
  • Fast mode plus: 1000kbps
  • High-speed mode: 3.4Mbps
• Internal filter to reject noise spikes
• Receiver FIFO depth of 8 bytes
• Transmitter FIFO depth of 8 bytes

The MAX78000 provides three instances of the I²C peripheral—I2C0, I2C1, and I2C2.

The I²S interface is a bidirectional, four-wire serial bus that provides serial communications for codecs and audio amplifiers compliant with the I²S Bus Specification, June 5, 1996. It provides the following features:

• Master and slave mode operation
• Support for 4 channels
• 8, 16, 24, and 32 bit frames
• Receive and transmit DMA support
• Wakeup on FIFO status (full/empty/threshold)
• Pulse density modulation support for receive channel
• Word select polarity control
• First bit position selection
• Interrupts generated for FIFO status​
• Receiver FIFO depth of 32 bytes
• Transmitter FIFO depth of 32 bytes

The MAX78000 provides one instance of the I²S peripheral (I2S0).

SPI is a highly configurable, flexible, and efficient synchronous interface among multiple SPI devices on a single bus. The bus uses a single clock signal and multiple data signals, and one or more slave select lines to address only the intended target device. The SPI operates independently and requires minimal processor overhead.

The provided SPI peripherals can operate in either slave or master mode and provide the following features:

• SPI modes 0, 1, 2, or 3 for single-bit communication
• 3- or 4-wire mode for single-bit slave device communication
• Full-duplex operation in single-bit, 4-wire mode
• Dual and quad data modes supported
• Multiple slave selects on some instances
• Multimaster mode fault detection
• Programmable interface timing
• Programmable SCK frequency and duty cycle
• 32-byte transmit and receive FIFOs
• Slave select assertion and deassertion timing with respect to leading/trailing SCK edge

The MAX78000 provides two instances of the SPI peripheral—SPI0 and SPI1. See Table 5 for configuration options.

​

The universal asynchronous receiver-transmitter (UART, LPUART) interface supports full-duplex asynchronous communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a given port, the system uses two extra pins to implement the industry-standard request to send (RTS) and clear to send (CTS) flow control signaling. Each instance is individually programmable.

• 2-wire interface or 4-wire interface with flow control
• 8-byte send/receive FIFO
• Full-duplex operation for asynchronous data transfers
• Interrupts available for frame error, parity error, CTS, Rx FIFO overrun, and FIFO full/partially full conditions
• Automatic parity and frame error detection
• Independent baud-rate generator
• Programmable 9th-bit parity support
• Multidrop support
• Start/stop bit support
• Hardware flow control using RTS/CTS
• 12.5Mbps for UART maximum bit rate
• 1.85Mbps for LPUART maximum bit rate
• Two DMA channels can be connected (read and write FIFOs)
• Programmable word size (5 bits to 8 bits)

The MAX78000 provides four instances of the UART peripheral—UART0, UART1, UART2, and LPUART0. LPUART0 is capable of operation in the SLEEP, LOW POWER, and MICRO POWER modes. See Table 6 for configuration options.

Maxim's 1-Wire bus consists of one signal that carries data and also supplies power to the slave devices and a ground return. The bus master communicates serially with one or more slave devices through the bidirectional, multidrop 1-Wire bus. The single-contact serial interface is ideal for communication networks requiring minimal interconnection.

The provided 1-Wire master supports the following features:

• Single contact for control and operation
• Unique factory identifier for any 1-Wire device
• Multiple device capability on a single line

The OWM supports both standard (15.6kbps) and overdrive (110kbps) speeds.

The standard DMA controller allows automatic one-way data transfer between two entities. These entities can be either memories or peripherals. The transfers are done without using CPU resources. The following transfer modes are supported:

• 4-channel
• Peripheral to data memory
• Data memory to peripheral
• Data memory to data memory
• Event support

All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from the FIFO.

The MAX78000 provides one instance of the standard DMA controller.

The dedicated hardware-based AES engine supports the following algorithms:

• AES-128
• AES-192
• AES-256

The AES keys are automatically generated by the engine and stored in dedicated flash to protect against tampering. Key generation and storage is transparent to the user.

The device provides a non-deterministic entropy source that can be used to generate cryptographic seeds or strong encryption keys as part of an overall framework for a secure customer application.

Software can use random numbers to trigger asynchronous events that add complexity to program execution to thwart replay attacks or key search methodologies.

The TRNG can support the system-level validation of many security standards. Maxim Integrated will work directly with the customer’s validation laboratory to provide the laboratory with any required information. Contact Maxim Integrated for details of compliance with specific standards.

A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application software. It supports a user-defined programmable polynomial up to 32-bits. Direct memory access copies data into the CRC module so that CRC calculations on large blocks of memory are performed with minimal CPU intervention. Examples of common polynomials are depicted in Table 7.

The bootloader allows loading and verification of program memory through a serial interface. Features include:

• Bootloader interface through UART
• Program loading of Motorola^® SREC format files
• Permanent lock state prevents altering or erasing program memory
• Access to the USN for device or customer application identification
• Disable SWD interface to block debug access port functionality

The secure boot feature ensures software integrity by automatically comparing program memory against a stored HMAC SHA-256 hash value after every reset. Programs that fail the integrity check indicate corrupted or modified program memory and are prevented from executing any instructions.

Devices with the secure boot feature also provide an optional challenge/response to authenticate before executing bootloader commands.