TemplateByTechPubs
CHGIN
Charger Input. Connect 2x 10μF (35V) between CHGIN and PGND. Connect a Schottky diode with anode at CHGIN and cathode at BYP if required. See the Design Considerations to Protect Against Hot Plug Event section.
CHGIN
BYP
CHGIN Bypass Pin. This pin is the input for the switching charger and the output for the boost converter when the charger is operating in 'reverse-boost' mode. Bypass with 2x 10μF (35V) ceramic capacitor from BYP to PGND.
BYP
T
T
IRQB
Interrupt Output. Connect a 100kΩ pullup resistor between IRQB and VIO.
IRQB
SCL
I2C Interface Clock Input
SCL
SDA
I2C Interface Data Input
SDA
PVDD
Internal Bias Regulator High Current Output Bypass Pin. Supplies internal noisy and high current gate drive loads. Bypass with 1x 1μF (6.3V) and 1x 100nF (6.3V) from PVDD to PGND.
Powering external loads from PVDD is not recommended, other than pullup resistors.
PVDD
THM
Thermistor Connection. Connect an external thermistor between THM and AGND.
THM
LX
Charger Switching Node. Connect the inductor between LX and SYS.
LX
SYS
Connection with System. Bypass with at least 2x 22μF (6.3V) ceramic capacitors from SYS to PGND.
This ensures that the minimum effective capacitance on the SYS node is 12μF (effective), for stability purposes.
For application purposes, SYS node capacitance can increase up to 350μF total (effective).
SYS
PGND
Charger Power Ground
PGND
BATTERY
BATTERY
AGND
Analog Ground
AGND
BST
High-Side FET Driver Supply. Bypass BST to LX with a 1x 100nF (6.3V) ceramic capacitor.
BST
SUSPND
Active-High Input to Disable the DC-DC Between CHGIN Input and SYS Output
SUSPND
BATSP
Battery Positive Differential Sense Pin. Connect to battery positive terminal as close as possible to eliminate errors due to trace/connector voltage drops.
BATSP
BATSN
Battery Negative Differential Sense Connection. Connect to the negative or ground terminal as close as possible.
BATSN
STAT
LED Low-Side Driver Output for Indicating Charging Status
STAT
DISQBAT
Active-high to disable internal QBATT FET between SYS and BATT.
DISQBAT
EXTSM
Exit Ship Mode Input by Push-Button. Active-high input.
EXTSM
DGND
Digital Ground
DGND
VIO
I2C Supply Voltage Input. Bypass to AGND with a 0.1μF (6.3V) capacitor.
VIO
QBEXT
External Battery FET Control Output. Connect a pullup resistor to VIO, SYS, or BATT supply.
QBEXT
VDD
Analog Voltage Level. The output of on-chip low voltage LDO used to power on-chip, low-noise circuits. Bypass with a 0.1μF (6.3V) ceramic capacitor to AGND.
Powering external loads from VDD is not recommended, other than pullup resistors.
VDD
PVDD
Internal Bias Regulator High Current Output Bypass Pin. Supplies internal noisy and high current gate drive loads. Bypass with 1x 1μF (6.3V) and 1x 100nF (6.3V) from PVDD to PGND.
Powering external loads from PVDD is not recommended, other than pullup resistors.
PVDD
MAX77976
MAX77976
SYS
Connection with System. Bypass with at least 2x 22μF (6.3V) ceramic capacitors from SYS to PGND.
This ensures that the minimum effective capacitance on the SYS node is 12μF (effective), for stability purposes.
For application purposes, SYS node capacitance can increase up to 350μF total (effective).
SYS
CHGIN
Charger Input. Connect 2x 10μF (35V) between CHGIN and PGND. Connect a Schottky diode with anode at CHGIN and cathode at BYP if required. See the Design Considerations to Protect Against Hot Plug Event section.
CHGIN
1.5kΩ
1.5kΩ
1.5kΩ
1.5kΩ
LX
Charger Switching Node. Connect the inductor between LX and SYS.
LX
LX
Charger Switching Node. Connect the inductor between LX and SYS.
LX
PGND
Charger Power Ground
PGND
PGND
Charger Power Ground
PGND
SYS
Connection with System. Bypass with at least 2x 22μF (6.3V) ceramic capacitors from SYS to PGND.
This ensures that the minimum effective capacitance on the SYS node is 12μF (effective), for stability purposes.
For application purposes, SYS node capacitance can increase up to 350μF total (effective).
SYS
SYS
Connection with System. Bypass with at least 2x 22μF (6.3V) ceramic capacitors from SYS to PGND.
This ensures that the minimum effective capacitance on the SYS node is 12μF (effective), for stability purposes.
For application purposes, SYS node capacitance can increase up to 350μF total (effective).
SYS
SYS
Connection with System. Bypass with at least 2x 22μF (6.3V) ceramic capacitors from SYS to PGND.
This ensures that the minimum effective capacitance on the SYS node is 12μF (effective), for stability purposes.
For application purposes, SYS node capacitance can increase up to 350μF total (effective).
SYS
BAT
Connection with Battery. Connect to the positive terminal of a single-cell Li-ion battery. Bypass with a 10μF (6.3V) ceramic capacitor from BATT to PGND.
BATT
BAT
Connection with Battery. Connect to the positive terminal of a single-cell Li-ion battery. Bypass with a 10μF (6.3V) ceramic capacitor from BATT to PGND.
BATT
BAT
Connection with Battery. Connect to the positive terminal of a single-cell Li-ion battery. Bypass with a 10μF (6.3V) ceramic capacitor from BATT to PGND.
BATT
1µF
1µF
2x22µF
2x22µF
10µF
10µF
0.1µF
0.1µF
0.1µF
0.1µF
IN
IN
1µF
1µF
2.2µF
1µF
0.47µH, 2.6MHz / 1µH, 1.3MHz
1µH, 1.3MHz/ 0.47µH, 2.6MHz
0 .47µH, 2.6MHz
10nF
10nF
10kΩ
10kΩ
10kΩ
10kΩ
2x10µF/ 35V
2.2µF/ 35V
x 10 µF/ 35V
Note: The Schottky diode between CHGIN and BYP is required when using a fixed voltage adaptor higher than 15V. It is needed for USB Type-C PD high voltage applications in some cases. See the Design Consideration to Protect Against Hot Plug Event section for details.
