| PIN | NAME | FUNCTION | TYPE |
| 1 | DISQBAT | Active-high to disable internal QBATT FET between SYS and BATT. | DI |
| 2 | THM | Thermistor Connection. Connect an external thermistor between THM and AGND. | A |
| 3 | VDD |
Analog Voltage Level. The output of on-chip low voltage LDO used to power on-chip, low-noise circuits. Bypass with a 0.1μF (6.3V) ceramic capacitor to AGND. Powering external loads from VDD is not recommended, other than pullup resistors. |
A |
| 4 | BATSN | Battery Negative Differential Sense Connection. Connect to the negative or ground terminal as close as possible. | A |
| 5 | BATSP | Battery Positive Differential Sense Pin. Connect to battery positive terminal as close as possible to eliminate errors due to trace/connector voltage drops. | A |
| 6, 7, 8 | BATT | Connection with Battery. Connect to the positive terminal of a single-cell Li-ion battery. Bypass with a 10μF (6.3V) ceramic capacitor from BATT to PGND. | P |
| 9, 10, 11 | SYS |
Connection with System. Bypass with at least 2x 22μF (6.3V) ceramic capacitors from SYS to PGND. This ensures that the minimum effective capacitance on the SYS node is 12μF (effective), for stability purposes. For application purposes, SYS node capacitance can increase up to 350μF total (effective). |
P |
| 12 | PVDD |
Internal Bias Regulator High Current Output Bypass Pin. Supplies internal noisy and high current gate drive loads. Bypass with 1x 1μF (6.3V) and 1x 100nF (6.3V) from PVDD to PGND. Powering external loads from PVDD is not recommended, other than pullup resistors. |
P |
| 13 | DGND | Digital Ground | A |
| 14, 15 ,16 | PGND | Charger Power Ground | P |
| 17, 18, 19 | LX | Charger Switching Node. Connect the inductor between LX and SYS. | P |
| 20 | BST | High-Side FET Driver Supply. Bypass BST to LX with a 1x 100nF (6.3V) ceramic capacitor. | A |
| 21 | BYP | CHGIN Bypass Pin. This pin is the input for the switching charger and the output for the boost converter when the charger is operating in 'reverse-boost' mode. Bypass with 2x 10μF (35V) ceramic capacitor from BYP to PGND. | P |
| 22, 23 | CHGIN | Charger Input. Connect 2x 10μF (35V) between CHGIN and PGND. Connect a Schottky diode with anode at CHGIN and cathode at BYP if required. See the Design Considerations to Protect Against Hot Plug Event section. | P |
| 24 | SCL | I2C Interface Clock Input | DI |
| 25 | SDA | I2C Interface Data Input | DI |
| 26 | EXTSM | Exit Ship Mode Input by Push-Button. Active-high input. | DI |
| 27 | VIO | I2C Supply Voltage Input. Bypass to AGND with a 0.1μF (6.3V) capacitor. | P |
| 28 | AGND | Analog Ground | A |
| 29 | STAT | LED Low-Side Driver Output for Indicating Charging Status | A |
| 30 | QBEXT | External Battery FET Control Output. Connect a pullup resistor to VIO, SYS, or BATT supply. | DO |
| 31 | SUSPND | Active-High Input to Disable the DC-DC Between CHGIN Input and SYS Output | DI |
| 32 | IRQB | Interrupt Output. Connect a 100kΩ pullup resistor between IRQB and VIO. | DO |