Functional Diagram
Functional Diagram
Functional Diagram
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CHGIN
Charger Input. Connect 2x 10μF (35V) between CHGIN and PGND. Connect a Schottky diode with anode at CHGIN and cathode at BYP if required. See the Design Considerations to Protect Against Hot Plug Event section.
CHGIN
CHGIN
SYS
Connection with System. Bypass with at least 2x 22μF (6.3V) ceramic capacitors from SYS to PGND. This ensures that the minimum effective capacitance on the SYS node is 12μF (effective), for stability purposes. For application purposes, SYS node capacitance can increase up to 350μF total (effective).
SYS
SYS
LX
Charger Switching Node. Connect the inductor between LX and SYS.
LX
LX
PGND
Charger Power Ground
PGND
PGND
BYP
CHGIN Bypass Pin. This pin is the input for the switching charger and the output for the boost converter when the charger is operating in 'reverse-boost' mode. Bypass with 2x 10μF (35V) ceramic capacitor from BYP to PGND.
BYP
BYP
BATT
Connection with Battery. Connect to the positive terminal of a single-cell Li-ion battery. Bypass with a 10μF (6.3V) ceramic capacitor from BATT to PGND.
BATT
BATT
Input Control
INPUT CONTROL
INPUT CONTROL
2x22uF 10V 0603
2x22µF 10V, 0603
2x22µF 10V, 0603
10uF 10V 0603
10µF 10V, 0603
10µF 10V, 0603
CONTROL REGISTERS
CONTROL REGISTERS
CONTROL REGISTERS
1.0uH/ 0.47uH
1.0µH/ 0.47µH
1.0µH/ 0.47µH
BYP
CHGIN Bypass Pin. This pin is the input for the switching charger and the output for the boost converter when the charger is operating in 'reverse-boost' mode. Bypass with 2x 10μF (35V) ceramic capacitor from BYP to PGND.
BYP
BYP
BATT
Connection with Battery. Connect to the positive terminal of a single-cell Li-ion battery. Bypass with a 10μF (6.3V) ceramic capacitor from BATT to PGND.
BATT
BATT
VUSB/VADP
VUSB/VADP
VUSB/VADP
Junction Temperature Sensor Temp.
JUNCTION TEMPERATURE SENSOR
JUNCTION
TEMPERATURE
SENSOR
SYS
Connection with System. Bypass with at least 2x 22μF (6.3V) ceramic capacitors from SYS to PGND. This ensures that the minimum effective capacitance on the SYS node is 12μF (effective), for stability purposes. For application purposes, SYS node capacitance can increase up to 350μF total (effective).
SYS
SYS
1.6/3.2MHz Buck Controller Charge Controller Reverse Boost Co...
Charge Timer
CHARGE TIMER
CHARGE
TIMER
VMBATT
VMBATT
VMBATT
VSYS
VSYS
VSYS
VCHGIN
VCHGIN
VCHGIN
Watchdog
WATCHDOG
WATCHDOG
Up to 5.5A of Charge current and Up to 10A of Discharge Current
UP TO 5.5A CHARGE UP TO 10A DISCHARGE
UP TO 5.5A CHARGE UP TO 10A DISCHARGE
BAT_SP
Battery Positive Differential Sense Pin. Connect to battery positive terminal as close as possible to eliminate errors due to trace/connector voltage drops.
BATSP
BATSP
BAT_SN
Battery Negative Differential Sense Connection. Connect to the negative or ground terminal as close as possible.
BATSN
BATSN
VBYP
VBYP
VBYP
VIBATT
VIBATT
VIBATT
+
+
+
RINSD
RINSD
R
INSD
GNDA
Analog Ground
AGND
AGND
BST
High-Side FET Driver Supply. Bypass BST to LX with a 1x 100nF (6.3V) ceramic capacitor.
BST
BST
1uF 6.3V 0402
1µF 6.3V, 0402
1µF 6.3V, 0402
PVDD
Internal Bias Regulator High Current Output Bypass Pin. Supplies internal noisy and high current gate drive loads. Bypass with 1x 1μF (6.3V) and 1x 100nF (6.3V) from PVDD to PGND. Powering external loads from PVDD is not recommended, other than pullup resistors.
PVDD
PVDD
Reg
REG
REG
0.1uF 6.3V 0402
0.1µF 6.3V, 0402
0.1µF 6.3V, 0402
4x10uF 35V 0603
Reverse Blocking
REVERSE BLOCKING
REVERSE
BLOCKING
BST
High-Side FET Driver Supply. Bypass BST to LX with a 1x 100nF (6.3V) ceramic capacitor.
BST
BST
MAX77975/MAX77976
MAX77975/MAX77976
MAX77975/MAX77976
2x10µF 35V, 0603
2x10µF 35V, 0603
1.3MHz / 2.6 MHz BUCK CONTROL CHARGE CONTROL REVERSE BOOST CO...
1.3MHz / 2.6 MHz
BUCK CONTROL
CHARGE CONTROL
REVERSE BOOST CONTROL
QCHGIN
Q
CHGIN
QHS
Q
HS
QLS
Q
LS
QBAT
Q
BAT
UP TO +19.5V OPERATING UP TO 3A INPUT CURRENT
UP TO +19V OPERATING
UP TO
3A INPUT CURRENT
2.2µF 35V, 0603
2
x
10
µF 35V, 0603
