Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics

(VSYS = 3.8V, VBATT = 3.8V, VVIO = 1.8V, VCHGIN = 5V, unless otherwise specified. Limits are production tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization.)

GENERAL ELECTRICAL CHARACTERISTICS
CHGIN Quiescent Current ICHGIN VCHGIN = 5.0V, SUSPEND pin digital high or MODE = 0, DEEP_SUSP_DIS = 1 0.19 0.38 mA
VCHGIN = 5.0V, SUSPEND pin digital high or MODE = 0, DEEP_SUSP_DIS = 0 85 μA
VCHGIN = 5.0V, VBATT = 4.2V, MODE = 5, DONE state (VSYS = 4.35V), ISYS = 0A 2.35 mA
Input Undervoltage Supply Current IIN VCHGIN = 2.4V, the input is undervoltage 0.035 mA
BAT Quiescent Current IBAT VCHGIN = 0V, VBATT = 3.6V, QBATT FET is on, LPM = 0, ISYS = 0A 29 µA
BAT Quiescent Current in Low-Power Mode IBAT VCHGIN = 0V, VBATT = 3.6V, QBATT FET is on, LPM = 1, ISYS = 0A 22 µA
BAT Quiescent Current in Factory-Ship Mode IBAT VCHGIN = 0V, VBATT = 3.6V, QBATT FET is off, VSYS = VVDD = 0V, factory-ship mode 3 µA
BAT Quiescent Current in Done State IMBDN VCHGIN = 5V, IBYP = 0A, VBATT = 4.2V, ISYS = 0A, QBATT FET is off, MODE = 5, done state 7.5 10.5 µA
SYS Operating Voltage VSYS Guaranteed by VSYS_UVLO_R and VSYS_OVLO_R VSYS_UVLO_R VSYS_OVLO_R V
VIO Voltage Range VVIO 1.62 5.5 V
SCL, SDA Input Low Level VSCL_SDA_IN_L TA = +25°C 0.3 x VVIO V
SCL, SDA Input High Level VSCL_SDA_IN_H TA = +25°C 0.7 x VVIO V
SCL, SDA Input Hysteresis VSCL_SDA_HYS TA = +25°C 0.05 x VVIO V
SCL, SDA Logic Input Current ISCL_SDA VSCL = VSDA = VVIO = 1.9V -10 +10 µA
SDA Output Low Voltage VSDA_OUT_L ISDA = 20mA sinking 0.4 V
IRQB Output Low Voltage VIRQB_OUT_L IIRQB = 1mA sinking 0.4 V
IRQB Output High Leakage IIRQB_H VIRQB = 5.5V, TA = 2+5°C -1 0 +1 μA
VIRQB = 5.5V, TA = +85°C 0.1
CHGIN INPUT LIMITER
CHGIN Operating Voltage Range VCHGIN VCHGIN must be less than VCHGIN_OVLO and greater than both VCHGIN_UVLO and (VSYS + VCHGIN2SYS_TH) for the charger to turn-on VCHGIN_UVLO VCHGIN_OVLO V
CHGIN Overvoltage Threshold VCHGIN_OVLO VCHGIN rising 19 19.5 20 V
CHGIN Overvoltage Threshold Hysteresis VCHGIN_OVLO_HYS 500 mV
CHGIN Undervoltage Threshold Setting Range VCHGIN_UVLO VCHGIN rising, 20% hysteresis, programmable at 4.7V, 4.8V, 4.9V, 5.05V 4.7 5.05 V
CHGIN Undervoltage Threshold Accuracy VCHGIN_UVLO_ACC VCHGIN rising, 4.7V setting 4.6 4.7 4.8 V
CHGIN to SYS Undervoltage Threshold Rising VCHGIN2SYS_TH VCHGIN - VSYS, rising 0.12 0.20 0.28 V
CHGIN Turn-On Threshold Validation Delay tD-UVLO Delay from VCHGIN > VCHGIN_UVLO to QCHGIN FET enable 8 ms
CHGIN Switching Start Delay tSTART Delay from Input Validation to LX switching (if charge or buck mode is selected and charger is not suspended); see the Input Validation section for input validation conditions 150 ms
CHGIN Adaptive Voltage Regulation Threshold Setting Range VCHGIN_REG Programmable at 4.5V, 4.6V, 4.7V, 4.85V. The input voltage regulation loop decreases the input current to regulate VCHGIN at VCHGIN_REG under weak input source conditions. If the input current is decreased to IIULO_DET and the input voltage is equal or below VCHGIN_REG, then the charger input is turned off. 4.5 4.85 V
CHGIN Adaptive Voltage Regulation Threshold Accuracy VCHGIN_REG_ACC 4.5V setting 4.4 4.5 4.6 V
CHGIN Input Current Limit Setting Range IINLIMIT Programmable, 500mA default, 50mA step, production tested at 100mA, 500mA, 1000mA, 1800mA, and 3200mA settings only 0.1 3.2 A
CHGIN Input Current Limit Accuracy IINLIMIT Charger enabled, 500mA input current limit setting 440 470 500 mA
Charger enabled, 1000mA input current limit setting 880 940 1000
Charger enabled, 1800mA input current limit setting 1584 1692 1800
Charger enabled, 3200mA input current limit setting 2816 3008 3200
CHGIN Input Current Low Threshold IIULO_DET Charger enabled, 3200mA input current limit setting 60 mA
SYSTEM BUCK
Buck Output Voltage Setting Range (Tracking Disabled) VSYSREG Programmable 4.15V to 4.46V in 10mV steps (5-bits). Production tested at 4.2V only. 4.15 4.46 V
Buck Output Voltage Accuracy (Tracking Disabled) VSYSREG_ACC Buck only, charging disabled -3 +3 %
Buck Output Voltage (Tracking Enabled) VSYSREG_TRK_MIN MODE = 4, SYS Tracking mode enabled, VBATT < VSYS_MIN/1.04 3.48 3.60 3.72 V
VSYSREG_TRK MODE = 4, SYS Tracking mode enabled, VBATT ≥ VSYS_MIN/1.04, VSYSREG_TRK represented as a percentage of VBATT 104 %
Buck Inductor Current Limit IHSILIM For MAX77976 8.5 9.5 10.5 A
IHSILIM For MAX77975 5.95 7.00 8.05
Buck Minimum On Time tON-MIN Measured on LX 100 ns
Buck Minimum Off Time tOFF-MIN Measured on LX 100 ns
System Power-Up Current (from BYP) ISYSPU_BYP Charger present, VSYS < VSYS_UVLO_R 50 75 100 mA
System Power-Up Time-Out (from BYP) tSYSPU_BYP 150 ms
CHARGER
Precharge Charge Current IPRECHG VBATT < VPRECHG 40 55 80 mA
Precharge Voltage Threshold VPRECHG VBATT rising 2.4 2.5 2.6 V
Precharge Voltage Threshold Hysteresis VPRECHG_HYS 500 mV
Trickle Charge Current ITRICKLE TKEN = 1 by default, VPRECHG < VBATT < VTRICKLE 270 300 330 mA
Trickle Charge Voltage Threshold VTRICKLE VBATT rising, TKEN = 1 by default 3.0 3.1 3.2 V
Trickle Charge Voltage Threshold Hysteresis VTRICKLE_HYS TKEN = 1 by default 100 mV
Prequalification Time tPQ Applies to the total time of precharge and trickle charge mode 30 min
Fast-Charge Current Setting Range IFC 100mA to 5500mA in 50mA steps; production tested at 500mA, 1000mA, 3000mA, and 5000mA settings (MAX77976 only) 0.1 5.5 A
100mA to 3500mA in 50mA steps; production tested at 500mA, 1000mA, and 3000mA settings (MAX77975 only) 0.1 3.5
Fast-Charge Current Accuracy IFC_ACC Programmed IFC ≥ 500mA, VBATT > VSYSMIN, TA = +25°C -3.5 +3.5 %
Programmed IFC ≥ 500mA, VBATT > VSYSMIN, TA = 0°C to +85°C -6 +6
Programmed IFC ≥ 500mA, VTRICKLE < VBATT < VSYSMIN (LDO mode), TA = -5°C to +85°C -10 +10
Fast-Charge Current Thermal Regulation Setting Range TREG Junction temperature when charge current starts to reduce for thermal regulation; programmable from +85°C to +130°C in 5°C steps; default value is +115°C 85 130 °C
Fast-Charge Current Thermal Regulation Gain ATJREG The charge current is decreased 5.73% of the fast-charge current full-scale for every degree that the junction temperature exceeds the thermal regulation temperature. This slope ensures that the full-scale current of 5.5A is reduced to 0A by the time the junction temperature is +17.5°C above the programmed loop set point. For lower programmed charge currents such as 480mA, this slope is valid for charge current reductions down to 80mA; below 100mA the slope becomes shallower but the charge current is reduced to 0A if the junction temperature is +20°C above the programmed loop set point. -315 mA/°C
Fast-Charge Termination Voltage Setting Range VBATTREG Programmable from 4.15V to 4.46V in 10mV steps (5-bits); production tested at 4.2V and 4.35V only 4.15 4.46 V
Fast-Charge Termination Voltage Accuracy at Room Temp VBATTREG_ACC VBATTREG = 4.35V setting, represented as percentage of VBATTREG; TA = +25°C -0.6 -0.3 +0.0 %
Fast-Charge Termination Voltage Accuracy VBATTREG_ACC VBATTREG = 4.35V setting, represented as percentage of VBATTREG; TA = -5°C to +85°C -0.8 -0.3 +0.2 %
Fast-Charge Termination Debounce Time tTERM 30 ms
Fast-Charge Constant Current + Constant Voltage Safety Time tFC Adjustable from 3hrs, 4hrs, 5hrs, 6hrs, 7hrs, 8hrs including a disable setting; 5hrs default 5 hrs
Top-Off Current Setting Range ITO Programmable from 150mA to 850mA with 50mA in 16 steps;
production tested at 150mA, 200mA, 500mA, and 850mA settings 		150 850 mA
Top-Off Current Accuracy ITO_ACC 150mA setting 122.5 177.5 mA
200mA setting 170 230
500mA setting 455 545
850mA setting 787.5 912.5
Top-Off Time tTO Adjustable from 30sec to 70min in 10min steps; default setting is 30min 30 min
Charge Restart Threshold Setting Range VRSTRT Adjustable at 100mV, 150mV, and 200mV; it can also be disabled 100 150 200 mV
Charge Restart Debounce Time tCRDG 130 ms
Charge State Change Interrupt Debounce Time tSCIDG Excludes transition to timer fault state, watchdog timer state 30 ms
Charge Watchdog Time tWD 80 s
Charge Timers Accuracy tACC -20 +20 %
Charge-Overvoltage Threshold VCOV VBAT_SP - VBAT_SN, relative to VCHG_CV_PRM 200 mV
Remote Sense BAT_SP Input Current in Charging Mode IBAT_SP_CHG VBATT_SP = VBATT = 3.8V, MODE = 5, TA = +25°C 14 μA
Remote Sense BAT_SN Input Current in Charging Mode IBAT_SN_CHG VBATT_SN = 0, MODE = 5, TA = +25°C 10 μA
SMART POWER SELECTOR
System Regulation Voltage (Charging Enabled, Low Battery) VSYSMIN Charging enabled, VBATT < VSYSMIN - VSYSTRK 3.492 3.600 3.708 V
VSYSTRK Charging enabled, VSYSMIN - VSYSTRK < VBATT < VSYSMIN, measure of VSYS - VBATT 0.45
BATT to SYS Reverse Regulation Voltage VBSREG Measure of VSYS - VBATT; production tested at 10mA and 2A -100 mV
SYS Self-Discharge Resistor RSYSSD Switching is disabled, QBATT FET is off, VSYS < VSYSUVLO_F 600 Ω
SYSTEM POWER-UP
System Power-Up Current (from BATT) ISYSPU_BAT VCHGIN = 0V 35 50 80 mA
System Power-Up Voltage (from BATT) VSYSPU_BAT VSYS rising, 100mV hysteresis 1.9 2.0 2.1 V
System Power-Up Time-Out (from BATT) tSYSPU_BAT 150 ms
REVERSE BOOST
Reverse Boost Quiescent Current VBYP = 5.1V, VBATT = 3.8V, MODE = 0x0A, VBYPSET = 0x1 2.5 mA
Reverse Boost Output Voltage Setting Range VBYP_OTG Measured on BYP pin, 2.5V < VBATT < 4.5V; adjustable from 5V to 12V with 0.1V step; production tested at 5V and 12V 5 12 V
Reverse Boost Output Voltage Accuracy VBYP_ACC Measured on BYP, MODE = 0x0A, VBYPSET = 0x1 4.95 5.10 5.25 V
Reverse Boost Inductor Current Limit ILSILIM For MAX77976 8.5 9.5 10.5 A
ILSILIM For MAX77975 5.95 7.00 8.05
CHGIN OUTPUT LIMITER
OTG Output Current Limit Setting Range (MAX77975) ICHGIN_OTG_LIM Configurable from 500mA to 2400mA in 100mA steps. Clamped to 12W power limit 500 2400 mA
OTG Output Current Limit Setting Range (MAX77976) ICHGIN_OTG_LIM Configurable from 500mA to 3100mA in 100mA steps. Clamped to 18W power limit 500 3100 mA
OTG Output Current Limit  ICHGIN_OTG_LIM 3.4V < VBATT < 4.5V, OTG_ILIM = 0x00 500 537 575 mA
3.4V < VBATT < 4.5V, OTG_ILIM = 0x04 900 967 1035
3.4V < VBATT < 4.5V, OTG_ILIM = 0x0A 1500  1612 1725
3.4V < VBATT < 4.5V, OTG_ILIM = 0x19 (MAX77975 only) 2400 2580 2760
3.4V < VBATT < 4.5V, OTG_ILIM = 0x19 (MAX77976 only) 3000 3225 3450
OTG Output Current Limit Alarm Time tOTG_ALARM Delay from OTG overcurrent event to BYP_I interrupt generated 20 ms
OTG Output Current Limit Fault Time tOTG_FAULT Delay from OTG overcurrent event to QCHGIN FET opening 30 ms
OTG Output Current Limit Retry Time tOTG_RETRY Delay from QCHGIN FET opening to QCHGIN FET closing again (OTG_REC_EN = 1) 300 ms
SWITCHE IMPEDANCES AND LEAKAGE CURRENTS
CHGIN to BYP On Resistance at Room Temp RCHGIN2BYP_ROOM CHGIN pin to BYP pin, TA = +25°C 13.0 16.9 mΩ
CHGIN to BYP On Resistance RCHGIN2BYP CHGIN pin to BYP pin, TA = -40°C to +85°C 13.0 20.0 mΩ
LX High-Side On Resistance at Room Temp RHS_ROOM BYP pin to LX pin, TA = +25°C 31.0 43.4 mΩ
LX High-Side On Resistance RHS BYP pin to LX pin, TA = -40°C to +85°C 31.0 54.3 mΩ
LX Low-Side On Resistance at Room Temp RLS_ROOM LX pin to PGND pin, TA = +25°C 16.0 22.4 mΩ
LX Low-Side On Resistance RLS LX pin to PGND pin, TA = -40°C to +85°C 16.0 28.0 mΩ
BATT to SYS On Resistance at Room Temp RBAT2SYS_ROOM BATT pin to SYS pin, VBATT = 4.4V, TA = +25°C 7.70 11.05 mΩ
BATT to SYS On Resistance RBAT2SYS BATT pin to SYS pin, VBATT = 4.4V, TA = -40°C to +85°C 7.70 12.75 mΩ
LX Leakage Current ILX_LEAK VLX = VPGND or VBYP, TA = +25°C 0.01 10 µA
VLX = VPGND or VBYP, TA = +85°C 1
BST Leakage Current IBST_LEAK VBST - VLX = 1.8V, TA = +25°C 0.01 10 µA
VBST - VLX = 1.8V, TA = +85°C 1
BYP Leakage Current IBYP_LEAK VBYP = 5.5V, VCHGIN = 0V, VLX = 0V, charger disabled, TA = +25°C 0.01 10 µA
VBYP = 5.5V, VCHGIN = 0V, VLX = 0V, charger disabled, TA = +85°C 1
BATSP Input Current Leakage IBATSP Charger disabled, VBATSP = VBATT, TA = +25°C ±1 μA
BATSN Input Current Leakage IBATSN Charger disabled, VBATSN = VAGND, TA = +25°C ±1 μA
LOGIC AND CONTROL I/Os
Input Low Level VIL SUSPND, DISQBAT, TA = +25°C 0.4 V
EXTSM, TA = +25°C 0.3 x VBATT
Input High Level VIH SUSPND, DISQBAT, TA = +25°C 1.4 V
EXTSM, TA = +25°C 0.7 x VBATT
Input Leakage Current ILK SUSPND, DISQBAT, EXTSM pin, at 5.5V (including current through pulldown resistor) 24 60 µA
Output Low Voltage QBEXT VOLQBEXT Sourcing 1mA, TA = +25°C 0.4 V
Output High Leakage QBEXT ILQBEXT VSYS = 5.5V, TA = +25°C -1 0 +1 µA
VSYS = 5.5V, TA = +85°C 0.1
SUSPND Internal Pulldown Resistor RSUSPND 235 kΩ
DISQBAT Internal Pulldown Resistor RDISQBAT 235 kΩ
EXTSM Internal Pulldown Resistor REXTSM 235 kΩ
EXTSM Debounce Time tEXTSM_DEB VBATT in 3.3V to 4.5V range, EXTSM_T = 0 10 ms
VBATT in 3.3V to 4.5V range, EXTSM_T = 1 0.1
CHARGE STATUS INDICATOR
Charge Status Current Setting Range ISTAT_RNG 5mA to 20mA in 5mA steps; production tested at VSTAT - VAGND = 1.0V and 5.0V 5 20 mA
Charge Status Current Accuracy ISTAT_ACC Production tested at 5mA and 20mA -30 +30 %
THERMISTOR MONITOR
THM Threshold, COLD THM_COLD VTHM/VPVDD rising, 1% hysteresis (thermistor temperature falling) 73.8 75.0 76.2 %
THM Threshold, COOL THM_COOL VTHM/VPVDD rising, 1% hysteresis (thermistor temperature falling) 64.3 65.5 66.7 %
THM Threshold, WARM THM_WARM VTHM/VPVDD falling, 1% hysteresis (thermistor temperature rising) 30.8 32.0 33.2 %
THM Threshold, HOT THM_HOT VTHM/VPVDD falling, 1% hysteresis (thermistor temperature rising) 20.8 22.0 23.2 %
THM Threshold, Disabled THM_DIS VTHM/VPVDD falling, 1% hysteresis, THM function is disabled below this voltage 4.8 6.0 7.2 %
THM Threshold, Battery Removal Detection THM_RM VTHM/VPVDD rising, 1% hysteresis, battery removal  85 87 89 %
THM Input Leakage Current ILKTHM VTHM = VAGND or VPVDD, charger disabled, TA = +25°C 0.1 1 µA
VTHM = VAGND or VPVDD, charger disabled, TA = +85°C 0.1
SUPPLIES AND MONITORING
VDD Output Voltage VVDD_1P8 VSYS or VBATT = 3.8V, IVDD = 20mA 1.71 1.80 1.89 V
SYS Undervoltage-Lockout Threshold (SYS Rising) VSYS_UVLO_R 2.74 2.80 2.86 V
SYS Undervoltage-Lockout Threshold (SYS Falling) VSYS_UVLO_F 2.55 2.60 2.65 V
SYS Undervoltage-Lockout Hysteresis VSYS_UVLO_H 200 mV
SYS Overvoltage-Lockout Threshold (SYS Rising) VSYS_OVLO_R SYS rising 5.2 5.35 5.5 V
SYS Overvoltage-Lockout Threshold (SYS Falling) VSYS_OVLO_F SYS falling 5 5.15 5.3 V
SYS Overvoltage-Lockout Hysteresis VSYS_OVLO_H 200 mV
Thermal Shutdown Threshold TSHDN_R Tj rising 155 °C
Thermal Shutdown Threshold Hysteresis TSHDN_H 15 °C
PVDD Output Voltage VPVDD_1P8 VSYS = 3.8V, IPVDD = 20mA 1.71 1.80 1.89 V
I2C-COMPATIBLE INTERFACE TIMING FOR STANDARD, FAST, AND FAST-MODE PLUS
Clock Frequency fSCL 1000 kHz
Hold Time (Repeated) START Condition tHD;STA 0.26 µs
CLK Low Period tLOW 0.5 µs
CLK High Period tHIGH 0.26 µs
Set-Up Time Repeated START Condition tSU;STA 0.26 µs
DATA Hold Time tHD:DAT 0 µs
DATA Valid Time tVD:DAT 0.45 µs
DATA Valid Acknowledge Time tVD:ACK 0.45 µs
DATA Set-Up time tSU;DAT 50 ns
Set-Up Time for STOP Condition tSU;STO 0.26 µs
Bus-Free Time Between STOP and START tBUF 0.5 µs
Pulse Width of Spikes that must be Suppressed by the Input Filter tSP 50 ns
I2C-COMPATIBLE INTERFACE TIMING FOR HS-MODE (CB = 100pF)
Clock Frequency fSCL 3.4 MHz
Set-Up Time Repeated START Condition tSU;STA 160 ns
Hold Time (Repeated) START Condition tHD;STA 160 ns
CLK Low Period tLOW 160 ns
CLK High Period tHIGH 60 ns
DATA Set-Up time tSU;DAT 10 ns
DATA Hold Time tHD:DAT 0 ns
Set-Up Time for STOP Condition tSU;STO 160 ns
Pulse Width of Spikes that must be Suppressed by the Input Filter tSP 10 ns
I2C-COMPATIBLE INTERFACE TIMING FOR HS-MODE (CB = 400pF)
Clock Frequency fSCL 1.7 MHz
Set-Up Time Repeated START Condition tSU;STA 160 ns
Hold Time (Repeated) START Condition tHD;STA 160 ns
CLK Low Period tLOW 320 ns
CLK High Period tHIGH 120 ns
DATA Set-Up time tSU;DAT 10 ns
DATA Hold Time tHD:DAT 0 ns
Set-Up Time for STOP Condition tSU;STO 160 ns
Pulse Width of Spikes that must be Suppressed by the Input Filter tSP 10 ns