- Complete Li+/LiPoly Battery Charger
- Prequalification, Constant Current, Constant Voltage
- 55mA Precharge Current
- 300mA Trickle Charge Current
- Adjustable Constant Current Charge
- 100mA to 5.5A in 50mA steps
- Adjustable Charge-Termination Threshold
- 150mA to 850mA in 50mA Steps
- Adjustable Battery Regulation Voltage
- 4.15V to 4.46V in 10mV Steps
- -0.8/+0.2% accuracy from 0°C to +85°C
- Remote Differential Sensing
- Synchronous Switch-Mode Based Design
- Smart Power Selector
- Optimally distributes power between the charge adapter, system, and battery.
- When powered by a charge adapter, the battery can provide supplemental current to the system.
- The charge adapter can support the system with a dead battery or without a battery.
- No External MOSFETs Required for Switcher
- CHGIN Input
- Adjustable Input Current Limit
- 100mA to 3.20A in 50mA steps (CHGIN_ILIM)
- Default is set to 500mA
- Supports AC-to-DC Wall Adapters
- VCHGIN_OVLO = 19V
- Reverse-Leakage Protection Prevents the Battery Leaking Current to the Inputs
- Adjustable Input Current Limit
- Charge Safety Watchdog Timer
- Selectable: 3hr to 10hr, plus a Disable Setting
- Die Temperature Monitor with Thermal Foldback Loop
- Selectable Die-Temperature Thresholds (°C): +85°C to +130°C in +5°C steps
- Input Voltage Dropout Control Allows Operation from High-Impedance Sources (AICL)
- BATT to SYS Switch is 7.7mΩ Typical
- Capable of 10A Steady-State Operation from BATT to SYS
- Short-Circuit Protection
- DISIBS Bit Allows the Host to Disable the Battery to System Discharge Path to Protect Against a Short-Circuit
- SYS Short to Ground
- Buck current is limited by switcher current limit and disabling of the synchronous rectifier.
The MAX77975/MAX77976 includes a full-featured switch-mode charger for a one-cell lithium-ion (Li+) or lithium-polymer (Li-polymer) battery. The current limit for CHGIN input is independently programmable from 100mA to 3.2A in 50mA steps allowing the flexibility for connection to either an AC-to-DC wall charger or a USB port.
The synchronous switch-mode DC-DC converter utilizes a high 1.3MHz/2.6MHz switching frequency which is ideal for portable devices because it allows the use of small components while eliminating excessive heat generation. The DC-DC has both a buck and a boost mode of operation. When charging the main-battery the converter operates as a buck. The DC-DC buck operates from a 4.3V to 19.5V source. The battery charge current is programmable from 100mA to 5.5A.
As a boost converter, the DC-DC uses energy from the main-battery to boost the voltage at BYP. The BYP supplies the USB OTG voltage (5.1V) and USB Type-C® PD Source Voltages (5V to 12V). The programmable boost output current limit range is from 0.5A to 3.1A with a 0.1A step.
Maxim’s Smart Power Selector architecture makes the best use of the limited adapter power and the battery’s power at all times to supply up to buck current limit from the buck to the system. (Additionally, supplement mode provides additional current from the battery to the system.) Adapter power that is not used for the system goes to charging the battery. All power switches for charging and switching the system load between the battery and adapter power are included on-chip—no external MOSFETs are required.
A multitude of safety features ensures reliable charging. Features include a charge timer, watchdog, junction thermal regulation, over/under voltage protection, and short circuit protection.
The SPS architecture is a network of internal switches and control loops that distribute energy between external power sources CHGIN, BYP, SYS, and BATT.
The Functional Diagram shows a detailed arrangement of the Smart Power Selector switches and gives them the following names: QCHGIN, QHS, QLS, and QBATT.
Switch and Control Loop Descriptions
- CHGIN Input Switch: The input switch is either completely on or completely off. As shown in the Functional Diagram, there are SPS control loops that monitor the current through the input switches as well as the input voltage.
- DC-DC Switches: QHS and QLS are the DC-DC switches that can operate as a buck (step-down) or a boost (step-up). When operating as a buck, energy is moved from BYP to SYS. When operating as a boost, energy is moved from SYS to BYP. SPS control loops monitor the DC-DC switch current, the SYS voltage, and the BYP voltage.
- Battery-to-System Switch: QBATT controls the battery charging and discharging. Additionally, QBATT allows the battery to be isolated from the system (SYS). An SPS control loop monitors the QBATT current.
Control Bits
- MODE configures the Smart Power Selector
- VBYPSET sets the BYP regulation voltage target
Energy Distribution Priority
- With a valid external power source:
- The external power source is the primary source of energy
- The main-battery is the secondary source of energy
- Energy delivery to BYP is the highest priority
- Energy delivery to SYS is the second priority
- Any energy that is not required by BYP or SYS is available to the main-battery charger
- With no power source available at CHGIN:
- The main-battery is the primary source of energy
- Energy delivery to BYP (if boost mode is selected) and SYS share the same priority
- BYP includes CHGIN if boost OTG mode is selected, itself limited by OTG_ILIM threshold
BYP Regulation Voltage
- When the DC-DC is off or in one of its buck modes and there is a valid power source at CHGIN, VBYP = VCHGIN - ICHGIN x RCHGIN2BYP.
- When the DC-DC is off and there is no valid power source at CHGIN, BYP is connected to LX through the high-side switch’s body diode.
SYS Regulation Voltage
- When the DC-DC is enabled as a buck and the charger is disabled, QBATT is off and VSYS is regulated to VSYSREG_TRK_MIN when the VBATT < VSYSMIN or VSYSREG_TRK when the VBATT ≥ VSYSMIN.
- When the DC-DC is enabled as a buck and the charger is enabled but in a non-charging state such as done, thermistor suspend, watchdog suspend or timer fault, QBATT is off and VSYS is regulated to VSYSREG_TRK_MIN when the VBATT < VSYSMIN or VSYSREG_TRK when the VBATT ≥ VSYSMIN.
- When the DC-DC is enabled as a buck and charging in prequalification, fast-charge, or top-off modes, VSYS is regulated to VSYSMIN when the VBATT < VSYSMIN; in this mode, the QBATT switch acts as a linear regulator and dissipates power [P = (VSYSMIN - VBATT) x IBATT]. When VBATT > VSYSMIN, then VSYS = VBATT + IBATT x RBAT2SYS; in this mode, the QBATT switch is closed.
- In all of the above modes, if the combined SYS and BYP loading exceeds the input current limit, then VSYS drops to VBATT - VBSREG and the battery provides supplemental current.
- When the DC-DC is enabled as a boost, then the QBATT switch is closed, and VSYS = VBATT - IBATT x RBAT2SYS.
The charger input is compared with several voltage thresholds to determine if it is valid. A charger input must meet the following four characteristics to be valid:
- CHGIN must be above VCHGIN_UVLO to be valid. Once CHGIN is above the UVLO threshold, the information (together with IN2SYS, described below) is latched and can only be reset when the charger is in adaptive input current loop (AICL) and input current is lower than the IULO_DET threshold.
- CHGIN must be below its overvoltage-lockout threshold (VCHGIN_OVLO).
- CHGIN must be above the system voltage by IN2SYS drop out.
- CHGIN input generates a CHGIN_I interrupt when its status changes. The input status can be read with CHGIN_OK and CHGIN_DTLS. Interrupts can be masked with CHGIN_M.
The default settings of the CHGIN_ILIM and MODE control bits are such that when a charge source is applied to CHGIN, the IC turns its DC-DC converter on in BUCK mode, limits VSYS to VSYSREG_TRK, and limits the charge source current to IINLIMIT. All control bits are reset on global shutdown.
An input voltage regulation loop allows the charger to be well behaved when it is attached to a poor quality charge source. The loop improves performance with relatively high resistance charge sources that exist when long cables are used or devices are charged with non-compliant USB hub configurations. Additionally, this input voltage regulation loop improves performance with current limited adapters. If the ICs input current limit is programmed above the current-limit threshold of a given adapter, the input voltage loop allows the IC to regulate at the current limit of the adapter. Finally, the input-voltage regulation loop allows the IC to perform well with adapters that have poor transient load response times.
The input voltage regulation loop automatically reduces the inductor average current to keep the input voltage at VCHGIN_REG. If the input current is reduced to IULO_DET and the input voltage is below VCHGIN_REG, then the charger input is turned off. VCHGIN_REG is programmable with VCHGIN_REG[1:0].
After operating with the input voltage regulation loop active, a AICL_I interrupt is generated, AICL_OK sets to 0. To optimize input power when working with a current limited charge source, monitor the AICL_OK status while decreasing the input current limit. When the input current limit is set below the limit of the adapter, the input voltage rises. Although the input current limit is lowered, more power can be extracted from the input source when the input voltage is allowed to rise.
Example 1. Optimum use of the Input Voltage Regulation Loop along with a current limited adapter.
Sequence of Events:
- VBATT = 3.2V, the system is operating normally.
- MODE = 0x04, CHGIN_ILIM = 100mA, CHG_CV_PRM = 4.2V, VCHGIN_REG = 4.5V, CHG_CC_TOT = 2.0A.
- A 5.0V 1.2A current limited dedicated USB charger is applied to CHGIN.
- The DC-DC buck regulator turns on, VSYS is regulated to VBATTREG (4.2V) and the input is allowed to provide 100mA to the system.
- The system detects that the charge source is a dedicated USB charger and enables the battery charger (MODE = 0x05) and programs an input current limit to 1.8A (CHGIN_ILIM = 1.8A).
- The input current limit starts to ramp up from 100mA to 1.8A, but at the input current limit of the adapter (1.2A), the adapter voltage collapses. The ICs input voltage regulation loop prevents the adapter voltage from falling below 4.5V (VCHGIN_REG = 4.5V). A AICL_I interrupt is generated and AICL_OK sets to 0.
- With the input-voltage regulation loop active, the adapter provides 1.2A at 4.5V which is a total of 5.4W being delivered to the system.
- The system software detects that the input voltage regulation loop is active and it begins to ramp down the programmed input current limit. When the current limit ramps down to 1.175A, the adapter is no longer in current limit, and the adapter voltage increases from 4.5V to 5.0V.
- With the adapter operating just below its current limit, it provides 1.175A at 5.0V which is a total of 5.88W to the system. This is 440mW more than when the adapter was in current limit.
To ensure a timely, complete, repeatable, and reliable reset behavior when the system has no power, the ICs actively discharge the SYS nodes when QBATT and switcher are disabled and VSYS is less than VSYSUVLO. As shown in Figure 1, the SYS discharge resistor is 600Ω.
Example 1. Basic System Self-Discharge
Initial Conditions: No charger adapter is present at CHGIN, the BAT-to-SYS switch is closed, CBAT = 100µF, CSYS = 200µF, VBATT = 3.6V, and VSYSUVLO falling is SYS_UVLOB_F.
Sequence of Events:
- With the system in its normal operating mode it is drawing 1A.
- The main battery is removed.
- The system continues to draw 1A until VSYS falls below VSYSUVLO. This takes 480µs ((3.6V-2.0V)/1A x 300µF).
- When the system voltage falls below VSYSUVLO, the system turns off leakage current. To facilitate discharging CBAT and CSYS the IC engages its 600Ω discharge resistors.
The MAX77975/MAX77976 transitions between power states as input/battery and load conditions dictate; see Figure 2.
The IC provides five (5) power modes and one (1) no power mode (MODE detailed description is at register CHG_CNFG_00 [3:0]). Under power limited conditions, the PowerPathTM feature maintains SYS load at the expense of battery charge current. Also, the battery supplements the input power when required. As shown, transitions between power states are initiated by detection/removal of valid power sources, OTG events, and undervoltage conditions. Details of the SYS voltage and BATT current are provided for each state. There are six main usage modes:
1. NO INPUT POWER, MODE = undefined: No input adapter or battery is detected. The charger and system are off. The battery is disconnected and the charger is off.
2. BATTERY-ONLY, MODE = any modes: Adapter is invalid and outside the input voltage operating range (QCHGIN = OFF). The battery is connected to power the SYS load (QBATT = ON).
3. NO CHARGE-BUCK, MODE = 0x04: Adapter is valid, buck supplies power to SYS. The battery is disconnected (QBATT = OFF) when SYS load is less than the power that buck can supply.
When SYS load is larger than the power that buck can supply, the battery is reconnected (QBATT = ON) and supplements extra SYS load.
4. CHARGE-BUCK, MODE = 0x05: Adapter is valid, buck supplies power to SYS, and charges battery with IBATT.
5. BATTERY-BOOST (FLASH), MODE = 0x09: OTG is inactive (QCHGIN = OFF). Battery is connected to support SYS and BYP loads (QBATT = ON), and charger is operating in boost mode (Boost = ON).
6. BATTERY-BOOST (OTG), MODE = 0x0A: OTG is active (QCHGIN = ON). Battery is connected to support SYS and OTG loads (QBATT = ON), and charger is operating in boost mode (Boost = ON).
The ICs utilize several charging states to safely and quickly charge batteries as shown in Figure 3. The figure shows an exaggerated view of a Li+/Li-Poly battery progressing through the following charge states when there is no system load and the die and battery are close to room temperature. It shows a complete charging state transition process with four states: prequalification, fast-charge, top-off, and done.
While in the “no input power or charger idle” state, the charge current is 0mA, the watchdog and charge timers are forced to 0, and the power to the system is provided by either the battery or the adapter. When both battery and adapter power is available, the adapter provides primary power to the system and the battery contributes supplemental energy to the system if necessary.
To exit the “no input power or charger idle” state, the charger input must be valid and the charger has to be enabled.
As shown in Figure 3, the precharge state occurs when the main-battery voltage is less than VPRECHG. After being in this state for tSCIDG, a CHG_I interrupt is generated only if CHG_OK was 0 previously, CHG_OK is set to 1, and CHG_DTLS is set to 0x00. In the precharge state, charge current into the battery is IPRECHG.
The following events cause the state machine to exit this state:
- Main battery voltage rises above VPRECHG and the charger enters the next state in the charging cycle: “Trickle Charge”.
- If the battery charger remains in this state for longer than tPQ, the charger state machine transitions to the “Timer Fault” state.
- If the watchdog timer is not serviced (see the Watchdog Timer section), the charger state machine transitions to the “Watchdog Suspend” state.
Note that the precharge state works with battery voltages down to 0V. The low 0V operation typically allows this battery charger to recover batteries that have an “open” internal pack protector. Typically a pack internal protection circuit opens if the battery has seen an overcurrent, undervoltage, or overvoltage. When a battery with an “open” internal pack protector is used with this charger, the precharge mode current flows into the 0V battery—this current raises the pack’s terminal voltage to the pointer where the internal pack protection switch closes.
Note that a normal battery typically stays in the precharge state for several minutes or less. Therefore a battery that stays in the precharge for longer than tPQ may be experiencing a problem.
As shown in Figure 3, the trickle charge state occurs when VBATT > VPRECHG and VBATT < VTRICKLE. After being in this state for tSCIDG, a CHG_I interrupt is generated only if CHG_OK was 0 previously, CHG_OK is set to 1, and CHG_DTLS = 0x00.
With TKEN = 1 and the IC is in its trickle charge state, the current in the battery is less than or equal to ITRICKLE. When TKEN = 0, the battery current is less than or equal to IFC.
Charge current may be less than ITRICKLE/IFC for any of the following reasons:
- The charger input is in input current limit
- The charger input voltage is low
- The charger is in thermal foldback
- The system load is consuming adapter current. Note that the system load always gets priority over the battery charge current.
Typical systems operate with TKEN = 1. When operating with TKEN = 0, the system’s software usually sets IFC to a low value such as 450mA and then monitors the battery voltage. When the battery exceeds a relatively low voltage such as 3.1V, then the system’s software usually increases IFC.
The following events cause the state machine to exit this state:
- When the main battery voltage rises above VTRICKLE or the PQEN bit is cleared, the charger enters the next state in the charging cycle: “Fast Charge (CC)”.
- If the battery charger remains in this state for longer than tPQ, the charger state machine transitions to the “Timer Fault” state.
- If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state.
Note that a normal battery typically stays in the trickle charge state for several minutes or less. Therefore a battery that stays in trickle charge for longer than tPQ may be experiencing a problem.
As shown in Figure 3, the fast-charge CC state occurs when the main-battery voltage is greater than the low-battery prequalification threshold and less than the battery regulation threshold (VTRICKLE < VBATT < VBATTREG). After being in the fast-charge CC state for tSCIDG, a CHG_I interrupt is generated only if CHG_OK was 0 previously, CHG_OK is set to 1, and CHG_DTLS = 0x01.
In the fast-charge CC state, the current into the battery is less than or equal to IFC. Charge current may be less than IFC for any of the following reasons:
- The charger input is in input current limit
- The charger input voltage is low
- The charger is in thermal foldback
- The system load is consuming adapter current. Note that the system load always gets priority over the battery charge current.
The following events causes the state machine to exit this state:
- When the main battery voltage rises above VBATTREG, the charger enters the next state in the charging cycle: “Fast Charge (CV)”.
- If the battery charger remains in this state for longer than tFC, the charger state machine transitions to the “Timer Fault” state.
- If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state.
The battery charger dissipates the most power in the fast-charge constant current state. This power dissipation causes the internal die temperature to rise. If the die temperature exceeds TREG, IFC is reduced. See the Thermal Foldback section for more information.
As shown in Figure 3, the fast-charge CV state occurs when the battery voltage rises to VBATTREG from the fast-charge CC state. After being in the fast-charge CV state for tSCIDG, a CHG_I interrupt is generated only if CHG_OK was 0 previously, CHG_OK is set to 1, and CHG_DTLS = 0x02.
In the fast-charge CV state, the battery charger maintains VBATTREG across the battery and the charge current is less than or equal to IFC. As shown in Figure 3, charger current decreases exponentially in this state as the battery becomes fully charged.
The smart power selector control circuitry may reduce the charge current lower than the battery may otherwise consume for any of the following reasons:
- The charger input is in input current limit
- The charger input voltage is low
- The charger is in thermal foldback
- The system load is consuming adapter current. Note that the system load always gets priority over the battery charge current.
The following events causes the state machine to exit this state:
- When the charger current is below ITO for tTERM, the charger enters the next state in the charging cycle: “TOP OFF” state.
- If the battery charger remains in this state for longer than tFC, the charger state machine transitions to the “Timer Fault” state.
- If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state.
As shown in Figure 3, the top-off state can only be entered from the fast-charge CV state when the charger current decreases below ITO for tTERM. After being in the top-off state for tSCIDG, a CHG_I interrupt is generated only if CHG_OK was 0 previously, CHG_OK is set to 1, and CHG_DTLS = 0x03. In the top-off state, the battery charger tries to maintain VBATTREG across the battery and typically the charge current is less than or equal to ITO.
The smart power selector control circuitry may reduce the charge current lower than the battery may otherwise consume for any of the following reasons:
- The charger input is in input current limit
- The charger input voltage is low
- The charger is in thermal foldback
- The system load is consuming adapter current. Note that the system load always gets priority over the battery charge current.
The following events cause the state machine to exit this state:
- After being in this state for the top-off time (tTO), the charger enters the next state in the charging cycle: “DONE” state.
- If VBATT < VBATTREG – VRSTRT, the charger goes back to the “FAST CHARGE (CC)” state.
- If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state.
As shown in Figure 3, the battery charger enters its done state after the charger has been in the top-off state for tTO. After being in this state for tSCIDG, a CHG_I interrupt is generated only if CHG_OK was 0 previously, CHG_OK is set to 0, and CHG_DTLS = 0x04.
The following events cause the state machine to exit this state:
- If VBATT < VBATTREG – VRSTRT, the charger goes back to the “FAST-CHARGE CC” state.
- If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state.
In the done state, the charge current into the battery (ICHG) is 0A. In the done state, the charger presents a very low load (IMBDN) to the battery. If the system load presented to the battery is low, then a typical system can remain in the done state for many days. If left in the done state long enough, the battery voltage decays below the restart threshold (VRSTRT), and the charger state machine transitions back into the fast-charge CV state. There is no soft-start (di/dt limiting) during the done to fast-charge state transition.
The battery charger provides both a charge timer and a watchdog timer to ensure safe charging. The charge timer prevents the battery from charging indefinitely. The time that the charger is allowed to remain in each of its prequalification states is tPQ. The time that the charger is allowed to remain in the fast-charge CC & CV states is tFC which is programmable with FCHGTIME. Finally, the time that the charger is in the top-off state is tTO which is programmable with TO_TIME. Upon entering the timer fault state a CHG_I interrupt is generated without a delay, CHG_OK is cleared, and CHG_DTLS = 0x06.
In the timer fault state, the charger is off. The charger can exit the timer fault state by programming the charger to be off and then programming it to be on again through the MODE bits. Alternatively, the charger input can be removed and re-inserted to exit the timer fault state.
The battery charger provides both a charge timer and a watchdog timer to ensure safe charging. The watchdog timer protects the battery from charging indefinitely if the host hangs or otherwise cannot communicate correctly. The watchdog timer is disabled by default with WDTEN = 0. To use the watchdog timer feature enable the feature by setting WDTEN. While enabled, the system controller must reset the watchdog timer within the timer period (tWD) for the charger to operate normally. Reset the watchdog timer by programming WDTCLR = 0x01.
If WD_QBATTOFF bit is set to 0 and the watchdog timer expires while the charger is in dead-battery prequalification, low-battery prequalification, fast-charge CC or CV, top-off, done, or timer fault, the charging stops, a CHG_I interrupt is generated only if CHG_OK was 1 previously, CHG_OK is cleared, and CHG_DTLS indicates that the charger is off because the watchdog timer expired. Once the watchdog timer has expired, the charger may be restarted by programming WDTCLR = 0x01. The SYS node can be supported by the battery and/or the adapter through the DC-DC buck while the watchdog timer is expired.
If WD_QBATTOFF bit is set to 1 and the watchdog timer expires, MAX77976 turns off the buck, charger, and QBATT switch for 150ms. And then VSYS voltage collapses and it resets all I2C registers. The IC restarts as initial power-up condition.
The thermal shutdown state occurs when the battery charger is in any state and the junction temperature (TJ) exceeds the device’s thermal-shutdown threshold (TSHDN). When TJ is close to TSHDN the charger folds back the charge current to 0A (see the Thermal Foldback section). Upon entering this state, CHG_I interrupt is generated if CHG_OK was 1 previously, CHG_OK is cleared, and CHG_DTLS = 0x0A.
In the thermal shutdown state, the charger is off. MODE register (CHG_CNFG_00[3:0] ) is reset to its default value as well as all O type registers.
DEBOUNCE TIME RISING | DEBOUNCE TIME FALLING | |
INTERRUPT | Typ (ms) | Typ (ms) |
AICL_I | 30 | 30 |
CHGIN_I | 7.5 | — |
INLIM_I | 30 | 30 |
BAT_I (Overvoltage TBATOV) | 7.5 | — |
BYP_I (TOTG_I) | 20 | — |
BYP_I (BST_ILIM) | 30 | — |
BYP_I (Buck Neg ILIM) | 0.5 | — |
Accuracy of the timer is defined by TACC.
BATSP and BATSN are differential remote sense lines for the main-battery. To improve accuracy and decrease charging times, the battery charger voltage sense is based on the differential voltage between BATSP and BATSN. Similarly, the thermistor voltage is interpreted with respect to BATSN.
A Maxim battery charger without the remote sensing function would typically measure the battery voltage between BATT and GND. In case a charge current of 1A measuring from BATT to GND leads to a VBATT that is 40mV higher than the real voltage because of RPAR1 and RPAR7 (ICHG x (RPAR1 + RPAR7) = 1A x 40mΩ = 40mV). Since the charger thinks the battery voltage is higher than it actually is, it enters its fast-charge CV state sooner and the effective charge time may be extended by 10 minutes (based on real lab measurements). This charger with differential remote sensing does not experience this type of problem because BATSP and BATSN sense the battery voltage directly. To get the maximum benefit from these sense lines, connect them as close as possible to the main-battery connector.
The DC-DC converter topology of the IC allows it to operate as a forward buck converter or as a reverse boost converter. The modes of the DC-DC converter are controlled with MODE. When MODE = 0x09 or 0x0A, the DC-DC converter operates in reverse boost mode allowing it to source current to BYP. To allow current flow to CHGIN, set MODE = 0x0A. This mode allows current to be sourced from CHGIN and is commonly referred to as OTG mode.
When MODE = 0x0A, the DC-DC converter operates in reverse boost mode and regulates VBYP to VBYP.OTG and the low ohmic (RCHGIN2BYP) switch from BYP to CHGIN is closed. The current through the BYP to CHGIN switch is limited to the value programmed by OTG_ILIM. The programmable OTG_ILIM options allow for supplying from 500mA to 3100mA to an external load. When the OTG mode is selected, the unipolar CHGIN transfer function measures the current going out of CHGIN. When OTG mode is not selected, the unipolar CHGIN transfer function measures current going into CHGIN.
If the external OTG load at CHGIN exceeds ICHGIN.OTG.ILIM current during a minimum time of TOTG_I ms, then a BYP_I interrupt is generated. BYP_OK = 0 and BYP_DTLS[0] = 1. In response to an overload at CHGIN during OTG mode operation, the BYP to CHGIN switch is latched off TOTG_fault after entering OTG_ILIM condition. If the overload at CHGIN persists, BYP_DTLS keeps continuing to report OTG_ILIM fault through BYP_DTLS[0] = 1.
If OTG_REC_EN bit = '1: other functions remain unaffected, i.e., BYP is supplied by reverse boost and the BYP to CHGIN switch automatically retries after TOTG_retry. If the overload at CHGIN persists, then the CHGIN switch toggles ON and OFF with TOTG_fault ON time and TOTG_retry OFF time.
If OTG_REC_EN bit = '0: the BYP to CHGIN switch remains off and the switcher is turned off until MODE is toggled.
BYP_I exit interrupt is only generated on OTG load release such as IOTG < ICHGIN.OTG.ILIM or FET opening. At that time, BYP_I interrupt is generated. BYP_OK = 1 and BYP_DTLS[0] = 0.
Note: On OTG_ILIM debounce time out, BYP_DTLS[0] is latched until the BYP_DTLS register is read by AP. BYP_OK is matching BYP_DTLS[0] behavior.
The IC is rated for a maximum discharge current of 10A. To protect against excessive battery discharge current, the IC must only be used with a battery pack with overcurrent protection circuit rated for 10A or less.
To protect the system from unexpected and critical events (e.g., excessive battery discharge current), the AP can control the MAX77975/MAX77976 QBATT switch by driving DISIBS bit to a logic-high.
There are different scenarios of how the IC responds to setting the DISIBS bit high depending on the available power source and the state of the charger:
1) The IC is only powered from BATT and DISIBS bit is set
a. QBATT switch opens
b. SYS collapses and is allowed to go to 0V
c. If RECYCLE_EN = 1, the IC self-recovers and restarts after tOCP_RETRY. If RECYCLE_EN = 0, after tOCP_RETRY, the IC does not recycle until a valid charger input is inserted.
2) The IC is powered from BATT, CHGIN is present, the charger buck is not switching, and DISIBS bit is set:
a. QBATT switch opens
b. SYS collapses and is allowed to go to 0V
a. Regardless of RECYCLE bit setting, the IC self-recovers and restarts after tOCP_RETRY.
3) The IC is powered from CHGIN, buck is switching, charge is OFF, and DISIBS bit is set:
a. QBATT stays OFF (opened)
b. Turn off Buck
c. SYS collapses and is allowed to go to 0V
d. Regardless of RECYCLE bit setting, the IC self-recovers and restarts after tOCP_RETRY.
4) The IC is powered from CHGIN, buck is switching, charge is ON, and DISIBS bit is set:
a. Charge is disabled
b. QBATT turns off (opened)
c. Turn off Buck
d. SYS collapses and is allowed to go to 0V
e. Regardless of RECYCLE bit setting, the IC self-recovers and restarts after tOCP_RETRY.
To protect the system from unexpected and critical events (e.g., excessive battery discharge current), the AP can control the ICs QBATT switch by driving the DISQBAT hardware pin. This pin can also be driven during factory test modes.
On DISQBAT low-to-high assertion, QBATT FET opens and any ongoing charge is disabled but buck keeps switching (if allowed by MODE setting).
The IC supports factory-boost mode to enter in boost mode (through CHG_CNFG_00.MODE setting) and keep QBATT OFF even if boost mode is set.
This functionality is only enabled once functional register CHG_CNFG_07.FMBST bit is set 1.
DISQBAT is an input control signal for QBATT FET with an external logic signal. If DISQBAT is driven by high, QBATT FET is truly disconnected. It has an internal 470kΩ pulldown resistor.
The ICs charger uses several thermal management techniques to prevent excessive battery and die temperatures.
Thermal foldback maximizes the battery charge current while regulating the ICs junction temperature. As shown in Figure 5, when the die temperature exceeds the value programmed by REGTEMP (TREG), a thermal limiting circuit reduces the battery charger’s target current by ATJREG. The target charge current reduction is achieved with an analog control loop (i.e., not a digital reduction in the input current). When the thermal foldback loop changes state, a CHG_I interrupt is generated and the system’s microprocessor may read the status of the thermal regulation loop through the TREG status bit. Note that the thermal foldback loop being active is not considered to be abnormal operation and the thermal foldback loop status does not affect the CHG_OK bit (only information contained within CHG_DTLS affects CHG_OK).
The thermistor input can be utilized to achieve functions such as, charge suspension, JEITA compliant charging, and battery removal detection. The thermistor monitoring feature can be disabled by connecting the THM pin to ground.
The THM input connects to an external negative temperature coefficient (NTC) thermistor to monitor battery or system temperature.
JEITA Compliant Charging
JEITA compliant charging is available with JEITA_EN = 1.
Charging stops when the thermistor temperature is out of range (T < TCOLD or T > THOT). The charge timers are reset and the CHG_DTLS[3:0], CHG_OK register bits report the charging suspension status, and CHG_I interrupt bit is set. When the thermistor comes back into range (TCOLD < T < THOT), charging resumes, and the charge timer restarts.
See the JEITA Controlled Charging section for more details.
Battery Removal Detection
With pullup connected between PVDD and THM, if battery is removed, the thermistor is disconnected from THM; this event is detected as THM is pulled up to PVDD. Battery removal event prevents charging.
Disable Thermistor Monitoring
Connecting THM to GND disables the thermistor monitoring function, and JEITA controlled charging is unavailable in this configuration. The IC detects an always-connected battery when THM is grounded, and charging starts automatically when a valid adapter is plugged in. In applications with removable batteries, do not connect THM to GND because the IC is not able to detect battery removal when THM is grounded. Instead, connecting THM to the thermistor pin in the battery pack is recommended.
Since the thermistor monitoring circuit employs an external bias resistor from THM to PVDD, the thermistor is not limited only to 10kΩ (at +25ºC). Any resistance thermistor can be used as long as the value is equivalent to the thermistors +25ºC resistance. For example, with a 10kΩ at RTB resistor, the charger enters a temperature suspend state when the thermistor resistance falls below 4.67kΩ (too hot) or rises above 30.3kΩ (too cold). This corresponds to 0ºC to +45ºC range when using a 10kΩ NTC thermistor with a beta of 3610. The general relation of thermistor resistance to temperature is defined by the following equation:
where:
RT = The resistance in Ω of the thermistor at temperature T in Celsius
R25= The resistance in Ω of the thermistor at +25ºC
β = The material constant of the thermistor, which typically ranges from 3000k to 5000k
T = The temperature of the thermistor in °C
Some designs might prefer other thermistor temperature limits. Threshold adjustment can be accommodated by changing RTB, connecting a resistor in series and/or in parallel with the thermistor, or using a thermistor with different β. For example, a +45ºC hot threshold and 0°C cold threshold can be realized by using a thermistor with a β to 4250 and connecting 120kΩ in parallel. Since the thermistor resistance near 0ºC is much higher than it is near +50ºC, a large parallel resistance lowers the cold threshold while only slightly lowering the hot threshold. Conversely, a small series resistance raises the cold threshold, while only slightly raising the hot threshold. Raising RTB, lowers both the hot and cold threshold, while lowering RTB raises both thresholds.
Thermistor bias current flows whenever PVDD is enabled (CHGIN valid or BOOST enabled). When using a 10kΩ thermistor and a 10kΩ pullup to THM, this results in an additional 90μA load. This load can be reduced to 9μA by instead using a 100kΩ thermistor and 100kΩ pullup resistor.
Thermistor | R25 (Ω) | 10000 | 10000 | 47000 | 100000 |
Thermistor Beta (β) | 3380 | 3610 | 4050 | 4250 | |
RTB (Ω) | 10000 | 10000 | 47000 | 100000 | |
R15 (Ω) | 14826 | 15223 | 75342 | 164083 | |
R45 (Ω) | 4900 | 4671 | 19993 | 40781 | |
Trip Temperatures | TCOLD (˚C) | -1.3 | 0.2 | 2.7 | 3.7 |
TCOOL (˚C) | 9.0 | 10.0 | 11.6 | 12.2 | |
TWARM (˚C) | 46.2 | 44.8 | 42.5 | 41.7 | |
THOT (˚C) | 62.5 | 59.8 | 55.6 | 54.1 |
The MAX77976 safely charges Li+ batteries in accordance with JEITA specifications. The IC monitors the battery temperature with an NTC thermistor connected at THM pin and automatically adjusts the fast-charge current and/or charge termination voltage as the battery temperature varies. JEITA controlled charging can be disabled by setting JEITA_EN to '0; if JEITA_EN = '0, thermistor input is not taken into account to determine charge state or charge current and voltage levels.
CHG_DTLS and THM_DTLS registers report JEITA controlled charging status.
The JEITA controlled fast-charging current (ICHGCC_JEITA) for TWARM < T < THOT is programmable with I2C bit CHG_CC_WARM.
The JEITA controlled charge termination voltage (VCHGCV_JEITA) for TCOLD < T < TCOOL is programmable with I2C bit CHG_CV_COOL.
The JEITA controlled fast-charging current for TCOLD < T < TCOOL is halved (to CHG_CC x 0.5) and the charge termination voltage for TWARM < T < THOT is reduced to (CHG_CV_PRM - 150mV), as shown in the Figure 6.
The JEITA controlled charging is suspended when the battery temperature is too cold or too hot (T < TCOLD or THOT < T).
Temperature thresholds TCOLD, TCOOL, TWARM, THOT depend on the thermistor selection. See the Thermistor Input (THM) section for more details.
When JEITA controlled battery charge current is reduced by 50%, the charger timer is doubled.
VDD is the 1.8V LDO output for the charger’s analog circuitry. VDD takes its power from the higher voltage of CHGIN, BATT, and SYS. VDD has a bypass capacitance of 1μF.
PVDD is the 1.8V LDO output for internal power circuitry. PVDD has a bypass capacitance of 1μF.
The ICs support factory-ship mode.
Charger's CHG_CNFG_07 bit 0: FSHIP_MODE bit controls this mode.
When this bit is set to 1, the IC goes into factory-ship mode.
This mode can be exited by battery removal or on a valid charger input plug or by pulling EXTSM high longer than tEXTSM_DEB (programmable with EXTSM_T bit).
Factory-ship mode can not be entered when a valid charger is present.
This feature minimizes battery leakage current when factory ships battery connected devices.
QBEXT is an open-drain output that is driven low in Battery mode and high-impedance (pulled-up externally) in non-battery mode.
The QBATT in MAX77976 has a very low RDSON that equals to 8.5mΩ. If the application requires a lower resistive discharging path then this output can be utilized to drive an external QBATT FET driver in parallel with internal QBATT. This output can be enabled or disabled by the QBEXT_CTRL bit.
SYSTEM MODE | USE CASE DETAILS | QBEXT OUTPUT |
Battery Mode | All use cases except non-battery mode | Low |
Non-Battery Mode | Valid adapter is present, and buck is switching (whatever charge status is) or MODE = 0x09 (Boost) or MODE = 0x0A (Boost + OTG) |
Hi-Z (pulled-up) |
STAT is the LED current sink shown in the following tables based on the STAT_MODE bit.
The LED driving current can be programmed through I2C STAT_CURR from 5mA to 20mA with a 5mA step.
CHG STATUS | LED | DUTY (%) |
No DC input or Suspend or Buck operation | Off | 0 |
Any Charging Timeout, Off by JEITA feature, Off by thermal shutdown | Blink in 2Hz | 50 |
DBAT, Pre-Q, CC, CV | Blink in 1Hz | 50 |
Top-off, Done, Restart | Solid on | 100 |
CHG STATUS | LED | DUTY (%) |
No DC input or Suspend or Buck operation | Off | 0 |
Any Charging Timeout, Off by JEITA feature, Off by thermal shutdown | Off | 0 |
DBAT, Pre-Q, CC, CV | Blink in 1Hz | 50 |
Top-off, Done, Restart | Solid on | 100 |
In USB Type-C compatible applications, the output slew rate of the travel adaptor when changing output levels is defined by the USB Type-C spec to be within 30mV/μs. However, non-compliant USB adapters or high fixed voltage sources ≥ 15V can cause high inrush current during a hot plug event. The amount of inrush current that can flow through the IC is defined by the following equation:
- I_inrush = dVIN/dt x C_BYP
With the recommended 2 x 10μF 0805 package capacitance at BYP node (effective capacitance of 4μF at 12V), the max inrush current can be as high as 4A if dVIN/dt is within 1V/μs. During this rising edge, the QCHGIN FET is off, so all the current goes through the body diode. To prevent damaging the IC when the application uses a voltage source that is already "hot" when connected, or with a high input slew rate, connect an external Schottky diode with anode at CHGIN and cathode at BYP. The Schottky diode must be selected as follows:
- Calculate I_inrush with dVIN/dt information and assume C_BYP = 4μF
- Select the Shottky so that when forward voltage at room temperature is 0.45V, the current is less than I_inrush x 1.5
Example: 1V/μs max slew rate, I_inrush = 4A. The Schottky is chosen to be rated at least 6A at 0.45V.
This section discusses the top system of the MAX77975/MAX77976 and how the IC manages its bias, system faults, and turn-on and off events.
The main bias includes voltage and current references for all circuitry that runs from the VSYS node.
VSYS Fault
The system monitors the VSYS node for undervoltage and overvoltage events. The following describes the IC behavior if any of these events is to occur.
VSYS Undervoltage Lockout (VSYSUVLO)
VSYS undervoltage lockout prevents the regulators from being used when the input voltage is below the operating range. When the voltage from SYS to GND (VSYS) is less than the undervoltage-lockout threshold (VSYSUVLO), MAX77975/MAX77976 shuts down and resets "O" Type I2C registers.
VSYS Overvoltage Lockout (VSYSOVLO)
VSYS overvoltage lockout is a fail-safe mechanism and prevents the regulators from being used when the input voltage is above the operating range. The absolute maximum ratings state that the SYS node withstands up to 6V. The SYS OVLO threshold is set to 5.35V (typ)—ideally VSYS should not exceed the battery charge termination threshold. Systems must be designed such that VSYS never exceeds 5.2V (transient and steady-state). If the VSYS exceeds VSYS_OVLO_R, the ICs shuts down and resets "O" Type I2C registers.
VSYS Power-Up Failure (PWRUPFAIL)
VSYS power-up failure is a hardware diagnostic mechanism to detect failures affecting the system and preventing the platform from powering up. When a valid power source (battery VBATT > SYS_UVLOB_R or charger with VCHGIN > VCHGIN_UVLO_R) is plugged, MAX77975/MAX77976 is expected to pull SYS node up by means of one of the system power-up current sources (ISYSPU_BAT or ISYSPU_BYP respectively). If VSYS does not rise above VSYSPU due to a fault in the application (external to MAX77976), after a time-out elapses (tSYSPU_BAT or tSYSPU_BYP respectively) a power-up fault is asserted and an interrupt (PWRUP_FAIL_INT) is generated. Because the SYS node is down, the application software may not be able to service the interrupt; the interrupt can only be observed by pulling VIO up externally and serviced by taking control of the I2C interface.
Thermal Fault
The ICs have one centralized thermal circuit which senses temperature on the die. If temperature increases >155°C (TSHDN) this constitutes a thermal shutdown event and the MAX77976 shuts down and resets "O" Type I2C registers. There is a 15°C thermal hysteresis. After thermal shutdown, if the die temperature is reduced by 15°C, the thermal shutdown bus is deasserted and the IC can be enabled again. The main battery charger has an independent thermal control loop which does not cause a thermal shutdown event. In the event that a charger thermal overload occurs, only the charger turns off.
Applicable in charge or buck mode.
EDGE TO I/T | I/T TO FAULT | ACTION ON FAULT | |||
tDEB (Rising) | tDEB (Falling) | tDEB (Rising) | tDEB (Falling) | ||
SYS UVLO | — | — | 8ms | — | O-Type reset |
SYS OVLO | *-/100μs by I2C | — | — | — | O-Type reset |
TSHDN | 175μs | — | — | — | O-Type reset |
OTG OCP | tOTG_ALARM | — | tOTG_FAULT - tOTG_ALARM | — | RBFET opens |
(*) depending on I2C bit SYSOVLO_DEB_EN
Main I2C Interface
The IC acts as a Slave Transmitter/Receiver and has the following slave addresses:
Slave Address (7 bit) 0x6B 110 1011
Slave Address (Write) 0xD6 1101 0110
Slave Address (Read) 0xD7 1101 0111
I2C Bit Transfer
One data bit is transferred for each clock pulse. The data on SDA must remain stable during the high portion of the clock pulse as changes in data during this time are interpreted as a control signal.
I2C Start and Stop Conditions
Both SDA and SCL remain High when the bus is not busy. The Start (S) condition is defined as a high-to-low transition of the SDA while the SCL is high. The Stop (P) condition is defined as a low-to-high transition of the SDA while the SCL is high.
I2C System Configuration
A device on the I2C bus that generates a “message” is called a “Transmitter” and a device that receives the message is a “Receiver”. The device that controls the message is the “Master” and the devices that are controlled by the “Master” are called “Slaves”.
I2C Acknowledge
The number of data bytes between the start and stop conditions for the Transmitter and Receiver are unlimited.
Each 8-bit byte is followed by an Acknowledge bit. The Acknowledge bit is a high level signal put on SDA by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after each byte it receives. Also a master receiver must generate an acknowledge after each byte it receives that has been clocked out of the slave transmitter.
The device that acknowledges must pulldown the SDA line during the acknowledge-clock pulse, so that the SDA line is stable and low during the high period of the acknowledge-clock pulse (setup and hold times must also be met). A master receiver must signal the end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave SDA high to enable the master to generate a stop condition.
Master Transmits (Write Mode)
Use the following format when the master writes to the slave.
Master Reads after Setting Register Address (Write Register Address and Read Data)
Use the following format to read a specific register.
Master Reads Register Data Without Setting Register Address (Read Mode)
Use the following format to read registers continuously starting from first address.