Application Circuits
Typical Application Circuits
Wide-Input I
2
C Programmable Charger
Buck-Boost Charger Input. CHGIN is also the buck output when the charger is operating in the reverse mode. Bypass with two 10μF/35V ceramic capacitors from CHGIN to PGND.
CHGIN
CHGIN
VSYS
V
SYS
System Supply Output. Bypass SYS to PGND with two 47µF/25V ceramic capacitors.
SYS
SYS
PK+
PK+
PK-
PK-
Battery Power Connection. Connect to the positive terminal of the battery pack. Bypass BATT to PGND with a 10μF/25V capacitor. All BATT pins must be connected together externally.
BATT
BATT
Battery Voltage Differential Sense Negative Input. Connect to the negative terminal of the battery pack.
BATSN
BATSN
Power Ground for Buck-Boost Low-Side MOSFETs
PGND
PGND
High-Side Input MOSFET Driver Supply. Bypass BST1 to LX1 with a 0.22μF/6.3V capacitor.
BST1
BST1
Serial Interface I2C Clock Input
SCL
SCL
Serial Interface I2C Data. Open-drain output.
SDA
SDA
Active-Low Open-Drain Interrupt Output. Connect a pullup resistor to the pullup power source.
INTB
INTB
Thermistor Input. Connect a negative temperature coefficient (NTC) thermistor from THM to GND. Connect a resistor equal to the thermistor +25°C resistance from THM to AVL. JEITA-controlled charging available with JEITA_EN = 1. Charging is suspended when the thermistor voltage is outside of the hot and cold limits. Connect THM to GND to disable the thermistor temperature sensor. Connect THM to AVL to emulate battery removal and prevent charging.
THM
THM
10K
10k
Ω
Input Current-Sense Negative Input
CSINN
CSINN
Input Current-Sense Positive Input
CSINP
CSINP
SYS Voltage Sensing Input for SYS UVLO and OVLO Detection
SYSA
SYSA
2.2µH 8A ISAT
2.2µH
8A I
SAT
47µF 25V 1210
47µF
16V
1210
47µF 25V 1210
47µF
16V
1210
10µF 25V 0603
10µF
16V
0805
Thermistor Input. Connect a negative temperature coefficient (NTC) thermistor from THM to GND. Connect a resistor equal to the thermistor +25°C resistance from THM to AVL. JEITA-controlled charging available with JEITA_EN = 1. Charging is suspended when the thermistor voltage is outside of the hot and cold limits. Connect THM to GND to disable the thermistor temperature sensor. Connect THM to AVL to emulate battery removal and prevent charging.
THM
THM
VBATT
V
BATT
Analog Ground
GND
GND
Input Power-OK/OTG Power-OK Output. Active-low, open-drain output pulls low when the CHGIN voltage is valid.
INOKB
INOKB
200KΩ 0201
200k
Ω
0402
Charger Status Output. Active-low, open-drain output, connect to the pullup through a 10kΩ resistor. Pulls low when the charging is in progress. Otherwise, STAT is high impedance. STAT toggles between low and high (when connected to a pullup rail) during charge. STAT becomes low when top-off threshold is detected and charger enters the done state. STAT becomes high (when connected to a pullup rail) when charge faults are detected.
STAT
STAT
Battery Voltage Differential Sense Positive Input. Connect to the positive terminal of the battery pack.
BATSP
BATSP
Inductor Connection One. Connect an inductor between LX1 and LX2.
LX1
LX1
0.22µF 6.3V/0402
0.22µF
6.3V
0402
High-Side Output MOSFET Driver Supply. Bypass BST2 to LX2 with a 0.22μF/6.3V capacitor.
BST2
BST2
Inductor Connection Two. Connect an inductor between LX1 and LX2.
LX2
LX2
0.22µF 6.3V/0402
0.22µF
6.3V
0402
Active-High Input. Connect the OTGEN pin to high enables the OTG function. When OTGEN pin is pulled low, the OTG enable function is controlled by I2C. To pull the OTGEN pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
OTGEN
OTGEN
Top-Off Current Setting Input. Connect a resistor (RITO) from ITO to GND programs the top-off current. See Table 7.
ITO
ITO
Active-High Input. Connect high to disable the integrated QBAT FET between SYS and BATT. Charging is disabled when DISQBAT connects to high. When DISQBAT is pulled low, QBAT FET control is defined in the QBAT and DC-DC Control—Configuration Table. To pull the DISQBAT pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
DISQBAT
DISQBAT
Fast-Charge Current Setting Input. Connect a resistor (RISET) from ISET to GND programs the fast charge current. See Table 6.
ISET
ISET
Charger Input Current Limit Setting Input. Connect a resistor (RINLIM) from INLIM to GND programs the charger input current limit. Refer to Table 5.
INLIM
INLIM
Active-High Input. Connect high to disable the DC-DC between CHGIN input and SYS output. Battery supplies the system power if the QBAT is on. See Table 2. Connect low to control the DC-DC with the power-path state machine. To pull the STBY pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
STBY
STBY
Charge Termination Voltage Setting Input. Connect a resistor (RVSET) from VSET to GND programs the charge termination voltage. See Table 8.
VSET
VSET
Device Configuration Input. Connect a resistor (RCNFG) from CNFG to GND to program the following parameter, see Table 1. Number of battery cells in series connection (2S or 3S)
CNFG
CNFG
Internal Bias Regulator High Current Output Bypass. Supports internal noisy and high current gate drive loads. Bypass to GND with a minimum 4.7μF/6.3V ceramic capacitor, and connect AVL to PVL with a 4.7Ω resistor. Powering external loads from PVL is not recommended, other than pullup resistors.
PVL
PVL
Analog Voltage Supply for On-Chip, Low-Noise Circuits. Bypass with a 4.7μF/6.3V ceramic capacitor to GND and connect AVL to PVL with a 4.7Ω resistor.
AVL
AVL
VPVL
V
PVL
4.7µF 6.3V 0402
4.7µF
6.3V
0402
4.7µF 6.3V 0402
4.7µF
6.3V
0402
10Ω 0201
4.7
Ω
0402
Active-High Input. Connect the OTGEN pin to high enables the OTG function. When OTGEN pin is pulled low, the OTG enable function is controlled by I2C. To pull the OTGEN pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
OTGEN
OTGEN
Active-High Input. Connect high to disable the DC-DC between CHGIN input and SYS output. Battery supplies the system power if the QBAT is on. See Table 2. Connect low to control the DC-DC with the power-path state machine. To pull the STBY pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
STBY
STBY
Active-High Input. Connect high to disable the integrated QBAT FET between SYS and BATT. Charging is disabled when DISQBAT connects to high. When DISQBAT is pulled low, QBAT FET control is defined in the QBAT and DC-DC Control—Configuration Table. To pull the DISQBAT pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
DISQBAT
DISQBAT
VPVL
V
PVL
Charger Status Output. Active-low, open-drain output, connect to the pullup through a 10kΩ resistor. Pulls low when the charging is in progress. Otherwise, STAT is high impedance. STAT toggles between low and high (when connected to a pullup rail) during charge. STAT becomes low when top-off threshold is detected and charger enters the done state. STAT becomes high (when connected to a pullup rail) when charge faults are detected.
STAT
STAT
Input Power-OK/OTG Power-OK Output. Active-low, open-drain output pulls low when the CHGIN voltage is valid.
INOKB
INOKB
VAVL
V
AVL
Serial Interface I2C Clock Input
SCL
SCL
Active-Low Open-Drain Interrupt Output. Connect a pullup resistor to the pullup power source.
INTB
INTB
Serial Interface I2C Data. Open-drain output.
SDA
SDA
VPVL
V
PVL
3.5V to 24V
3.5V TO 25.4V
10µF 35V 1206
10µF
35V
1210
10mΩ 1206
10m
Ω
1206
VBUS
V
BUS
2/3-CELL LI-ION BATTERY
2/3-CELL LI-ION
BATTERY
MAX77960 MAX77961
MAX77960
MAX77961
200KΩ 0201
200k
Ω
0402
VAVL
V
AVL
47µF 25V 1210
3A I
F
INRUSH PROTECTION CIRCUIT (FOR 3S BATTERY)
INRUSH
PROTECTION
CIRCUIT
(FOR 3S BATTERY)
Wide-Input I
2
C Programmable Charger with Charger Disabled
Buck-Boost Charger Input. CHGIN is also the buck output when the charger is operating in the reverse mode. Bypass with two 10μF/35V ceramic capacitors from CHGIN to PGND.
CHGIN
CHGIN
VSYS
V
SYS
System Supply Output. Bypass SYS to PGND with two 47µF/25V ceramic capacitors.
SYS
SYS
PK+
PK+
PK-
PK-
Battery Power Connection. Connect to the positive terminal of the battery pack. Bypass BATT to PGND with a 10μF/25V capacitor. All BATT pins must be connected together externally.
BATT
BATT
Battery Voltage Differential Sense Negative Input. Connect to the negative terminal of the battery pack.
BATSN
BATSN
Power Ground for Buck-Boost Low-Side MOSFETs
PGND
PGND
High-Side Input MOSFET Driver Supply. Bypass BST1 to LX1 with a 0.22μF/6.3V capacitor.
BST1
BST1
Serial Interface I2C Clock Input
SCL
SCL
Serial Interface I2C Data. Open-drain output.
SDA
SDA
Active-Low Open-Drain Interrupt Output. Connect a pullup resistor to the pullup power source.
INTB
INTB
Thermistor Input. Connect a negative temperature coefficient (NTC) thermistor from THM to GND. Connect a resistor equal to the thermistor +25°C resistance from THM to AVL. JEITA-controlled charging available with JEITA_EN = 1. Charging is suspended when the thermistor voltage is outside of the hot and cold limits. Connect THM to GND to disable the thermistor temperature sensor. Connect THM to AVL to emulate battery removal and prevent charging.
THM
THM
10K
10k
Ω
Input Current-Sense Negative Input
CSINN
CSINN
Input Current-Sense Positive Input
CSINP
CSINP
SYS Voltage Sensing Input for SYS UVLO and OVLO Detection
SYSA
SYSA
2.2µH 8A ISAT
2.2µH
8A I
SAT
47µF 25V 1210
47µF
16V
1210
47µF 25V 1210
47µF
16V
1210
10µF 25V 0603
10µF
16V
0805
Thermistor Input. Connect a negative temperature coefficient (NTC) thermistor from THM to GND. Connect a resistor equal to the thermistor +25°C resistance from THM to AVL. JEITA-controlled charging available with JEITA_EN = 1. Charging is suspended when the thermistor voltage is outside of the hot and cold limits. Connect THM to GND to disable the thermistor temperature sensor. Connect THM to AVL to emulate battery removal and prevent charging.
THM
THM
VBATT
V
BATT
Analog Ground
GND
GND
Input Power-OK/OTG Power-OK Output. Active-low, open-drain output pulls low when the CHGIN voltage is valid.
INOKB
INOKB
200KΩ 0201
200k
Ω
0402
Charger Status Output. Active-low, open-drain output, connect to the pullup through a 10kΩ resistor. Pulls low when the charging is in progress. Otherwise, STAT is high impedance. STAT toggles between low and high (when connected to a pullup rail) during charge. STAT becomes low when top-off threshold is detected and charger enters the done state. STAT becomes high (when connected to a pullup rail) when charge faults are detected.
STAT
STAT
Battery Voltage Differential Sense Positive Input. Connect to the positive terminal of the battery pack.
BATSP
BATSP
Inductor Connection One. Connect an inductor between LX1 and LX2.
LX1
LX1
0.22µF 6.3V/0402
0.22µF
6.3V
0402
High-Side Output MOSFET Driver Supply. Bypass BST2 to LX2 with a 0.22μF/6.3V capacitor.
BST2
BST2
Inductor Connection Two. Connect an inductor between LX1 and LX2.
LX2
LX2
0.22µF 6.3V/0402
0.22µF
6.3V
0402
Active-High Input. Connect the OTGEN pin to high enables the OTG function. When OTGEN pin is pulled low, the OTG enable function is controlled by I2C. To pull the OTGEN pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
OTGEN
OTGEN
Top-Off Current Setting Input. Connect a resistor (RITO) from ITO to GND programs the top-off current. See Table 7.
ITO
ITO
Active-High Input. Connect high to disable the integrated QBAT FET between SYS and BATT. Charging is disabled when DISQBAT connects to high. When DISQBAT is pulled low, QBAT FET control is defined in the QBAT and DC-DC Control—Configuration Table. To pull the DISQBAT pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
DISQBAT
DISQBAT
Fast-Charge Current Setting Input. Connect a resistor (RISET) from ISET to GND programs the fast charge current. See Table 6.
ISET
ISET
Charger Input Current Limit Setting Input. Connect a resistor (RINLIM) from INLIM to GND programs the charger input current limit. Refer to Table 5.
INLIM
INLIM
Active-High Input. Connect high to disable the DC-DC between CHGIN input and SYS output. Battery supplies the system power if the QBAT is on. See Table 2. Connect low to control the DC-DC with the power-path state machine. To pull the STBY pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
STBY
STBY
Charge Termination Voltage Setting Input. Connect a resistor (RVSET) from VSET to GND programs the charge termination voltage. See Table 8.
VSET
VSET
Device Configuration Input. Connect a resistor (RCNFG) from CNFG to GND to program the following parameter, see Table 1. Number of battery cells in series connection (2S or 3S)
CNFG
CNFG
Internal Bias Regulator High Current Output Bypass. Supports internal noisy and high current gate drive loads. Bypass to GND with a minimum 4.7μF/6.3V ceramic capacitor, and connect AVL to PVL with a 4.7Ω resistor. Powering external loads from PVL is not recommended, other than pullup resistors.
PVL
PVL
Analog Voltage Supply for On-Chip, Low-Noise Circuits. Bypass with a 4.7μF/6.3V ceramic capacitor to GND and connect AVL to PVL with a 4.7Ω resistor.
AVL
AVL
VPVL
V
PVL
4.7µF 6.3V 0402
4.7µF
6.3V
0402
4.7µF 6.3V 0402
4.7µF
6.3V
0402
10Ω 0201
4.7
Ω
0402
Active-High Input. Connect the OTGEN pin to high enables the OTG function. When OTGEN pin is pulled low, the OTG enable function is controlled by I2C. To pull the OTGEN pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
OTGEN
OTGEN
Active-High Input. Connect high to disable the DC-DC between CHGIN input and SYS output. Battery supplies the system power if the QBAT is on. See Table 2. Connect low to control the DC-DC with the power-path state machine. To pull the STBY pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
STBY
STBY
Active-High Input. Connect high to disable the integrated QBAT FET between SYS and BATT. Charging is disabled when DISQBAT connects to high. When DISQBAT is pulled low, QBAT FET control is defined in the QBAT and DC-DC Control—Configuration Table. To pull the DISQBAT pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
DISQBAT
DISQBAT
VPVL
V
PVL
Charger Status Output. Active-low, open-drain output, connect to the pullup through a 10kΩ resistor. Pulls low when the charging is in progress. Otherwise, STAT is high impedance. STAT toggles between low and high (when connected to a pullup rail) during charge. STAT becomes low when top-off threshold is detected and charger enters the done state. STAT becomes high (when connected to a pullup rail) when charge faults are detected.
STAT
STAT
Input Power-OK/OTG Power-OK Output. Active-low, open-drain output pulls low when the CHGIN voltage is valid.
INOKB
INOKB
VAVL
V
AVL
Serial Interface I2C Clock Input
SCL
SCL
Active-Low Open-Drain Interrupt Output. Connect a pullup resistor to the pullup power source.
INTB
INTB
Serial Interface I2C Data. Open-drain output.
SDA
SDA
VPVL
V
PVL
3.5V to 24V
3.5V TO 25.4V
10µF 35V 1206
10µF
35V
1210
10mΩ 1206
10m
Ω
1206
VBUS
V
BUS
2/3-CELL LI-ION BATTERY
2/3-CELL LI-ION
BATTERY
MAX77960 MAX77961
MAX77960
MAX77961
200KΩ 0201
200k
Ω
0402
VAVL
V
AVL
INRUSH PROTECTION CIRCUIT (FOR 3S BATTERY)
INRUSH
PROTECTION
CIRCUIT
(FOR 3S BATTERY)
47µF 25V 1210
3A I
F
Wide-Input Autonomous Charger
Buck-Boost Charger Input. CHGIN is also the buck output when the charger is operating in the reverse mode. Bypass with two 10μF/35V ceramic capacitors from CHGIN to PGND.
CHGIN
CHGIN
VSYS
V
SYS
System Supply Output. Bypass SYS to PGND with two 47µF/25V ceramic capacitors.
SYS
SYS
PK+
PK+
PK-
PK-
Battery Power Connection. Connect to the positive terminal of the battery pack. Bypass BATT to PGND with a 10μF/25V capacitor. All BATT pins must be connected together externally.
BATT
BATT
Battery Voltage Differential Sense Negative Input. Connect to the negative terminal of the battery pack.
BATSN
BATSN
Power Ground for Buck-Boost Low-Side MOSFETs
PGND
PGND
High-Side Input MOSFET Driver Supply. Bypass BST1 to LX1 with a 0.22μF/6.3V capacitor.
BST1
BST1
Serial Interface I2C Clock Input
SCL
SCL
Serial Interface I2C Data. Open-drain output.
SDA
SDA
Active-Low Open-Drain Interrupt Output. Connect a pullup resistor to the pullup power source.
INTB
INTB
Thermistor Input. Connect a negative temperature coefficient (NTC) thermistor from THM to GND. Connect a resistor equal to the thermistor +25°C resistance from THM to AVL. JEITA-controlled charging available with JEITA_EN = 1. Charging is suspended when the thermistor voltage is outside of the hot and cold limits. Connect THM to GND to disable the thermistor temperature sensor. Connect THM to AVL to emulate battery removal and prevent charging.
THM
THM
10K
10k
Ω
Input Current-Sense Negative Input
CSINN
CSINN
Input Current-Sense Positive Input
CSINP
CSINP
3.5V to 24V
3.5V TO 25.4V
SYS Voltage Sensing Input for SYS UVLO and OVLO Detection
SYSA
SYSA
2.2µH 8A ISAT
2.2µH
8A I
SAT
47µF 25V 1210
47µF
16V
1210
47µF 25V 1210
47µF
16V
1210
10µF 25V 0603
10µF
16V
0805
Thermistor Input. Connect a negative temperature coefficient (NTC) thermistor from THM to GND. Connect a resistor equal to the thermistor +25°C resistance from THM to AVL. JEITA-controlled charging available with JEITA_EN = 1. Charging is suspended when the thermistor voltage is outside of the hot and cold limits. Connect THM to GND to disable the thermistor temperature sensor. Connect THM to AVL to emulate battery removal and prevent charging.
THM
THM
VBATT
V
BATT
Analog Ground
GND
GND
10µF 35V 1206
10µF
35V
1210
Input Power-OK/OTG Power-OK Output. Active-low, open-drain output pulls low when the CHGIN voltage is valid.
INOKB
INOKB
200KΩ 0201
200k
Ω
0402
Charger Status Output. Active-low, open-drain output, connect to the pullup through a 10kΩ resistor. Pulls low when the charging is in progress. Otherwise, STAT is high impedance. STAT toggles between low and high (when connected to a pullup rail) during charge. STAT becomes low when top-off threshold is detected and charger enters the done state. STAT becomes high (when connected to a pullup rail) when charge faults are detected.
STAT
STAT
2/3-CELL LI-ION BATTERY
2/3-CELL LI-ION
BATTERY
Battery Voltage Differential Sense Positive Input. Connect to the positive terminal of the battery pack.
BATSP
BATSP
10mΩ 1206
10m
Ω
1206
VBUS
V
BUS
Inductor Connection One. Connect an inductor between LX1 and LX2.
LX1
LX1
0.22µF 6.3V/0402
0.22µF
6.3V
0402
High-Side Output MOSFET Driver Supply. Bypass BST2 to LX2 with a 0.22μF/6.3V capacitor.
BST2
BST2
Inductor Connection Two. Connect an inductor between LX1 and LX2.
LX2
LX2
0.22µF 6.3V/0402
0.22µF
6.3V
0402
Active-High Input. Connect the OTGEN pin to high enables the OTG function. When OTGEN pin is pulled low, the OTG enable function is controlled by I2C. To pull the OTGEN pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
OTGEN
OTGEN
Top-Off Current Setting Input. Connect a resistor (RITO) from ITO to GND programs the top-off current. See Table 7.
ITO
ITO
Active-High Input. Connect high to disable the integrated QBAT FET between SYS and BATT. Charging is disabled when DISQBAT connects to high. When DISQBAT is pulled low, QBAT FET control is defined in the QBAT and DC-DC Control—Configuration Table. To pull the DISQBAT pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
DISQBAT
DISQBAT
Fast-Charge Current Setting Input. Connect a resistor (RISET) from ISET to GND programs the fast charge current. See Table 6.
ISET
ISET
Charger Input Current Limit Setting Input. Connect a resistor (RINLIM) from INLIM to GND programs the charger input current limit. Refer to Table 5.
INLIM
INLIM
Active-High Input. Connect high to disable the DC-DC between CHGIN input and SYS output. Battery supplies the system power if the QBAT is on. See Table 2. Connect low to control the DC-DC with the power-path state machine. To pull the STBY pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
STBY
STBY
Charge Termination Voltage Setting Input. Connect a resistor (RVSET) from VSET to GND programs the charge termination voltage. See Table 8.
VSET
VSET
Device Configuration Input. Connect a resistor (RCNFG) from CNFG to GND to program the following parameter, see Table 1. Number of battery cells in series connection (2S or 3S)
CNFG
CNFG
Internal Bias Regulator High Current Output Bypass. Supports internal noisy and high current gate drive loads. Bypass to GND with a minimum 4.7μF/6.3V ceramic capacitor, and connect AVL to PVL with a 4.7Ω resistor. Powering external loads from PVL is not recommended, other than pullup resistors.
PVL
PVL
Analog Voltage Supply for On-Chip, Low-Noise Circuits. Bypass with a 4.7μF/6.3V ceramic capacitor to GND and connect AVL to PVL with a 4.7Ω resistor.
AVL
AVL
VPVL
V
PVL
4.7µF 6.3V 0402
4.7µF
6.3V
0402
4.7µF 6.3V 0402
4.7µF
6.3V
0402
10Ω 0201
4.7Ω
0402
Active-High Input. Connect the OTGEN pin to high enables the OTG function. When OTGEN pin is pulled low, the OTG enable function is controlled by I2C. To pull the OTGEN pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
OTGEN
OTGEN
Active-High Input. Connect high to disable the DC-DC between CHGIN input and SYS output. Battery supplies the system power if the QBAT is on. See Table 2. Connect low to control the DC-DC with the power-path state machine. To pull the STBY pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
STBY
STBY
Active-High Input. Connect high to disable the integrated QBAT FET between SYS and BATT. Charging is disabled when DISQBAT connects to high. When DISQBAT is pulled low, QBAT FET control is defined in the QBAT and DC-DC Control—Configuration Table. To pull the DISQBAT pin low with a pulldown resistor, the resistance must be lower than 44kΩ.
DISQBAT
DISQBAT
VPVL
V
PVL
Charger Status Output. Active-low, open-drain output, connect to the pullup through a 10kΩ resistor. Pulls low when the charging is in progress. Otherwise, STAT is high impedance. STAT toggles between low and high (when connected to a pullup rail) during charge. STAT becomes low when top-off threshold is detected and charger enters the done state. STAT becomes high (when connected to a pullup rail) when charge faults are detected.
STAT
STAT
Input Power-OK/OTG Power-OK Output. Active-low, open-drain output pulls low when the CHGIN voltage is valid.
INOKB
INOKB
VAVL
V
AVL
MAX77960 MAX77961
MAX77960
MAX77961
200KΩ 0201
200k
Ω
0402
VAVL
V
AVL
47µF 25V 1210
3A I
F
INRUSH PROTECTION CIRCUIT (FOR 3S BATTERY)
INRUSH
PROTECTION
CIRCUIT
(FOR 3S BATTERY)
