| PIN | NAME | FUNCTION |
| 1 | BST1 | High-Side Input MOSFET Driver Supply. Bypass BST1 to LX1 with a 0.22μF/6.3V capacitor. |
| 2 | CHGIN | Buck-Boost Charger Input. CHGIN is also the buck output when the charger is operating in the reverse mode. Bypass with two 10μF/35V ceramic capacitors from CHGIN to PGND. |
| 3 | LX1 | Inductor Connection One. Connect an inductor between LX1 and LX2. |
| 4 | PGND | Power Ground for Buck-Boost Low-Side MOSFETs |
| 5 | LX2 | Inductor Connection Two. Connect an inductor between LX1 and LX2. |
| 6 | SYS | System Supply Output. Bypass SYS to PGND with two 47µF/25V ceramic capacitors. |
| 7 | OTGEN | Active-High Input. Connect the OTGEN pin to high enables the OTG function. When OTGEN pin is pulled low, the OTG enable function is controlled by I2C. To pull the OTGEN pin low with a pulldown resistor, the resistance must be lower than 44kΩ. |
| 8 | DISQBAT | Active-High Input. Connect high to disable the integrated QBAT FET between SYS and BATT. Charging is disabled when DISQBAT connects to high. When DISQBAT is pulled low, QBAT FET control is defined in the QBAT and DC-DC Control—Configuration Table. To pull the DISQBAT pin low with a pulldown resistor, the resistance must be lower than 44kΩ. |
| 9 | BST2 | High-Side Output MOSFET Driver Supply. Bypass BST2 to LX2 with a 0.22μF/6.3V capacitor. |
| 10 | BATSN | Battery Voltage Differential Sense Negative Input. Connect to the negative terminal of the battery pack. |
| 11 | BATSP | Battery Voltage Differential Sense Positive Input. Connect to the positive terminal of the battery pack. |
| 12 | BATT | Battery Power Connection. Connect to the positive terminal of the battery pack. Bypass BATT to PGND with a 10μF/25V capacitor. All BATT pins must be connected together externally. |
| 13 | THM | Thermistor Input. Connect a negative temperature coefficient (NTC) thermistor from THM to GND. Connect a resistor equal to the thermistor +25°C resistance from THM to AVL. JEITA-controlled charging available with JEITA_EN = 1. Charging is suspended when the thermistor voltage is outside of the hot and cold limits. Connect THM to GND to disable the thermistor temperature sensor. Connect THM to AVL to emulate battery removal and prevent charging. |
| 14 | SCL | Serial Interface I2C Clock Input |
| 15 | SDA | Serial Interface I2C Data. Open-drain output. |
| 16 | STAT |
Charger Status Output. Active-low, open-drain output, connect to the pullup through a 10kΩ resistor. Pulls low when the charging is in progress. Otherwise, STAT is high impedance. STAT toggles between low and high (when connected to a pullup rail) during charge. STAT becomes low when top-off threshold is detected and charger enters the done state. STAT becomes high (when connected to a pullup rail) when charge faults are detected. |
| 17 | INOKB | Input Power-OK/OTG Power-OK Output. Active-low, open-drain output pulls low when the CHGIN voltage is valid. |
| 18 | INTB | Active-Low Open-Drain Interrupt Output. Connect a pullup resistor to the pullup power source. |
| 19 | SYSA | SYS Voltage Sensing Input for SYS UVLO and OVLO Detection |
| 20 | GND | Analog Ground |
| 21 | INLIM | Charger Input Current Limit Setting Input. Connect a resistor (RINLIM) from INLIM to GND programs the charger input current limit. Refer to Table 5. |
| 22 | CNFG |
Device Configuration Input. Connect a resistor (RCNFG) from CNFG to GND to program the following parameter, see Table 1.
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| 23 | ISET | Fast-Charge Current Setting Input. Connect a resistor (RISET) from ISET to GND programs the fast charge current. See Table 6. |
| 24 | VSET | Charge Termination Voltage Setting Input. Connect a resistor (RVSET) from VSET to GND programs the charge termination voltage. See Table 8. |
| 25 | ITO | Top-Off Current Setting Input. Connect a resistor (RITO) from ITO to GND programs the top-off current. See Table 7. |
| 26 | AVL | Analog Voltage Supply for On-Chip, Low-Noise Circuits. Bypass with a 4.7μF/6.3V ceramic capacitor to GND and connect AVL to PVL with a 4.7Ω resistor. |
| 27 | PVL | Internal Bias Regulator High Current Output Bypass. Supports internal noisy and high current gate drive loads. Bypass to GND with a minimum 4.7μF/6.3V ceramic capacitor, and connect AVL to PVL with a 4.7Ω resistor. Powering external loads from PVL is not recommended, other than pullup resistors. |
| 28 | STBY | Active-High Input. Connect high to disable the DC-DC between CHGIN input and SYS output. Battery supplies the system power if the QBAT is on. See Table 2. Connect low to control the DC-DC with the power-path state machine. To pull the STBY pin low with a pulldown resistor, the resistance must be lower than 44kΩ. |
| 29 | CSINP | Input Current-Sense Positive Input |
| 30 | CSINN | Input Current-Sense Negative Input |