Applications Information

Buck-boost allows a range of inductance for different combinations of switching frequency and maximum nominal CHGIN voltage. See Table 11 for recommendations. The lower the inductor DCR is, the higher the buck-boost efficiency is. The user needs to weigh the trade-offs between inductor size and DCR value and choose a suitable inductor for the buck-boost. See Table 12 for inductor recommendations.

The CHGIN capacitor, C_CHGIN, reduces the current peaks drawn from the input power source and reduces switching noise in the device. In OTG mode, it also reduces the output voltage ripple and ensures regulation loop stability. The impedance of C_CHGIN at the switching frequency should be kept very low. Ceramic capacitors with X5R or X7R dielectrics are highly recommended due to their small size, low ESR, and small temperature coefficients. For most applications, a 10μF capacitor is sufficient. See Table 13 for CHGIN capacitor recommendations.

The SYS capacitor, C_SYS, is required to keep the output voltage ripple small and to ensure regulation loop stability. The C_SYS must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. For stable operation, buck-boost requires 40μF of minimum effective output capacitance. Considering the DC bias characteristic of ceramic capacitors, 2 x 47μF (1210) or 3 x 47μF (1206) or 7 x 22μF (0805) capacitors are recommended for 2-cell applications, and 3 x 47μF (1210) or 4 x 47μF (1206) capacitors are recommended for 3-cell applications. See Table 14 for SYS capacitor recommendations.

When the battery hot inserts into the MAX77960/MAX77961, it creates high inrush current flowing through the body diode of Q_BAT FET. The inrush current peaks at tens of amperes and lasts for less than a few hundreds of microseconds. Such current can possibly damage the Q_BAT FET. For IC protection, the following battery insertion protection is required on the board:

• For system designs with a 2S battery, include an external 3A Schottky diode from BATT to SYS. The Schottky diode has low forward voltage drop when conducting high current in the forward direction. It diverts the inrush current from BATT to SYS at battery insertion. The inrush current flowing through the Q_BAT FET is greatly reduced and therefore the IC is protected. See Figure 14.
• For system designs with a 3S battery, the inrush current is higher than a 2S battery due to higher battery voltage. In addition to the 3A Schottky diode from BATT to SYS, it is required to include an inrush protection circuit. The inrush protection circuit consists of an FET and RC network. See Figure 15 for a complete solution. At battery hot insertion, V_GS of the FET is slowly charged by the RC network. The FET gradually turns on and limits the inrush current. For FET selection, check the current and voltage rating of the FET to guarantee that it satisfies the system specification.

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Careful circuit board layout is critical to achieve low switching power losses and clean, stable operation. Figure 16 shows a PCB layout example.

When designing the PCB, follow these guidelines:

1. Place the CHGIN capacitor (C_CHGIN) and SYS capacitors (C_SYS) immediately next to the CHGIN pin and SYS pin of the IC, respectively. Since the IC operates at a high switching frequency, this placement is critical for minimizing parasitic inductance within the input and output current loops which can cause high voltage spikes and can damage the internal switching MOSFETs.
2. Place the inductor next to the LX pins and make the traces between the LX pins and the inductor short and wide to minimize PCB trace impedance. Excessive PCB impedance reduces converter efficiency. When routing LX traces on a separate layer, make sure to include enough vias to minimize trace impedance. Routing LX traces on multiple layers is recommended to further reduce trace impedance. Furthermore, do not make LX traces take up an excessive amount of area. The voltage on this node switches very quickly and additional area creates more radiated emissions.
3. Route LX nodes to their corresponding bootstrap capacitors (C_BST) as short as possible. Prioritize C_BST placement to reduce trace length to the IC.
4. Route CSINP and CSINN traces as symmetrical as possible. Having the same trace parasitics improves accuracy of the differential CHGIN current sensing.
5. Place the PVL capacitor (C_PVL) immediately next to the PVL pin. Proximity to the IC provides a stable supply for the internal circuitry.
6. Place the BATT capacitor (C_BATT) and SYSA capacitor (C_SYSA) immediately next to the BATT pin and SYSA pin of the IC, respectively.
7. Keep the power traces and load connections short and wide. This is essential for high converter efficiency.
8. Do not neglect ceramic capacitor DC voltage derating. Choose capacitor values and case sizes carefully. See the SYS Capacitor Selection section and refer to Tutorial 5527 for more information.

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