Detailed Description

The MAX77958 is a robust solution for USB Type-C CC detection and power delivery (PD) protocol implementation. It detects connected accessories or devices by using Type-C CC detection and USB PD messaging. The IC protects against overvoltage and overcurrent, and detects moisture and prevents corrosion on the USB Type-C connector. The IC also has a D+/D- USB switch and BC1.2 detection to support legacy USB standards. It contains V_CONN switches for USB PD and an enable pin for an external V_CONN boost or buck converter.

The IC can be used in sink mode to determine the source capabilities of the connected device to optimize power into the sink device. The IC can also be used in source mode to advertise the power capabilities of the source to connected devices and accessories.

The IC is compliant with USB Type-C Version 1.3 and PD 3.0. It can be further customized without affecting the compliance. The embedded default firmware in the MAX77958 is able to support operations that are expected in the Type-C and PD applications.

The default firmware operations are as follows:

• BC1.2, Type-C, and PD adapter detection
• Automatic PD negotiation
• Default sink PDOs: 5V/3A, 9V/3A, and 15V/3A. If there are multiple source PDOs matching to the MAX77958 sink PDO list, the MAX77958 requests the highest power of PDO.
• Automatic role setting according to port partner's role

In addition to the default operation, operation of the IC can be customized for specific applications. This is accomplished using the customization script in the evaluation kit (EV kit) GUI to support different Maxim chargers.

The MAX77958 supports both standalone and MCU based systems. In the standalone system (see Figure 1), the MAX77958 plays a role as system MCU along with the customization script that can be generated through the GUI SW. The customization script is stored in the MTP. In response to events that are happening in the Type-C connector, the customization script automatically executes commands specified by the designer. All sequential control operations are possible without the need for MCU.

In the MCU based system (see Figure 2), the MCU controls the peripheral ICs. In response to port events, the MAX77958 interrupts the MCU and controls the MAX77958 and MAX77962 according to system needs.

The MAX77958 is a complete solution for USB port charger detection and High-Power USB charging on a single USB Type-C connector. It can also be used in any power sink or source application.

The USB Type-C is an internal block that detects connected accessories by using USB Type-C, USB PD messaging and USB BC1.2 charger detection. The USB Type-C block auto-configures switches for common connected accessories including USB cables (SDP/CDP/DCP).

• UFP—Upstream Facing Port. Typical USB device role for data transfer.
• DFP—Down Stream Facing Port. Typical USB host role for data transfer.
• DRP—Dual Role Port. USB Type-C port that can operate in either DFP or UFP roles.
• Source—Initial power state for a DFP. Power role can be swapped by USB Power Delivery command.
• Sink—Initial power state for a UFP. Power role can be swapped by USB Power Delivery command.

The USB Type-C connector management block supports DRP operation. The port cycles between advertising DFP/source and UFP/sink operations while waiting for a port to be connected. The internal state machine handles all the tasks of detecting and configuring the CC pins for the correct mode. A manual mode allows forcing either DFP or UFP operation in cases where the DRP operation is not appropriate

When a DFP is detected (either from DRP mode or force UFP mode), the USB Type-C Connection State Machine detects the active CC line and reports this with an interrupt to the host application processor (AP). The AP then uses this information to de-mux the SuperSpeed USB lines as required. The USB Type-C Connection State Machine also auto detects the DFP advertised current (default, 1.5A and 3.0A). Upon detection of a change in the advertised current, an interrupt is sent to the AP.

When a UFP is detected (either from DRP mode or force DFP mode), the USB Type-C State Machine detects the active CC line. If the Interrupt is enabled, and an AP is present, the IC toggles the INT line to report this to the host AP. Additionally, if an active cable is connected, the IC detects the presence of R_A on the unconnected CC line to determine if it is necessary to turn on V_CONN. The advertised initial supply current is the default USB current (500mA/900mA depending on if SuperSpeed is active). The advertised current can be changed through an I²C command or automatically to 1.5A. 3.0A is optionally available but is disabled by default.

Reported Status and Interrupts

• Connected Device Detection
• Active CC Line
• V_CONN Enabled (R_A Present)
• Advertised Current in UFP (Source) Mode
• Error State

Operation Controls

• Force Source (DFP) or Sink (UFP) State
• Control Swap of Power Role or V_CONN Role
• Enable/Disable of Audio or Debug Accessories
• Set Advertisement of CC Pin Current in Source Role

The IC detects a connection to a DTS when it operates in sink power role. A debug accessory device is detected when the CC1 and CC2 pins are pulled up by an Rp resistor from the connected device.

The voltage levels on the CC1 and CC2 pins give the orientation and current capability.

The MAX77958 features Moisture and Dry detection on the USB Type-C receptacle. When the Moisture detection feature is enabled (enabled as default), the MAX77958 is monitoring CC1/CC2 and SBU1/SBU2 for 1 DRP source cycle periodically. In case the impedance on these pins are less than Moisture threshold, the MAX77958 runs its unique algorithm until Dry is detected on the receptacle.

When Moisture and Dry are detected, the MAX77958 reports to the AP by setting CC_STATUS1[1].

To take advantage of the MAX77958 Moisture detection feature, external resistor configuration on the SBU1 and SBU2 are required.

The USB adapter detection is USB BC1.2 compliant with the ability to automatically detect common charger types.

USB adapter detection has the following controls in the I²C register file:

• Charger detection enable (ChgDetEn)
• Charger detection manual—request a new run of charger detection (ChgDetMan)

The Adapter Detection State Machine follows USB BC1.2 requirements and detects SDP, CDP, and DCP types. If the D+/D- lines are detected as open, the adapter detection state machine indicates SDP as required by BC1.2 requirements.

With a USB BC1.2 compliant state machine, the IC reports that a DCP is detected based on the bias voltage. The IC default firmware can automatically set an external charger's input current limit based on the BC1.2 adapter type that was detected.

The IC also reports the operation status of the Adapter Detection State Machine in the ChgTypRun interrupt bit in the I²C register map.

Note: Adapter Detect running state is indicated until the Adapter Detection State Machine is complete.

The MAX77958 integrates the V_CONN switch which connects V_CIN to one of CC1 and CC2. Once CC detection identifies Ra/Ra on CC1 and CC2, the V_CONN switch routes V_CIN to the pin that is not connected to the CC line in the cable.

The MAX77958 also provides programmable V_CONN switch current limit from 200mA to 500mA in 100mA step. If V_CONN load current exceeds the current limit for 3ms, then an interrupt is generated to the Application Processor (AP). If AP wants to keep supplying V_CONN power, then the AP must configure a higher current limit or no current limit within 12ms. If not, the V_CONN switch is turned OFF in 12ms after an Interrupt is generated.

CCDetEn = 0 or ChgDetEn = 0

   1. Nothing happens when V_BUS is attached. Nothing occurs when ChgDetMan is set to 1.

CCDetEn = 1 and ChgDetEn = 1

1. Charger detection runs automatically when V_BUS is attached
2. If V_BUS voltage enters the valid range, all switches connected to DP/DN are opened
3. Charger detection algorithm begins.
4. When charger detection finishes, DP/DN switch settings are restored.

USBAuto = 0

   1. No automatic switch configuration happens

USBAuto = 1

1. Operates only after charger detection completes, SDP or CDP is found, and if no special charger is found (SpChgTyp = 000 unknown).
2. Set DP/DN connected to DP2/DN1, over-riding any previous switch setting.
3. At any time, the AP is allowed to change these switch settings.
4. If AP has not changed the switch settings when V_BUS drops below the valid level, DP/DN sets to Hi-Z.

The IC supports USB Power Delivery Revision 3.0. The power delivery subsystem is separated into 2 parts: Automatic Power Control and Application Processor Message Passthrough.

Application Processor Message Passthrough

There are many USB PD messages that are unrelated to power control. These messages pass on to the AP to decode and reply. USB PD messages have time critical components and the IC automatically handles these time critical events.

The IC automatically operates in the lowest possible power state. The IC power consumption depends on the following conditions:

• Request has been made across the I²C bus
• USB Type-C end-to-end detection is valid
• V_BUS is present

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 The lowest possible power consumption state is no V_BUS, CCDetEn = 0, and no I²C traffic requests.

The IC monitors the system for the following faults:

• Undervoltage lockout
• VIO fault

When the V_AVL falls below AVL_UVLOF (2.6V max) for more than 8ms, the MAX77958 enters into a shutdown state. Once the V_AVL voltage is higher than AVL_UVLOR (2.8V max), the MAX77958 exits shutdown state to be functional.

When VIO1 and VIO2 fall below 1.0V, the IC goes into shutdown state. Once VIO1 and VIO2 voltages rise higher than 1.3V, the IC comes out of shutdown state.

1. Firmware restarts a watchdog timer in 1.86s.

2. If the watchdog timer is not kicked in 1.86s, it executes the following actions:

   a.) MAX77958 reboots

   b.) MAX77958 notifies MA_SYSERROR_BOOT_WDT

The I²C bus is a multi-master bus. The maximum number of devices that can attach to the bus is only limited by bus capacitance.

Figure 6 shows an example of a typical I²C system. A device on the I²C bus that sends data to the bus is called a transmitter. A device that receives data from the bus is called a receiver. The device that initiates a data transfer and generates SCL clock signals to control the data transfer is a master. Any device that is being addressed by the master is considered a slave. When the MAX77958 I²C-compatible interface is operating, it is a slave on the I²C bus and it can be both a transmitter and a receiver.

One data bit is transferred for each SCL clock cycle. The data on SDA must remain stable during the high portion of the SCL clock pulse. Changes in SDA while SCL is high are control signals (START and STOP conditions).

When the I²C serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high.

A START condition from the master signals the beginning of a transmission to the IC. The master terminates transmission by issuing a NOT ACKNOWLEDGE followed by a STOP condition.

A STOP condition frees the bus. To issue a series of commands to the slave, the master can issue REPEATED START (Sr) commands instead of a STOP command in order to maintain control of the bus. In general, a REPEATED START command is functionally equivalent to a regular START command.

When a STOP condition or incorrect address is detected, the IC internally disconnects SCL from the I²C serial interface until the next START condition, minimizing digital noise and feed-through.

Both the I²C bus master and the IC (slave) generate acknowledge bits when receiving data. The acknowledge bit is the last bit of each nine bit data packet. To generate an ACKNOWLEDGE (A), the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. To generate a NOT-ACKNOWLEDGE (nA), the receiving device allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time.

The IC acts as a slave transmitter/receiver. The slave address of the IC is 0x4Ah/0x4Bh,0x4Ch/0x4Dh and 0x4Eh/0x4Fh depending on configuration of GPIO6.The least significant bit is the read/write indicator (1 for read, 0 for write).

The IC provides I²C 3.0-compatible (1MHz) serial interface.

• I²C Revision 3 Compatible Serial Communications Channel
  • 0Hz to 100kHz (Standard Mode)
  • 0Hz to 400kHz (Fast Mode)
  • 0Hz to 1MHz (Fast-Mode Plus)
• Does not Support I²C Clock Stretching

Operating in standard mode, fast mode, and fast-mode plus does not require any special protocols. The main consideration when changing the bus speed through this range is the combination of the bus capacitance and pullup resistors. Higher time constants created by the bus capacitance and pullup resistance (C x R) slow the bus operation. Therefore, when increasing bus speeds the pullup resistance must be decreased to maintain a reasonable time constant. Refer to the “Pullup Resistor Sizing” section of the I²C revision 3.0 specification for detailed guidance on the pullup resistor selection. In general, for bus capacitance of 200pF, a 100kHz bus needs 5.6kΩ pullup resistors, a 400kHz bus needs about 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω pullup resistors. Note that the pullup resistor dissipates power when the open-drain bus is low. The lower the value of the pullup resistor, the higher the power dissipation (V²/R).

Operating in high-speed mode requires some special considerations. For the full list of considerations, see the I²C 3.0 specification. The major considerations with respect to the IC are:

• I²C bus master uses current source pullups to shorten the signal rise times.
• I²C slave must use a different set of input filters on its SDA and SCL lines to accommodate for the higher bus speed.
• The communication protocols need to utilize the high-speed master code.

At power-up and after each STOP condition, the IC input filters are set for standard mode, fast mode, or fast-mode plus (i.e., 0Hz to 1MHz). To switch the input filters for high-speed mode, use the high-speed master code protocols that are described in the Communication Protocols section.

Figure 9 shows the protocol for the I²C master device to write one byte of data to the IC. This protocol is the same as SMBus specification’s “Write Byte” protocol.

The “Write Byte” protocol is as follows:

1. The master sends a START command (S).
2. The master sends the 7-bit slave address followed by a write bit (R/W = 0).
3. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
7. The slave acknowledges the data byte. At the rising edge of SCL, the data byte is loaded into its target register and the data becomes active.
8. The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing a REPEATED START (Sr) leaves the bus input filters in their current state.

Figure 10 shows the protocol for writing to sequential registers. This protocol is similar to the “Write Byte” protocol, except the master continues to write after it receives the first byte of data. When the master is done writing, it issues a STOP or REPEATED START.

The “Writing to Sequential Registers” protocol is as follows:

1. The master sends a START command (S).
2. The master sends the 7-bit slave address followed by a write bit (R/W = 0).
3. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a data byte.
7. The slave acknowledges the data byte. At the rising edge of SCL, the data byte is loaded into its target register and the data becomes active.
8. Steps 6 to 7 are repeated as many times as the master requires.
9. During the last acknowledge related clock pulse, the slave issues an ACKNOWLEDGE (A).
10. The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing a REPEATED START (Sr) leaves the bus input filters in their current state.

The I²C master device reads one byte of data to the IC. This protocol is the same as SMBus specification’s “Read Byte” protocol.

The “Read Byte” protocol is as follows:

1. The master sends a START command (S).
2. The master sends the 7-bit slave address followed by a write bit (R/W = 0).
3. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a REPEATED START command (Sr).
7. The master sends the 7-bit slave address followed by a read bit (R/W = 1).
8. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
9. The addressed slave places 8-bits of data on the bus from the location specified by the register pointer.
10. The master issues a NOT-ACKNOWLEDGE (nA).
11. The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing a REPEATED START (Sr) leaves the bus input filters in their current state.

Figure 12 shows the protocol for reading from sequential registers. This protocol is similar to the “Read Byte” protocol except the master issues an ACKNOWLEDGE (A) to signal the slave that it wants more data—when the master has all the data it requires, it issues a NOT-ACKNOWLEDGE (nA) and a STOP (P) to end the transmission.

The “Continuous Read from Sequential Registers” protocol is as follows:

1. The master sends a START command (S).
2. The master sends the 7-bit slave address followed by a write bit (R/W = 0).
3. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
4. The master sends an 8-bit register pointer.
5. The slave acknowledges the register pointer.
6. The master sends a REPEATED START command (Sr).
7. The master sends the 7-bit slave address followed by a read bit (R/W =1).
8. The addressed slave asserts an ACKNOWLEDGE (A) by pulling SDA low.
9. The addressed slave places 8-bits of data on the bus from the location specified by the register pointer.
10. The master issues an ACKNOWLEDGE (A) signaling the slave that it wishes to receive more data.
11. Steps 9 to 10 are repeated as many times as the master requires. Following the last byte of data, the master must issue a NOT-ACKNOWLEDGE (nA) to signal that it wishes to stop receiving data.
12. The master sends a STOP condition (P) or a REPEATED START condition (Sr). Issuing a STOP (P) ensures that the bus input filters are set for 1MHz or slower operation. Issuing a REPEATED START (Sr) leaves the bus input filters in their current state.

Figure 13 shows the protocol for engaging HS-Mode operation. HS-Mode operation allows for a bus operating speed up to 3.4MHz.

The “Engaging HS-Mode” protocol is as follows:

1. Begin the protocol while operating at a bus speed of 1MHz or lower.
2. The master sends a START command (S).
3. The master sends the 8-bit master code of 0000 1xx0b, where ‘xx’ are don’t care bits.
4. The addressed slave issues a NOT-ACKNOWLEDGE (nA).
5. The master may now increase its bus speed up to 3.4MHz and issue any read/write operation.

The master may continue to issue high-speed read/write operations until a STOP (P) is issued. Issuing a STOP (P) ensures that the bus input filters are set for 1MHz or slower operation.

The MAX77958 I²C supports the HS mode extension feature. The HS extension feature keeps the high-speed operation even after a ‘STOP’ condition. This eliminates the need for HS master code issued by the I²C master controller when the I²C master controller wants to stay in HS mode for multiple read/write cycles.

As shown in Figure 14, the HS extension mode can be enabled by setting HS_EXT bit in I2C_CFG register (ADDR 0x15) from LS mode only (entering HS extension mode from HS mode is not supported).