| PARAMETER | SYMBOL | CONDITIONS | MIN | TYP | MAX | UNITS |
|---|---|---|---|---|---|---|
| GLOBAL INPUT SUPPLY | ||||||
| Shutdown Supply Current | ISHDN | EN = LOW, VIN = 8.4V, VVIO = 0V, TA = +25°C | 4 | 15 | μA | |
| Quiescent Current 1 | IQ1 | VIN = 8.4V, automatic mode | 30 | μA | ||
| Shutdown VIO Current | ISHDN_VIO | 0 | μA | |||
| OUT Leakage Current | ILK_OUT | VOUT = 4.2V, AD_EN = 0 | 1.4 | μA | ||
| INPUT UNDERVOLTAGE LOCKOUT | ||||||
| Undervoltage-Lockout Threshold | VUVLO_R | Rising (when VUVLO_F = 4.1V) | 4.9 | V | ||
| VUVLO_F | Falling (OTP options: 4.1V, 4.3V, 4.5V, 4.7V) | 3.977 | 4.1 | 4.223 | ||
| THERMAL ALARMS AND SHUTDOWN | ||||||
| Thermal Alarm at +100°C | TINT100 | TJ rising, +15°C hysteresis | 100 | °C | ||
| Thermal Alarm at +120°C | TINT120 | TJ rising, +15°C hysteresis | 120 | °C | ||
| ENABLE INPUTS AND LOGIC | ||||||
| EN Debounce Time | tEN | EN_DEB[2:0] = 010 | 2 | ms | ||
| Input LOW Level | VIL | 0.4 | V | |||
| Input HIGH Level | VIH | 1.1 | V | |||
| Input Leakage Current | ILK | 0.1 | µA | |||
| Output High Leakage IRQB | VIRQB = 5.5V, TA = +85°C | 0.1 | μA | |||
| SWITCHED-CAPACITOR CONVERTER | ||||||
| Input Operating Voltage Range | VIN | VUVLO_F | VIOVP | V | ||
| Input OVP | VIOVP | I2C programmable 9.5V, 10.0V, 10.5V, 11.0V; default 9.5V | 9.5 | V | ||
| Output OVP | VOOVP | Default = 5V | 5 | V | ||
| OCP Threshold | IOCP | I2C programmable from 4.2A to 11.6A with 200mA step; default 8.8A | 8.8 | A | ||
| OCP Accuracy | IOCP_ACC | IOCP = 8.8A | -10 | +10 | % | |
| In the entire IOCP range | -16 | +16 | ||||
| OCP2 Offset | IOCP2 | I2C programmable from 90mV to 240mV with 10mV step; default 240mV | 240 | mV | ||
| Soft-Start Current | ISS | I2C programmable options: 145mA, 290mA, 435mA, 580mA; default 580mA | 580 | mA | ||
| Soft-Start Current Accuracy | ISS_ACC | ISS = 290mA | -30 | +30 | % | |
| Light Load Efficiency 1 | ηLIGHT1 | IOUT = 1mA, VIN = 7.4V | 92 | % | ||
| Light Load Efficiency 2 | ηLIGHT2 | IOUT = 30mA, VIN = 7.4V | 97 | % | ||
| Peak Efficiency | ηPEAK | VIN = 7.4V, fSW = 0.25MHz | 98.5 | % | ||
| Heavy Load Efficiency | ηHEAVY | IOUT = 8A, VIN = 7.4V | 95 | % | ||
| S1, S5 NMOS ON Resistance | RDSON | IN to CFxP | 11 | mΩ | ||
| S2, S6 NMOS ON Resistance | RDSON | OUT to CFxN | 13 | mΩ | ||
| S3, S7 NMOS ON Resistance | RDSON | CFxP to OUT | 13 | mΩ | ||
| S4, S8 NMOS ON Resistance | RDSON | CFxN to PGND | 13 | mΩ | ||
| Switching Frequency | fSW | I2C programmable options: 0.25MHz, 0.5MHz, 0.75MHz, 1MHz, 1.2MHz, 1.5MHz; when 0.5MHz is selected | 0.47 | 0.5 | 0.53 | MHz |
| Switching Frequency Dither Rate | fSW_DTHR | I2C programmable options: OFF, 3%, 6%, 12%; default 3% | -3 | +3 | % | |
| Dead Time | tDDT |
S1 off to S3 on, S3 off to S1 on S2 off to S4 on, S4 off to S2 on S5 off to S7 on, S7 off to S5 on S6 off to S8 on, S8 off to S6 on |
10 | ns | ||
| SKIP Mode Threshold | ISKIP | Enter to SKIP mode, 0.5A hysteresis | 1.1 | A | ||
| OUT Active Discharge Resistance | RAD_OUT | Enable output active discharge; disable output | 1k | 1.5k | Ω | |
| LINEAR REGULATORS | ||||||
| AVDD Linear Regulator Output Voltage | VAVDD | 1.71 | 1.8 | 1.89 | V | |
| HVDD Linear Regulator Output Voltage | VOUT + 1.8 | V | ||||
| INTERNAL PULLUP/DOWN RESISTANCE | ||||||
| EN Pulldown Resistance | RPUPD | Pulled down to AGND, when internal pulldown enabled | 1.5 | MΩ | ||
| SDA AND SCL I/O STAGE | ||||||
| SCL, SDA Input Low Level | TA = +25°C | 0.3 x VVIO | V | |||
| SCL, SDA Input High Level | TA = +25°C | 0.7 x VVIO | V | |||
| SCL, SDA Input Hysteresis | TA = +25°C | 0.05 x VVIO | V | |||
| SCL, SDA Logic Input Current | VSCL = VSDA = VVIO = 1.8V | -10 | +10 | µA | ||
| SCL, SDA Input capacitance | 10 | pF | ||||
| SDA Output Low Voltage | Sinking 20mA | 0.4 | V | |||
| I2C COMPATIBLE INTERFACE TIMING FOR STANDARD, FAST, AND FAST-MODE PLUS | ||||||
| Clock Frequency | fSCL | 1000 | kHz | |||
| Hold Time (Repeated) START Condition | tHD;STA | 0.26 | µs | |||
| CLK Low Period | tLOW | 0.5 | µs | |||
| CLK High Period | tHIGH | 0.26 | µs | |||
| Setup Time Repeated START Condition | tSU;STA | 0.26 | µs | |||
| DATA Hold Time | tHD:DAT | 0 | µs | |||
| DATA Valid Time | tVD:DAT | 0.45 | µs | |||
| DATA Valid Acknowledge Time | tVD:ACK | 0.45 | µs | |||
| DATA Setup time | tSU;DAT | 50 | ns | |||
| Setup Time for STOP Condition | tSU;STO | 0.26 | µs | |||
| Bus-Free Time Between STOP and START | tBUF | 0.5 | µs | |||
| Pulse Width of Spikes that Must be Suppressed by the Input Filter | 50 | ns | ||||
| I2C COMPATIBLE INTERFACE TIMING FOR HS-MODE (CB = 100pF) | ||||||
| Clock Frequency | fSCL | 3.4 | MHz | |||
| Setup Time Repeated START Condition | tSU;STA | 160 | ns | |||
| Hold Time (Repeated) START Condition | tHD;STA | 160 | ns | |||
| CLK Low Period | tLOW | 160 | ns | |||
| CLK High Period | tHIGH | 60 | ns | |||
| DATA Setup time | tSU;DAT | 10 | ns | |||
| DATA Hold Time | tHD:DAT | 0 | ns | |||
| Setup Time for STOP Condition | tSU;STO | 160 | ns | |||
| Pulse Width of Spikes that Must be Suppressed by the Input Filter | 10 | ns | ||||
| I2C COMPATIBLE INTERFACE TIMING FOR HS-MODE (CB = 400pF) | ||||||
| Clock Frequency | fSCL | 1.7 | MHz | |||
| Setup Time Repeated START Condition | tSU;STA | 160 | ns | |||
| Hold Time (Repeated) START Condition | tHD;STA | 160 | ns | |||
| CLK Low Period | tLOW | 320 | ns | |||
| CLK High Period | tHIGH | 120 | ns | |||
| DATA Setup time | tSU;DAT | 10 | ns | |||
| DATA Hold Time | tHD:DAT | 0 | ns | |||
| Setup Time for STOP Condition | tSU;STO | 160 | ns | |||
| Pulse Width of Spikes that Must be Suppressed by the Input Filter | 10 | ns | ||||