In modern electronic devices, system level current consumption is ever increasing to fulfill the needs of more power-hungry end applications. This generally requires larger battery energy storage and thus higher power charging to keep the same charging time. For many low-voltage applications, it is sometimes advantageous to configure the battery source as a 2-series battery and use a highly-efficient 2-to-1 voltage converter to supply the system. With the same charging current, it is much faster to charge 2-series batteries than 2-parallel batteries because of the higher charger voltage. On the system side, the 2-to-1 converter acts as a current-doubler, thus delivering much higher current to the system. In this configuration, the system uses the 2-series battery as if it is 2-parallel, with the benefit of charging much faster. The switched-capacitor converter fits this requirement well by providing ultra-high DC-DC conversion efficiency and occupying less PCB design area.
Switched-Capacitor Converter (SCC)
The SCC is a type of DC-DC converter that only utilizes capacitors as the energy storage device. Compared to the buck converter which utilizes inductors, the switched-capacitor converter topology achieves higher efficiency with smaller solution size and lower cost.
The IC is an interleaved, dual-phase switched-capacitor converter. It generates an output voltage of VIN/2 and is capable of supplying up to 8A output current. Each phase of the interleaved SCC operates with a fixed 50% duty cycle and reduces the ripple on the output voltage and current.
Enable or Disable the Device by EN
The IC can be enabled or disabled by digitally controlling the EN pin when VIO is kept low. The EN pin is active-high. Once EN is pulled high for longer than the EN debounce time, the IC initiates the soft-start operation. If the soft-start operation is successful, it is followed by the SCC fully-active state. The SCC turns off immediately when EN is low. To always enable the IC, tie the EN pin to VIN.
Figure 1. Enable Timing Waveform Without VIO
Enable or Disable the Device by EN and VIO
The IC can be kept enabled by holding valid VIO, and EN can be configured as push-button operation.
Once the EN pin is pulled high for longer than the EN debounce time, the IC initiates the soft-start followed by the SCC fully active. If VIO is asserted and valid (VIO > VIO_OK threshold) IC before EN is released (means goes HIGH), then this holds the output. If EN goes LOW before VIO is valid, the IC disables the output. After the output is on hold, the SCC can be turned off by turning off the VIO regulator in the application system. The SCC turns off after OFF_DEB has passed after the moment VIO goes low. Usually, VIO is system IO voltage rail so this feature enables the device with a push-button easier and disables when the system is going to shutdown.
Figure 2. Enable Timing Waveform with VIO Hold
Enable by I2C
Some applications can supply VIO before the IC output is enabled. In this case, the host microcontroller can enable the IC output by writing SCC_EN register to 0x1 through I2C. The host can disable the output by writing the SCC_EN register to 0x0 through I2C.
Figure 3. Enable Timing Waveform with I2C Command
Startup and Soft-Start
During the device startup, the flying capacitors (CFLY)are connected in parallel to the output capacitor. An internal current source charges the capacitors up to the voltage close to the target VIN/2 in normal operation. The soft-start current can be configured through I2C.
If the output voltage has not reached the voltage close to VIN/2 within 120ms (default soft-start timeout setting), the IC generates the interrupt of SS_FLT_INT (Soft-Start Timer Fault Interrupt) and it returns to the STANDBY state. If the soft-start is successful, the SCC enters the normal operation.
PGOOD
PGOOD is a power good indicator output. After soft-start, the PGOOD pin outputs 1.8V. PGOOD remains at 1.8V as long as SCC is operating normally. If the PGOOD feature is used, an external RC filter with 1kΩ and 10nF is required to add at the PGOOD pin.
Figure 4. PGOOD Filter Example Circuit
Automatic Mode (Automatic-Skip Mode) and Fixed-Frequency Mode
When the IC enters normal operation, the SCC operates with 50% duty cycle. The switching frequency can be configured through the SCC_CFG2 register.
In the fixed-frequency mode, the SCC always operates, which provides unregulated VIN/2 voltage at the OUT pin. When load current is low, the switcher consumption becomes significant enough to affect efficiency. To save power, the IC can enter the automatic-skip mode to only turn on the switcher when OUT voltage drops below the SKIP operation threshold.
To enable the IC to automatically enter SKIP mode when OUT load current is low, configure as SCC_CFG1.FIX_FREQ = 0. This is the default setting.
To configure the IC to always operate in fixed-frequency mode, configure as SCC_CFG1.FIX_FREQ = 1.
Operation detail for the SKIP mode is illustrated in Figure 5. When the output voltage is higher than REF_DCM, the IC enters into SKIP mode. In SKIP mode, the IC only switches when the output voltage drops below REF_SKIP. The IC stops switching when output voltage reaches the REF_SKIP_H threshold. When a heavy load is applied and the output falls down to the REF_CCM threshold, the IC enters the fixed-frequency mode. By doing it this way, it saves power in light loads and eventually provides higher efficiency at the entire load range as well as still maintaining the output close to VIN/2.
Figure 5. SKIP Mode Operation Diagram
Undervoltage Lockout
When VIN falls below VUVLO_F (typ 4.1V, OTP option), the IC enters into the shutdown state and UVLO forces the IC to a dormant state until VIN rises above the VUVLO_R threshold which allows the IC to be securely functional. VUVLO_F is programmable through I2C or OTP.
Frequency Dithering
Switched DC-DC converter operation can produce EMI emissions with a dominant peak frequency. Frequency dithering can reduce the peak emission of the converter by spreading the emission over a frequency band. The IC includes a frequency dithering feature applicable to all synthesized frequencies (from 0.25MHz up to 1.5MHz). Dithering can be disabled or enabled with different programmable spreads (3%, 6%, 12%).
Overcurrent Protections
During operation, the IC provides two layers of overcurrent protection. The output current is monitored for detecting overcurrent condition OCP1. The output voltage is sensed for faster short-circuit protection OCP2.
The IC protects and disables the output if the output current ≥ OCP1 or the output voltage ≤ VIN/2 - OCP2.
OCP1 can be programmed from 4.2A to 9.6A in steps of 200mA, or additionally to 10.0A, 10.4A, 11.0A, or 11.6A through I2C. OCP2 is programmable from 110mV to 240mV in steps of 10mV, or additionally set to OFF or 310mV through I2C.
High Current Alarm
When IOUT reaches 90% of IOCP (progammable to 80% or 90% through I2C), OC_ALM_INT interrupt bit and OC_ALM status bits are set.
When IOUT decreases below 85% of the level of IOCP, the OC_ALM status bit resets.
Thermal Alarms and Fault
The IC has a thermal protection circuit which monitors temperature on the die. If the die temperature exceeds +155°C, the IC enters the thermal shutdown state, and the T_SHDN_INT sets. After the thermal shutdown, if the die temperature reduces by +15°C, the thermal shutdown is deasserted and the user can re-enable the SCC again.
In addition to the +155°C threshold, there are additional comparators which trip at +100°C and +120°C. T_ALM1 and T_ALM2 interrupts are generated respectively.
Input Overvoltage Protection (IOVP)
When VIN is higher than VIOVP (I2C programmable to 9.5V, 10.0V, 10.5V, or 11.0V), the switched-capacitor converter disables output and enters the standby mode.
State Diagram
Figure 6 shows the operation states and conditions to trigger state transitions.
Figure 6. Device State Diagram
I2C Interface Description
Main I2C Interface
The IC acts as a Slave Transmitter/Receiver and has the following slave addresses:
Slave Address (7 bit) 110 1000
Slave Address (Write) 0xD0 1101 0000
Slave Address (Read) 0xD1 1101 0001
I2C Bit Transfer
One data bit is transferred for each clock pulse. The data on SDA must remain stable during the high portion of the clock pulse as changes in data during this time are interpreted as a control signal.
Figure 7. I2C Bit Transfer
I2C Start And Stop Conditions
Both SDA and SCL remain High when the bus is not busy. The Start (S) condition is defined as a high-to-low transition of the SDA while the SCL is high. The Stop (P) condition is defined as a low-to-high transition of the SDA while the SCL is high.
Figure 8. I2C Start and Stop
I2C System Configuration
A device on the I2C bus that generates a “message” is called a “Transmitter” and a device that receives the message is a “Receiver”. The device that controls the message is the “Master” and the devices that are controlled by the “Master” are called “Slaves”.
Figure 9. System Configurations
I2C Acknowledge
The number of data bytes between the start and stop conditions for the Transmitter and Receiver are unlimited.
Each 8-bit byte is followed by an Acknowledge bit. The Acknowledge bit is a high level signal put on SDA by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after each byte it receives. Also a master receiver must generate an acknowledge after each byte it receives that has been clocked out of the slave transmitter.
The device that acknowledges must pulldown the SDA line during the acknowledge-clock pulse, so that the SDA line is stable and low during the high period of the acknowledge-clock pulse (setup and hold times must also be met). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave SDA high to enable the master to generate a stop condition.
Figure 10. I2C Acknowledge
Master Transmits (Write Mode)
Use the following format when the master writes to the slave.
Figure 11. I2C Master Transmits
Master Reads After Setting Register Address (Write Register Address and Read Data)
Use the following format to read a specific register.
Figure 12. I2C Master Reads After Setting Register Address
Master Reads Register Data Without Setting Register Address (Read Mode)
Use the following format to read registers continuously starting from first address.
