The input capacitor, CIN, reduces the current peaks drawn from the input power source and reduces switching noise in the device. The impedance of CIN at the switching frequency should be kept very low. Ceramic capacitors with X5R or X7R dielectrics are highly recommended due to their small size, low ESR, and small temperature coefficients. For most applications, a 4.7µF capacitor per phase is sufficient.
The output capacitor, COUT, is required to keep the output voltage ripple small. COUT must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. The recommended minimum output capacitance is 10µF per phase.
The flying capacitor, CFLY, is required to have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. For optimized efficiency, it is recommended to select 2x47µF for each phase.
MFGR. |
SERIES |
NOMINAL |
RATED |
TEMPERATURE CHARACTERISTICS |
CASE SIZE |
DIMENSIONS |
Murata | GRM188B31C475KAAJ | 4.7 | 16 | X5R | 0603 | 1.6 x 0.8 x 0.8 |
MFGR. |
SERIES |
NOMINAL |
RATED |
TEMPERATURE CHARACTERISTICS |
CASE SIZE |
DIMENSIONS |
Murata | GRM188R60J476ME15 | 47 | 6.3 | X5R | 0603 | 1.6 x 0.8 x 0.8 |
Murata | GRM219R60J476ME44 | 47 | 6.3 | X5R | 0805 | 2.0 x 1.2 x 0.85 |
MFGR. |
SERIES |
NOMINAL |
RATED |
TEMPERATURE CHARACTERISTICS |
CASE SIZE |
DIMENSIONS |
Murata | GRM155R60J106ME15 | 10 | 6.3 | X5R | 0402 | 1.0 x 0.5 x 0.5 |
MFGR. |
SERIES |
NOMINAL |
RATED |
TEMPERATURE CHARACTERISTICS |
CASE SIZE |
DIMENSIONS |
Murata | GRM033R61A105ME15 | 1 | 10 | X5R | 0201 | 0.6 x 0.3 x 0.3 |
MFGR. |
SERIES |
NOMINAL |
RATED |
TEMPERATURE CHARACTERISTICS |
CASE SIZE |
DIMENSIONS |
Murata | GRM033R60J473KE15 | 0.047 | 6.3 | X5R | 0201 | 0.6 x 0.3 x 0.3 |
Layout Guidelines
- The CFLY capacitors need to be placed as close as possible to the IC. This is a high priority.
- All power traces must be as symmetrical as possible across two phases. For example, the CF1P is symmetrical with CF1N, and the OUT trace is symmetrical on both sides.
- The guide has a power trace under the capacitor. For some designs, this is not allowed. If this is not allowed, keep the same flying capacitor location, and put a lot of via near the OUT pin of the IC to bring it down to another layer, and use multiple layers of the same trace to reinforce the OUT trace. Refer to the MAX77932 EV kit as an example.
- For the AGND pin, do not directly tie to the top layer PGND. Run via through and tie it to the more stable system ground plane.
- For inner pins, especially BST1P/N, BST2P/N, and HVDD, they need to connect through via. They are critical to the operation of the converter. Use a trace as wide as possible on the connecting layer to connect these pins, and the shortest path possible to the corresponding capacitors.