Pin Specifications

Pin Description
PIN	NAME	FUNCTION	REF SUPPLY	TYPE
D6	SYS_Q	Quiet SYS Input		Power
D9	SYS_A	Analog SYS Input	2	Power
A1, A3, A9, D3, D4, D5, E5, F4, J9	GND_A	Analog Ground. Short to GND_D, GND_D2 and GND_Q.	GND	GND
C4	GND_D	Digital Ground Connection. Short to GND_D2, GND_A, and GND_Q.	1	GND
C8	GND_Q	Quiet Ground Connection. Short to GND_A, GND_Q, GND_D, and GND_D2.	1	GND
J8	GND_D2	Digital Ground Connection. Short to GND_D, GND_A, and GND_Q.		GND
E1, E2, E3, F1, F2	SYS	System Power Connection. Connect system loads to this node. Bypass with 2 x 10µF/10V ceramic capacitors from SYS to CHGPG ground plane.	5	Power
H5, H6, J5, J6	CHGIN	High Current Charger Input. Bypass to CHGPG with a 2.2µF/25V ceramic capacitor. It also serves as the reverse boost output.	CHGIN	Power
G5, G6, H4, J4	BYP	CHGIN Bypass Pin. This pin can see up to OVP limit. Output of adapter input current limit block and input to switching charger. BYP is also the boost converter output when the charger is operating in 'reverse boost' mode. Bypass with 2 x 10µF/25V ceramic capacitors from BYP to CHGPG ground plane.
H2, H3, J2, J3	CHGLX	Charger Switching Node. Connect the inductor between CHGLX and SYS.	4
G3	BST	High-side FET Driver Supply. Bypass BST to CHGLX with a 0.1µF/6.3V ceramic capacitor.	1
G1, H1, J1	CHGPG	Charger Power Ground Connection	2	GND
G2	CHGRGSUB	Substrate Charger Ground Connection	1	GND
F5	AVL	Analog Voltage Level. Output of on-chip 5V LDO used to power on-chip, low-noise circuits. Bypass with a 2.2µF/10V ceramic capacitor to GND. Powering external loads from AVL is not recommended, other than pulldown resistors.	1
G4	PVL	Internal bias regulator high current output bypass pin. Supports internal noisy and high current gate drive loads. Bypass to PGND with a minimum 10µF/10V ceramic capacitor.	1
C7	CHGIND	Charging Status Indication GPIO output. Open-drain, option to tie to charger as an active-low output that indicates when the charging is active.	AVL	I/O
C1, C2, D1, D2	BATT	Battery Power Connection. Connect to the positive terminal of a single-cell (or parallel cell) Li-ion battery. Bypass BATT to CHGPG ground plane with a 10µF/10V ceramic capacitor.	4
E4	BAT_SP	Battery Positive Differential Sense Connection. Connect to the positive terminal close to the battery.	BATT
F3	BAT_SN	Battery Negative Differential Sense Connection. Connect to the negative or ground terminal close to the battery.	BATT
E6	INOKB	Charger input valid, active-low logic output flag. Open-drain output indicates when valid voltage is present at both CHGIN and SYS.	1
E7	DETBATB	Battery Detection Active-Low Input. Connect this pin to the ID pin on the battery pack. If DETBATB is pulled below 80% of the externally applied V_IO voltage, this is an indication that the battery is present and the charger starts when valid CHGIN and/or WCIN power is present. If DETBATB is driven high to V_IO voltage or left unconnected, this is an indication that the battery is not present and the charger does not start. DETBATB is pulled high to V_IO pin through an off-chip pullup resistor.	1
B2	ONKEY	ONKEY is an active-low signal with default 1000ms debounce timer. When no charging source is available at CHGIN, enable DISQIBS bit (DISIBS = 1) with I²C to set the device in ship mode. With a healthy battery, pressing the ONKEY longer than the debounce timer re-enables the Q_BAT switch and the device exits ship mode.	AVL
F6	OVPENB	Logic-low enable pin enables the external overvoltage protection IC.	1
D7	V_BUSDET	Input Voltage Detection Pin. This input pin is a voltage clamped version of the input voltage and is used to trigger the device OVLO/UVLO features. Connect a 1µF ceramic capacitor between this pin and CHGPG (ground).	1
B5	SLAVE	Input pin to indicate if slave charger is connected. Short to GND_A—no slave charger connected. Short to SYS_A—slave charger connected.
C5	SWI1	Data Input/Output. Open-drain, 1-wire interface pin for slave 1.	1
C6	SWI2	Data Input/Output. Open-drain, 1-wire interface pin for slave 2.
B3	CSP	Slave-Charger Sense Current Positive Input. Option to add a 10mΩ sense resistor from CSP to CSN to have current sense information return to the master for processing. If slave charging is unused, short this pin to BATT.	1
C3	CSN	Slave-Charger Sense Current Negative Input. Option to add a 10mΩ sense resistor from CSP to CSN to have current sense information return to the master for processing. If slave charging is unused, short this pin to BATT.
J7	SAFEOUT	Safeout LDO Output. Default 4.9V and on when CHGIN power is valid. Bypass with a 1µF/10V ceramic capacitor to GND.	1
E8	V_IO	Digital I/O Supply Input for I²C interface	1
F9	SDA	I²C Serial Data	1
E9	SCL	I²C Serial Clock	1
D8	INTB	Interrupt Output. Active-low, open-drain output.	1
B1	THM	Thermistor Connection. Determine battery temperature using ratiometric measurement.	1
A2	THMB	Pullup voltage for THM pin pullup resistor that can be switched to save power.	1
C9	TEST1	Test I/O Pin. Ground this pin in the application.	V_CCTEST
B8	TEST2	Test I/O Pin. Ground this pin in the application.	1
B7	TEST3	Test I/O Pin. Ground this pin in the application.	1
B6	TEST4	Test I/O Pin. Ground this pin in the application.	1
B9	V_CCTEST	Test Mux Supply. Ground this pin in the application.	1
A7	DN	Common Negative Output 1. Connect to D- on mini/micro USB connector.	1
A8	DP	Common Positive Output2. Connect to D+ on mini/micro USB connector.	1
A6	CC1	Type-C CC pin 1, can be connected in parallel with USB power delivery transceiver.
A4	CC2	Type-C CC pin 2, can be connected in parallel with USB power delivery transceiver.
A5	V_CONNIN	5V power supply for supplying power to the unused CC pin if required.
B4	V_{CONNBTEN_SYS}	Output pin, used to enable external V_CONN boost.
F7, F8, G7, G8, G9, H7, H8, H9	NC1–NC8	No connection. Connect to GND.

D6

SYS_Q

Quiet SYS Input

Power

D9

SYS_A

Analog SYS Input

2

Power

A1, A3, A9, D3, D4, D5, E5, F4, J9

GND_A

Analog Ground. Short to GND_D, GND_D2 and GND_Q.

GND

C4

GND_D

Digital Ground Connection. Short to GND_D2, GND_A, and GND_Q.

1

GND

C8

GND_Q

Quiet Ground Connection. Short to GND_A, GND_Q, GND_D, and GND_D2.

1

GND

J8

GND_D2

Digital Ground Connection. Short to GND_D, GND_A, and GND_Q.

GND

E1, E2, E3, F1, F2

SYS

System Power Connection. Connect system loads to this node. Bypass with 2 x 10µF/10V ceramic capacitors from SYS to CHGPG ground plane.

5

Power

H5, H6, J5, J6

CHGIN

High Current Charger Input. Bypass to CHGPG with a 2.2µF/25V ceramic capacitor. It also serves as the reverse boost output.

CHGIN

Power

G5, G6, H4, J4

BYP

CHGIN Bypass Pin. This pin can see up to OVP limit. Output of adapter input current limit block and input to switching charger. BYP is also the boost converter output when the charger is operating in 'reverse boost' mode. Bypass with 2 x 10µF/25V ceramic capacitors from BYP to CHGPG ground plane.

H2, H3, J2, J3

CHGLX

Charger Switching Node. Connect the inductor between CHGLX and SYS.

4

G3

BST

High-side FET Driver Supply. Bypass BST to CHGLX with a 0.1µF/6.3V ceramic capacitor.

1

G1, H1, J1

CHGPG

Charger Power Ground Connection

2

GND

G2

CHGRGSUB

Substrate Charger Ground Connection

1

GND

F5

AVL

Analog Voltage Level. Output of on-chip 5V LDO used to power on-chip, low-noise circuits. Bypass with a 2.2µF/10V ceramic capacitor to GND. Powering external loads from AVL is not recommended, other than pulldown resistors.

1

G4

PVL

Internal bias regulator high current output bypass pin. Supports internal noisy and high current gate drive loads. Bypass to PGND with a minimum 10µF/10V ceramic capacitor.

1

C7

CHGIND

Charging Status Indication GPIO output. Open-drain, option to tie to charger as an active-low output that indicates when the charging is active.

AVL

I/O

C1, C2, D1, D2

BATT

Battery Power Connection. Connect to the positive terminal of a single-cell (or parallel cell) Li-ion battery. Bypass BATT to CHGPG ground plane with a 10µF/10V ceramic capacitor.

4

E4

BAT_SP

Battery Positive Differential Sense Connection. Connect to the positive terminal close to the battery.

BATT

F3

BAT_SN

Battery Negative Differential Sense Connection. Connect to the negative or ground terminal close to the battery.

BATT

E6

INOKB

Charger input valid, active-low logic output flag. Open-drain output indicates when valid voltage is present at both CHGIN and SYS.

1

E7

DETBATB

Battery Detection Active-Low Input. Connect this pin to the ID pin on the battery pack. If DETBATB is pulled below 80% of the externally applied V_IO voltage, this is an indication that the battery is present and the charger starts when valid CHGIN and/or WCIN power is present. If DETBATB is driven high to V_IO voltage or left unconnected, this is an indication that the battery is not present and the charger does not start. DETBATB is pulled high to V_IO pin through an off-chip pullup resistor.

1

B2

ONKEY

ONKEY is an active-low signal with default 1000ms debounce timer. When no charging source is available at CHGIN, enable DISQIBS bit (DISIBS = 1) with I²C to set the device in ship mode. With a healthy battery, pressing the ONKEY longer than the debounce timer re-enables the Q_BAT switch and the device exits ship mode.

AVL

F6

OVPENB

Logic-low enable pin enables the external overvoltage protection IC.

1

D7

V_BUSDET

Input Voltage Detection Pin. This input pin is a voltage clamped version of the input voltage and is used to trigger the device OVLO/UVLO features. Connect a 1µF ceramic capacitor between this pin and CHGPG (ground).

1

B5

SLAVE

Input pin to indicate if slave charger is connected. Short to GND_A—no slave charger connected. Short to SYS_A—slave charger connected.

C5

SWI1

Data Input/Output. Open-drain, 1-wire interface pin for slave 1.

1

C6

SWI2

Data Input/Output. Open-drain, 1-wire interface pin for slave 2.

B3

CSP

Slave-Charger Sense Current Positive Input. Option to add a 10mΩ sense resistor from CSP to CSN to have current sense information return to the master for processing. If slave charging is unused, short this pin to BATT.

1

C3

CSN

Slave-Charger Sense Current Negative Input. Option to add a 10mΩ sense resistor from CSP to CSN to have current sense information return to the master for processing. If slave charging is unused, short this pin to BATT.

J7

SAFEOUT

Safeout LDO Output. Default 4.9V and on when CHGIN power is valid. Bypass with a 1µF/10V ceramic capacitor to GND.

1

E8

V_IO

Digital I/O Supply Input for I²C interface

1

F9

SDA

I²C Serial Data

1

E9

SCL

I²C Serial Clock

1

D8

INTB

Interrupt Output. Active-low, open-drain output.

1

B1

THM

Thermistor Connection. Determine battery temperature using ratiometric measurement.

1

A2

THMB

Pullup voltage for THM pin pullup resistor that can be switched to save power.

1

C9

TEST1

Test I/O Pin. Ground this pin in the application.

V_CCTEST

B8

TEST2

Test I/O Pin. Ground this pin in the application.

1

B7

TEST3

Test I/O Pin. Ground this pin in the application.

1

B6

TEST4

Test I/O Pin. Ground this pin in the application.

1

B9

V_CCTEST

Test Mux Supply. Ground this pin in the application.

1

A7

DN

Common Negative Output 1. Connect to D- on mini/micro USB connector.

1

A8

DP

Common Positive Output2. Connect to D+ on mini/micro USB connector.

1

A6

CC1

Type-C CC pin 1, can be connected in parallel with USB power delivery transceiver.

A4

CC2

Type-C CC pin 2, can be connected in parallel with USB power delivery transceiver.

A5

V_CONNIN

5V power supply for supplying power to the unused CC pin if required.

B4

V_{CONNBTEN_SYS}

Output pin, used to enable external V_CONN boost.

F7, F8, G7, G8, G9, H7, H8, H9

NC1–NC8

No connection. Connect to GND.