24-Lead FC2QFN
| Package Code | F243A3F+1 |
| Outline Number | 21-100385 |
| Land Pattern Number | 90-100128 |
| Thermal Resistance, Four-Layer Board: | |
| Junction-to-Ambient (θJA) | 31°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 7.5°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Provides Drive To High-Side Internal nMOS. Connect a 0.1μF/6.3V bootstrap capacitor between this pin and the LX node.Charger Input Valid, Active-Low Logic Output Flag. Open-drain output indicates when valid voltage is present at CHGIN.Open-Drain Charge Status Indication Output. STAT is toggling low and high impedance during charge. STAT becomes low when top-off threshold is detected and in done state. STAT becomes high impedance when charge faults happen.USB Type-C CC2 ConnectionUSB Type-C CC1 ConnectionCommon Positive Output 1. Connect to D+ on USB Type-C or micro-USB connector.Common Negative Output 1. Connect to D- on USB Type-C or micro-USB connector.Active-High Logic Input. Enable/disable the reverse boost converter.Analog Ground. Short to ground plane.Output of On-Chip LDO Used to Power On-Chip, Low-Noise Circuits. Bypass with a 2.2µF/10V ceramic capacitor to GND. Powering external loads from VDD is not recommended other than pullup resistors.Thermistor Connection. Connect an external negative temperature coefficient (NTC) thermistor from THM to GND. Connect a resistor equal to the thermistor +25°C resistance from THM to PVL.Fast-Charge Current Setting Pin. Connect a resistor (RIFAST) from IFAST to GND to program the fast charge current. Use 24.9kΩ for 3.15A fast charge current. See the Application Information section.Battery Power Connection. Connect to the positive terminal of a single-cell (or parallel cell) Li-ion battery. Bypass BATT to PGND ground plane with a 10µF ceramic capacitor.System Power Node. Bypass SYS to PGND with a 2x10µF/10V ceramic capacitor.Output of On-Chip LDO, Noisy Rail due to Bootstrap Operation. Bypass with a 2.2µF/10V ceramic capacitor to PGND. Powering external loads from PVL is not recommended.Power Ground. Connect the return of the buck output capacitor close to these pins.Switching Node. Connect an inductor between LX and SYS. When the buck converter is enabled, LX switches between BYP and PGND to control the input current, battery current, battery voltage, and die temperature.System Power Connection. Output of OVP adapter input block and input to switching charger. Bypass with a 22µF/16V ceramic capacitor from BYP to PGND.Charger Input. Up to 13.7V operating, 16VDC withstand input pin connected to an adapter or USB power source. Connect a 2.2µF/16V ceramic capacitor from CHGIN to GND.