| 1 | BST | Provides Drive to High-Side Internal nMOS. Connect a 100nF/6.3V bootstrap capacitor between this pin and the LX node. |
| 2 | INOKB | Charger Input Valid, Active Low Logic Output Flag. Open-drain output indicates when valid voltage is present at CHGIN. |
| 3 | STAT | Open Drain Charge Status Indication Output. STAT toggles low and high impedance during charge. STAT becomes low when top-off threshold is detected and in done state. STAT becomes high impedance when charge faults occur. |
| 4 | CC2 | USB Type-C CC2 Connection |
| 5 | CC1 | USB Type-C CC1 Connection |
| 6 | DP | Common Positive Output 1. Connect to D+ on USB Type-C or micro USB connector. |
| 7 | DN | Common Negative Output 1. Connect to D- on USB Type-C or micro USB connector. |
| 8 | ENBST | Active High Logic Input. Enable/Disable the Reverse Boost Converter |
| 9 | GND | Analog Ground. Short to ground plane. |
| 10 | VDD | Output of On-Chip LDO Used to Power On-Chip, Low-Noise Circuits. Bypass with a 2.2µF/10V ceramic capacitor to GND. Powering external loads from VDD is not recommended other than pullup resistors. |
| 11 | ITOPOFF | Top Off Current Setting Pin. Connect a resistor (RTOPOFF) from ITOPOFF to GND to program the top-off current from 100mA to 350mA. Use 8.06kΩ for 100mA top-off current. The pin is also used to enable or disable the charger. See the Applications Information section. |
| 12 | IFAST | Fast Charge Current Setting Pin. Connect a resistor (RIFAST) from IFAST to GND to program the fast charge current. Use 24.9kΩ for 3.15A fast charge current. See the Applications Information section. |
| 13, 14 | BATT | Battery Power Connection. Connect to the positive terminal of a single-cell (or parallel cell) Li-ion battery. Bypass BATT to PGND ground plane with a 10µF ceramic capacitor. |
| 15, 16 | SYS | System Power Node. Bypass SYS to PGND with a 2x10µF/10V ceramic capacitor. |
| 17 | PVL | Output of On-Chip LDO, Noisy Rail Due to Bootstrap Operation. Bypass with a 2.2µF/10V ceramic capacitor to PGND. Powering external loads from PVL is not recommended. |
| 18, 19 | PGND | Power Ground. Connect the return of the buck output capacitor close to these pins. |
| 20, 21 | LX | Switching Node. Connect an inductor between LX and SYS. When the buck converter is enabled, LX switches between BYP and PGND to control the input current, battery current, battery voltage, and die temperature. |
| 22 | BYP | System Power Connection. Output of OVP adapter input block and input to switching charger. Bypass with 22µF/16V ceramic capacitor from BYP to PGND. |
| 23, 24 | CHGIN | Charger Input. Up to 13.7V operating, 16VDC withstand input pin connected to an adapter or USB power source. Connect a 2.2µF/16V ceramic capacitor from CHGIN to GND. |
