Application Circuits
Typical Application Circuits
Typical Applications Circuit
TemplateByTechPubs
General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO.
GPIO0
GPIO0
4.7µF 25V (0603)
4.7µF
25
V
(
0603)
Charger Input. Connect to a DC charging source. Bypass to GND with a 4.7μF ceramic capacitor.
CHGIN
CHGIN
VSYS
V
SYS
System Power Output. SYS provides power to the system resources as well as the control logic of the device. Connect to IN_SBB and bypass to GND with a 22μF ceramic capacitor.
SYS
SYS
Li+ Battery Connection. Connect to positive battery terminal. Bypass to GND with a 4.7μF ceramic capacitor.
BATT
BATT
+
+
LITHIUM ION BATTERY
LITHIUM ION
BATTERY
Thermistor Monitor. Thermally couple an NTC to the battery and connect between THM and GND. If not used, connect THM directly to ground.
THM
THM
Quiet Ground. Connect GND to PGND, and the low-impedance ground plane of the PCB.
GND
GND
VSYS
V
SYS
SIMO Power Input. Connect IN_SBB to SYS and bypass to PGND with a minimum of 10μF ceramic capacitor as close as possible to the IN_SBB pin.
IN_SBB
IN_SBB
Power ground for the SIMO low-side FETs. Connect PGND to GND, and the low-impedance ground plane of the PCB.
PGND
PGND
VSBB0
V
SBB
0
SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.
SBB0
SBB0
VSBB1
V
SBB
1
SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-boost. Bypass SBB1 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.
SBB1
SBB1
L 1.5µH
L
1
.5µH
CSYS 22µF/10V (0603)
C
SYS
22
µF/10V
(
0603)
Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is enabled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB.
LXA
LXA
Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB.
LXB
LXB
I2C Interface and GPIO Driver Power
VIO
V
IO
I2C Data
SDA
SDA
I2C Clock
SCL
SCL
Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between IRQ and a voltage equal to or less than VSYS.
nIRQ
nIRQ
VSBB0
V
SBB
0
Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO0 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected.
IN_LDO0
IN_LDO0
VLDO0
V
LDO
0
Linear Regulator Output 0. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO0 and connect this pin to ground or leave unconnected.
LDO0
LDO0
1µF 6.3V (0402)
1µF
6
.3V
(
0402)
Active-Low Enable Input. EN supports push-button or slide-switch configurations. If not used, connect EN to SYS and use the CNFG_SBBx_B.EN_SBBx[2:0] and CNFG_LDOx_B.EN_LDOx[2:0] bitfields to enable channels. Pulled up internally to VCCINT.
nEN
nEN
Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between RST and a voltage equal to or less than VSYS.
nRST
nRST
Internal Charger 3V Logic Supply Powered from CHGIN. Bypass to GND with a 1μF ceramic capacitor. Do not load VL externally.
VL
V
L
1µF 10V (0402)
1µF
10
V
(
0402)
VSBB2
V
SBB
2
SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.
SBB2
SBB2
22µF 10V (0603)
22µF
10
V
(
0603)
PROCESSOR
PROCESSOR
VIO/Power
V
IO
/
POWER
4.7µF 6.3V (0603)
4.7µF
6
.3V
(
0603)
Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power signals.
AMUX
AMUX
Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power signals.
AMUX
AMUX
ADC INPUT
ADC INPUT
SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 3300pF ceramic capacitor between BST and LXB.
BST
BST
Thermistor Bias Supply. Connect a resistor equal to the NTCs room temperature resistance between TBIAS and THM. Do not load TBIAS with any other external circuitry. If not used, leave the pin disconnected.
TBIAS
TBIAS
MAX77654
MAX77654
LITHIUM ION BATTERY CHARGER
LITHIUM ION BATTERY CHARGER
T
T
SIMO BUCK-BOOST
SIMO BUCK-BOOST
LDO
LDO
Analog Multiplexer
ANALOG
MULTIPLEXER
I2C
I
2
C
GPIO
GPIO
TOP LEVEL
TOP LEVEL
CBST 3300pF/6.3V (0201)
C
BST
3300
pF/6.3V
(
0201)
Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between RST and a voltage equal to or less than VSYS.
nRST
nRST
I2C Data
SDA
SDA
I2C Clock
SCL
SCL
Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between IRQ and a voltage equal to or less than VSYS.
nIRQ
nIRQ
SYSTEM RESOURCES
SYSTEM
RESOURCES
General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO.
GPIO0
GPIO0
Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power signals.
AMUX
AMUX
General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO.
GPIO0
GPIO0
*
*
*
*
*PULLUP RESISTORS NOT DRAWN
*PULLUP RESISTORS NOT DRAWN
DC Charging Source
DC CHARGING SOURCE
General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO.
GPIO1
GPIO1
General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO.
GPIO1
GPIO1
General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO.
GPIO1
GPIO1
Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO1 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected.
IN_LDO1
IN_LDO1
1µF 6.3V (0402)
1µF
6
.3V
(
0402)
VLDO1
V
LDO
1
Linear Regulator Output 1. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO1 and connect this pin to ground or leave unconnected.
LDO1
LDO1
General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO
GPIO2
GPIO2
General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO
GPIO2
GPIO2
