Pin Specifications

Pin Description
PIN	NAME	FUNCTION	TYPE
	C1, D3	NC	Not connected.
TOP LEVEL
A4	A4	V_IO	I²C Interface and GPIO Driver Power	Power Input
B3	B3	nEN	Active-Low Enable Input. EN supports push-button or slide-switch configurations. If not used, connect EN to SYS and use the CNFG_SBBx_B.EN_SBBx[2:0] and CNFG_LDOx_B.EN_LDOx[2:0] bitfields to enable channels. Pulled up internally to V_CCINT.	Digital Input
B2	B2	nIRQ	Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between IRQ and a voltage equal to or less than V_SYS.	Digital Output
A2	A2	nRST	Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between RST and a voltage equal to or less than V_SYS.	Digital Output
C2	C2	GPIO2	General Purpose Input/Output. The GPIO I/O stage is internally biased with V_IO	Digital I/O
A1	A1	GPIO1	General Purpose Input/Output. The GPIO I/O stage is internally biased with V_IO.	Digital I/O
B1	B1	GPIO0	General Purpose Input/Output. The GPIO I/O stage is internally biased with V_IO.	Digital I/O
B4	B4	SCL	I²C Clock	Digital Input
A3	A3	SDA	I²C Data	Digital I/O
C3	C3, D1, D2, E1	GND	Quiet Ground. Connect GND to PGND, and the low-impedance ground plane of the PCB.	Ground
CHARGER
E1	—	CHGIN	Charger Input. Connect to a DC charging source. Bypass to GND with a 4.7μF ceramic capacitor.	Power Input
E2	E2, E3	SYS	System Power Output. SYS provides power to the system resources as well as the control logic of the device. Connect to IN_SBB and bypass to GND with a 22μF ceramic capacitor.	Power Output
E3	—	BATT	Li+ Battery Connection. Connect to positive battery terminal. Bypass to GND with a 4.7μF ceramic capacitor.	Power I/O
D1	—	VL	Internal Charger 3V Logic Supply Powered from CHGIN. Bypass to GND with a 1μF ceramic capacitor. Do not load V_L externally.	Power Output
D3	—	TBIAS	Thermistor Bias Supply. Connect a resistor equal to the NTCs room temperature resistance between TBIAS and THM. Do not load TBIAS with any other external circuitry. If not used, leave the pin disconnected.	Analog
D2	—	THM	Thermistor Monitor. Thermally couple an NTC to the battery and connect between THM and GND. If not used, connect THM directly to ground.	Analog Input
C1	—	AMUX	Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power signals.	Analog Output
SIMO BUCK-BOOST
E4	E4	IN_SBB	SIMO Power Input. Connect IN_SBB to SYS and bypass to PGND with a minimum of 10μF ceramic capacitor as close as possible to the IN_SBB pin.	Power Input
C6	C6	SBB0	SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.	Power Output
C4	C4	SBB1	SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-boost. Bypass SBB1 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.	Power Output
D4	D4	SBB2	SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.	Power Output
D6	D6	BST	SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 3300pF ceramic capacitor between BST and LXB.	Power Input
D5, C5	D5, C5	LXB	Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB.	Power Input
E5	E5	LXA	Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is enabled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB.	Power I/O
E6	E6	PGND	Power ground for the SIMO low-side FETs. Connect PGND to GND, and the low-impedance ground plane of the PCB.	Ground
LDO
B6	B6	IN_LDO0	Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO0 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected.	Power Input
A6	A6	IN_LDO1	Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO1 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected.	Power Input
B5	B5	LDO0	Linear Regulator Output 0. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO0 and connect this pin to ground or leave unconnected.	Power Output
A5	A5	LDO1	Linear Regulator Output 1. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO1 and connect this pin to ground or leave unconnected.	Power Output

C1, D3

NC

Not connected.

A4

V_IO

I²C Interface and GPIO Driver Power

Power Input

B3

nEN

Active-Low Enable Input. EN supports push-button or slide-switch configurations. If not used, connect EN to SYS and use the CNFG_SBBx_B.EN_SBBx[2:0] and CNFG_LDOx_B.EN_LDOx[2:0] bitfields to enable channels.

Pulled up internally to V_CCINT.

Digital Input

B2

nIRQ

Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between IRQ and a voltage equal to or less than V_SYS.

Digital Output

A2

nRST

Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between RST and a voltage equal to or less than V_SYS.

Digital Output

C2

GPIO2

General Purpose Input/Output. The GPIO I/O stage is internally biased with V_IO

Digital I/O

A1

GPIO1

General Purpose Input/Output. The GPIO I/O stage is internally biased with V_IO.

Digital I/O

B1

GPIO0

General Purpose Input/Output. The GPIO I/O stage is internally biased with V_IO.

Digital I/O

B4

SCL

I²C Clock

Digital Input

A3

SDA

I²C Data

Digital I/O

C3

C3, D1, D2, E1

GND

Quiet Ground. Connect GND to PGND, and the low-impedance ground plane of the PCB.

Ground

E1

—

CHGIN

Charger Input. Connect to a DC charging source. Bypass to GND with a 4.7μF ceramic capacitor.

Power Input

E2

E2, E3

SYS

System Power Output. SYS provides power to the system resources as well as the control logic of the device. Connect to IN_SBB and bypass to GND with a 22μF ceramic capacitor.

Power Output

E3

—

BATT

Li+ Battery Connection. Connect to positive battery terminal. Bypass to GND with a 4.7μF ceramic capacitor.

Power I/O

D1

—

VL

Internal Charger 3V Logic Supply Powered from CHGIN. Bypass to GND with a 1μF ceramic capacitor. Do not load V_L externally.

Power Output

D3

—

TBIAS

Thermistor Bias Supply. Connect a resistor equal to the NTCs room temperature resistance between TBIAS and THM. Do not load TBIAS with any other external circuitry. If not used, leave the pin disconnected.

Analog

D2

—

THM

Thermistor Monitor. Thermally couple an NTC to the battery and connect between THM and GND. If not used, connect THM directly to ground.

Analog Input

C1

—

AMUX

Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power signals.

Analog Output

E4

IN_SBB

SIMO Power Input. Connect IN_SBB to SYS and bypass to PGND with a minimum of 10μF ceramic capacitor as close as possible to the IN_SBB pin.

Power Input

C6

SBB0

SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.

Power Output

C4

SBB1

SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-boost. Bypass SBB1 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.

Power Output

D4

SBB2

SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.

Power Output

D6

BST

SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 3300pF ceramic capacitor between BST and LXB.

Power Input

D5, C5

LXB

Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB.

Power Input

E5

LXA

Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is enabled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB.

Power I/O

E6

PGND

Power ground for the SIMO low-side FETs. Connect PGND to GND, and the low-impedance ground plane of the PCB.

Ground

B6

IN_LDO0

Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO0 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected.

Power Input

A6

IN_LDO1

Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO1 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected.

Power Input

B5

LDO0

Linear Regulator Output 0. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO0 and connect this pin to ground or leave unconnected.

Power Output

A5

LDO1

Linear Regulator Output 1. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO1 and connect this pin to ground or leave unconnected.

Power Output