Package Information

WLP

Package Code	N302C2+1
Outline Number	21-100307
Land Pattern Number	Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ_JA)	49ºC/W (2s2p board)

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

data-opMAX77654AENVN%2B

data-opMAX77654DENV%2B

data-opMAX77654DENV%2BT

data-opMAX77654MENV%2BT

data-opMAX77654MENV%2B

data-opMAX77654AENVN%2BT

data-opMAX77654FENV%2B

data-opMAX77654FENV%2BT

data-opMAX77654AENV%2B

data-opMAX77654BENV%2B

data-opMAX77654BENV%2BT

data-opMAX77654AENV%2BT

Not connected.I2C Interface and GPIO Driver PowerActive-Low Enable Input. EN supports push-button or slide-switch configurations. If not used, connect EN to SYS and use the CNFG_SBBx_B.EN_SBBx[2:0] and CNFG_LDOx_B.EN_LDOx[2:0] bitfields to enable channels. Pulled up internally to VCCINT.Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between IRQ and a voltage equal to or less than VSYS.Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between RST and a voltage equal to or less than VSYS.General Purpose Input/Output. The GPIO I/O stage is internally biased with VIOGeneral Purpose Input/Output. The GPIO I/O stage is internally biased with VIO.General Purpose Input/Output. The GPIO I/O stage is internally biased with VIO.I2C ClockI2C DataQuiet Ground. Connect GND to PGND, and the low-impedance ground plane of the PCB.Charger Input. Connect to a DC charging source. Bypass to GND with a 4.7μF ceramic capacitor.System Power Output. SYS provides power to the system resources as well as the control logic of the device. Connect to IN_SBB and bypass to GND with a 22μF ceramic capacitor.Li+ Battery Connection. Connect to positive battery terminal. Bypass to GND with a 4.7μF ceramic capacitor.Internal Charger 3V Logic Supply Powered from CHGIN. Bypass to GND with a 1μF ceramic capacitor. Do not load VL externally.Thermistor Bias Supply. Connect a resistor equal to the NTCs room temperature resistance between TBIAS and THM. Do not load TBIAS with any other external circuitry. If not used, leave the pin disconnected.Thermistor Monitor. Thermally couple an NTC to the battery and connect between THM and GND. If not used, connect THM directly to ground.Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power signals.SIMO Power Input. Connect IN_SBB to SYS and bypass to PGND with a minimum of 10μF ceramic capacitor as close as possible to the IN_SBB pin.SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-boost. Bypass SBB1 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-boost. Bypass SBB0 to PGND with a 10μF ceramic capacitor. If not used, see the Unused Outputs section.SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 3300pF ceramic capacitor between BST and LXB.Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB.Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is enabled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA and LXB.Power ground for the SIMO low-side FETs. Connect PGND to GND, and the low-impedance ground plane of the PCB.Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO0 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected.Linear Regulator Input. If connected to a SIMO output with a short trace, IN_LDO1 can share the output's capacitor. Otherwise, bypass with a 2.2μF ceramic capacitor to ground. If not used, connect to ground or leave unconnected.Linear Regulator Output 0. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO0 and connect this pin to ground or leave unconnected.Linear Regulator Output 1. Bypass with a 1.0μF ceramic capacitor to GND. If not used, disable LDO1 and connect this pin to ground or leave unconnected.