Detailed Description

The MAX77654 provides a highly-integrated battery charging and power management solution for low-power applications. The linear charger can charge various Li+ batteries with a wide range of charge current and charger termination voltage options. Temperature monitoring and JEITA compliance settings add additional functionality and safety to the charger.

Five regulators are integrated within this device (see Table 1). A single-inductor, multiple output (SIMO) buck-boost regulator efficiently provides three independently programmable power rails. Two 100mA low-dropout linear regulators (LDOs) provide ripple rejection for audio and other noise sensitive applications.

This device includes other features such as an analog multiplexer that switches several internal voltage and current signals to an external node for monitoring with an external ADC. A bidirectional I²C serial interface allows for configuring and checking the status of the device. An internal on/off controller provides regulator sequencing and supervisory functionality for the device.

Table 1. Regulator Summary
REGULATOR NAME	REGULATOR TOPOLOGY	MAXIMUM I_OUT (mA)	V_INRANGE	MAX77654 V_OUT RANGE/RESOLUTION
SBB0	SIMO	Up to 500*	2.7 to 5.5V	0.8 to 5.5V in 50mV steps
SBB1	SIMO	Up to 500*	2.7 to 5.5V	0.8 to 5.5V in 50mV steps
SBB2	SIMO	Up to 500*	2.7 to 5.5V	0.8 to 5.5V in 50mV steps
LDO0/1	PMOS LDOs	100	1.7 to 5.5V	0.8 to 3.975V in 25mV steps

*Shared capacity with other SBBx channels. See the SIMO Available Output Current section for more information.

Part Number Decoding

The MAX77654 has different one-time programmable (OTP) options and variants to support a variety of applications. OTP options set default settings such as output voltage or CHGIN current limit. Variants are versions of MAX77654 with different features. See Figure 1 for how to identify these. Table 2 and Table 3 list all available OTP options and variants. Refer to Maxim Integrated naming convention for more details.

Table 2. Variants Table
VARIANT LETTER	NONE	N
Supports Charger, Analog Multiplexer, and Thermistor?	Yes
Supports SIMO Buck-Boost Regulator?	Yes	Yes
Supports LDO/LSW?	Yes	Yes
Supports I²C Serial Communication?	Yes	Yes

Table 3. OTP Options Table
		OTP LETTER AND SETTINGS
	VARIANT	NONE							N
Block	Bit Field Name	A	B	C*	D	F	M	N	A
Global	SBIA_LPM (Bias Power Mode)	NPM	NPM	NPM	NPM	NPM	NPM	LPM	NPM
	DBEN_nEN (nEN Debounce time)	500μs	500μs	30ms	500μs	30ms	500μs	500us	500μs
	nEN_MODE	Push-Button	Push-Button	Push-Button	Push-Button	Push-Button	Push-Button	Push-Button	Slide-Switch
	T_MRST (Manual Reset Time)	8s	8s	8s	8s	16s	8s	8s	8s
	ALT_GPIO0 (GPIO0 Mode)	GPIO	Alt.	GPIO	GPIO	GPIO	GPIO	GPIO	GPIO
	ALT_GPIO1 (GPIO1 Mode)	GPIO	Alt.	GPIO	GPIO	GPIO	Alt.	GPIO	GPIO
	ALT_GPIO2 (GPIO2 Mode)	GPIO	Alt.	GPIO	GPIO	GPIO	Alt.	GPIO	GPIO
	ADDR (I²C Address (7-bit))	0x48	0x48	0x48	0x48	0x48	0x48	0x48	0x48
	UVLO_F[3:0] (SYSUVLO Falling)	2.60V	2.60V	2.85V	2.60V	2.60V	2.60V	2.60V	2.60V
	UVLO_H[3:0] (SYSUVLO Hysteresis)	0.30V	0.30V	0.30V	0.30V	0.15V	0.30V	0.30V	0.30V
	DIDM (Metal Option ID)	0b0	0b0	0b0	0b0	0b0	0b0	0b0	0b0
	CID[4:0] (Chip ID)	0x6	0x2	0x9	0xC	0x12	0xA	0x11	0x7

Watchdog	WDT_LOCK (Watchdog Timer Disable Lock)	Unlocked	Unlocked	Unlocked	Unlocked	Unlocked	Unlocked	Unlocked	Unlocked
Watchdog	WDT_EN (Watchdog Timer Enable)	Disabled	Disabled	Disabled	Disabled	Disabled	Disabled	Disabled	Disabled

SIMO	TV_SBB0[6:0] (SBB0 V_OUT)	1.800V	3.000V	4.000V	2.050V	0.800V	1.800V	2.050V	1.350V
	IP_SBB0[1:0] (SBB0 Inductor Current Peak Limit)	0.500A	1.000A	0.500A	0.500A	0.333A	0.500A	0.500A	1.000A
	OP_MODE (SBB0) (SBB0 Operating Mode)	Buck	Buck	Buck-Boost	Buck	Buck	Buck	Buck	Buck
	ADE_SBB0 (Active-Discharge Resistor Enable)	Enabled	Enabled	Enabled	Enabled	Disabled	Enabled	Enabled	Disabled
	EN_SBB0[2:0] (SBB0 Enable Control)	Off	Off	Off	FPS Slot 0	Off	On	FPS Slot 0	Off
	TV_SBB1[6:0] (SBB1 V_OUT)	1.800V	1.800V	1.800V	1.200V	1.850V	1.100V	3.300V	1.800V
	IP_SBB1[1:0] (SBB1 Inductor Current Peak Limit)	0.500A	1.000A	0.333A	0.500A	0.333A	0.500A	0.500A	1.000A
	OP_MODE (SBB1) (SBB1 Operating Mode)	Buck	Buck	Buck	Buck	Buck	Buck	Buck-Boost	Buck
	ADE_SBB1 (Active-Discharge Resistor Enable)	Enabled	Enabled	Enabled	Enabled	Disabled	Enabled	Enabled	Disabled
	EN_SBB1[2:0] (SBB1 Enable Control)	FPS Slot 0	On	FPS Slot 0	FPS Slot 3	On	On	FPS Slot 0	FPS Slot 0
	TV_SBB2[6:0] (SBB2 V_OUT)	3.500V	3.500V	4.000V	3.300V	0.800V	3.300V	3.300V	3.300V
	IP_SBB2[1:0] (SBB2 Inductor Current Peak Limit)	0.333A	1.000A	0.333A	0.500A	0.333A	1.000A	0.500A	1.000A
	OP_MODE (SBB2) (SBB2 Operating Mode)	Buck-Boost	Buck-Boost	Buck-Boost	Buck-Boost	Buck	Buck-Boost	Buck-Boost	Buck-Boost
	ADE_SBB2 (Active-Discharge Resistor Enable)	Enabled	Enabled	Disabled	Enabled	Disabled	Enabled	Enabled	Enabled
	EN_SBB2[2:0] (SBB2 Enable Control)	Off	Off	Off	FPS Slot 0	Off	On	FPS Slot 0	FPS Slot 3

LDO	TV_LDO0[6:0] (LDO0 V_OUT)	1.800V	1.800V	1.800V	1.850V	0.800V	1.600V	1.850V	1.200V
	LDO0_MD (LDO or LSW Mode)	LDO	LDO	LDO	LDO	LDO	LDO	LDO	LDO
	ADE_LDO0 (Active-Discharge Resistor Enable)	Enabled	Enabled	Enabled	Enabled	Disabled	Enabled	Enabled	Enabled
	EN_LDO0[2:0] (LDO0 Enable Control)	FPS Slot 0	Off	Off	FPS Slot 1	Off	FPS Slot 3	FPS Slot 1	FPS Slot 1
	TV_LDO1[6:0] (LDO1 V_OUT)	3.000V	Don't Care	3.000V	Don't Care	0.800V	Don't Care	1.850V	1.350V
	LDO1_MD (LDO or LSW Mode)	LDO	LSW	LDO	LSW	LDO	LSW	LDO	LDO
	ADE_LDO1 (Active-Discharge Resistor Enable)	Enabled	Enabled	Enabled	Disabled	Disabled	Enabled	Enabled	Disabled
	EN_LDO1[2:0] (LDO1 Enable Control)	Off	Off	Off	Off	Off	FPS Slot 2	FPS Slot 1	Off

Charger	CHG_EN (Charger Enable)	Enabled	Enabled	Enabled	Disabled	Enabled	Enabled	Enabled
Charger	ICHGIN_LIM_DEF (Default Charger Input Current Limit)	95mA	95mA	95mA	475mA	475mA	475mA	95mA

*Future OTP option. Contact Maxim Integrated for availability.

Support Material

The following support materials are available for this device:

MAX77654 Register Map: Full table of registers that can be read from or written to by I²C.
MAX77654 Programmer's Guide: Basic software implementation guidance.
MAX77654 SIMO Calculator: Tool to estimate supported maximum current and ripple for specified conditions.

Top-Level Interconnect Simplified Diagram

Figure 2 shows the same major blocks as the Typical Applications Circuit with an increased emphasis on the routing between each block. This diagram is intended to familiarize the user with the landscape of the device. Many of the details associated with these signals are discussed throughout the data sheet. At this stage of the data sheet, note the addition of the main bias and clock block that are not shown in the Typical Applications Circuit section. The main bias and clock block provides voltage, current, and clock references for other blocks as well as many resources for the top-level digital control.

Detailed Description—Global Resources

The global resources encompass a set of circuits that serve the entire device and ensure safe, consistent, and reliable operation.

Features and Benefits

Voltage Monitors
- SYS POR (power-on-reset) comparator generates a reset signal upon power-up.
- SYS undervoltage ensures repeatable behavior when power is applied to and removed from the device.
- SYS overvoltage monitor inhibits operation with overvoltage power sources to ensure reliability in faulty environments.
Thermal Monitors
- +165°C junction temperature shutdown
Manual Reset
- 8s or 16s period
Wake-up Events
- Charger insertion (with 120ms debounce)
- nEN input assertion
Interrupt Handler
- Interrupt output (nIRQ)
- All interrupts are maskable
Push-Button/Slide-Switch On-key (nEN)
- Configurable push-button/slide-switch functionality
- 500μs or 30ms debounce timer interfaces directly with mechanical switches
On/Off Controller
- Startup/shut-down sequencing
- Programmable sequencing delay
GPIO, RST Digital I/Os

Voltage Monitors

The device monitors the system voltage (V_SYS) to ensure proper operation using three comparators (POR, UVLO, and OVLO). These comparators include hysteresis to prevent their outputs from toggling between states during noisy system transitions.

SYS POR Comparator

The SYS POR comparator monitors V_SYS and generates a power-on reset signal (POR). When V_SYS is below V_POR, the device is held in reset (SYSRST = 1). When V_SYS rises above V_POR, internal signals and on-chip memory stabilize and the device is released from reset (SYSRST = 0).

SYS Undervoltage-Lockout Comparator

The SYS undervoltage-lockout (UVLO) comparator monitors V_SYS and generates a SYSUVLO signal when the V_SYS falls below UVLO threshold. The SYSUVLO signal is provided to the top-level digital controller. See Figure 6 and Table 6 for additional information regarding the UVLO comparator:

When the device is in the STANDBY state, the UVLO comparator is disabled.
When transitioning out of the STANDBY state, the UVLO comparator is enabled allowing the device to check for sufficient input voltage. If the device has sufficient input voltage, it can transition to the RESOURCE ON state; if there is insufficient input voltage, the device transitions back to the STANDBY state.

SYS Overvoltage-Lockout Comparator

The device is rated for 5.5V maximum operating voltage (V_SYS) with an absolute maximum input voltage of 6.0V. An overvoltage-lockout monitor increases the robustness of the device by inhibiting operation when the supply voltage is greater than V_SYSOVLO. See Figure 6 and Table 6 for additional information regarding the OVLO comparator:

When the device is in the STANDBY state, the OVLO comparator is disabled.

Chip Identification

The MAX77654 offers different one-time-programmable (OTP) options to, for example, set the default output voltages. These options are identified by the chip identification number, which can be read in the CID register.

nEN Enable Input

nEN is an active-low internally debounced digital input that typically comes from the system’s on-key. The debounce time is programmable with CNFG_GLBL.DBEN_nEN. The primary purpose of this input is to generate a wake-up signal for the PMIC that turns on the regulators. Maskable rising/falling interrupts are available for nEN (INT_GLBL0.nEN_R and INT_GLBL0.nEN_F) for alternate functionality.

The nEN input can be configured to work either with a push-button (CNFG_GLBL.nEN_MODE = 0) or a slide-switch (CNFG_GLBL.nEN_MODE = 1). See Figure 3 for more information. In both push-button mode and slide-switch mode, the on/off controller looks for a falling edge on the nEN input to initiate a power-up sequence.

nEN Manual Reset

nEN works as a manual reset input when the on/off controller is in the "Resource-On" state. The manual reset function is useful for forcing a power-down in case communication with the processor fails. When nEN is configured for push-button mode and the input is asserted (nEN = LOW) for an extended period (t_MRST), the on/off controller initiates a power-down sequence and goes to standby mode. When nEN is configured for slide-switch mode and the input is deasserted (nEN = HIGH) for an extended period (t_MRST), the on/off controller initiates a power-down sequence and goes to standby mode.

nEN Dual-Functionality: Push-Button vs. Slide-Switch

The nEN digital input can be configured to work with a push-button or a slide-switch. The timing diagram below shows nENs dual functionality for power-on sequencing and manual reset. The default configuration of the device is push-button mode (CNFG_GLBL.nEN_MODE = 0) and no additional programming is necessary. Applications that use a slide-switch on-key configuration must set CNFG_GLBL.nEN_MODE = 1 within t_MRST.

nEN Internal Pullup Resistors to V_CCINT

The nEN logic thresholds are referenced to V_CCINT, an always-on internal voltage domain. There are internal pullup resistors between nEN and V_CCINT (R_{nEN_PU}), which can be configured with the CNFG_GLBL_A.PU_DIS bit. See Figure 4. While PU_DIS = 0, the pullup value is approximately 200kΩ. While PU_DIS = 1, the pullup value is 10MΩ.

V_CCINT defined by the following conditions:

V_CCINT = V_L (3V typ.) if CHGIN is valid (STAT_CHG_B.CHGIN_DTLS[1:0] = 0b11) and not USB suspended (CNFG_CHG_G.USBS = 0).
V_CCINT = V_BATT if CHGIN is invalid (STAT_CHG_B.CHGIN_DTLS[1:0] ≠ 0b11) or CHGIN is valid but USB suspended (CNFG_CHG_G.USBS = 1).

Applications using a slide-switch on-key or push-pull digital output connected to nEN can reduce quiescent current consumption by changing pullup strength to 10MΩ. Applications using normally-open, momentary, and push-button on-keys (as shown in Figure 4) do not create this leakage path and should use the stronger 200kΩ pullup option.

Figure 4. nEN Pullup Resistor Configuration

Interrupts (nIRQ)

nIRQ is an active-low, open-drain output that is typically routed to the host processor's interrupt input to signal an important change in device status. See the Register Map section for a comprehensive list of all interrupt bits and status registers.

A pullup resistor to a voltage less than or equal to V_SYS is required for this node. nIRQ is the logical NOR of all unmasked interrupt bits in the register map.

All interrupts are masked by default. Masked interrupt bits do not cause the nIRQ pin to change. Unmask the interrupt bits to allow nIRQ to assert.

Reset Output (nRST)

nRST is an open-drain, active-low output that is typically used to hold the processor in a reset state when the device is powered down. During a power-up sequence, the nRST deasserts after the last regulator in the power-up chain is enabled (t_RSTODD). During a power-down sequence, the nRST output asserts before any regulator is powered down (t_RSTOAD). See Figure 10 for nRST timing.

A pullup resistor to a voltage less than or equal to V_SYS is required for this node.

General-Purpose Input Output (GPIO)

The provided general-purpose input/output (GPIO) pins increase system flexibility. See Figure 5 for more details.

Clear CNFG_GPIOx.DIR to configure GPIO as a general-purpose output (GPO). The GPO can either be in push-pull mode (CNFG_GPIOx.DRV = 1) or open-drain mode (CNFG_GPIOx.DRV = 0).

The push-pull output mode is ideal for applications that need fast (~2ns) edges and low power consumption.
The open-drain mode requires an external pullup resistor (typically 10kΩ–100kΩ). Connect the external pullup resistor to a bias voltage that is less than or equal to V_IO.
- The open-drain mode can be used to communicate to different logic domains. For example, to send a signal from the GPO on a 1.8V logic domain (V_IO = 1.8V) to a device on a 1.2V logic domain, connect the external pullup resistor to 1.2V.
- The open-drain mode can be used to connect several open-drain (or open-collector) devices together on the same bus to create wired logic (wired AND logic is positive-true; wired OR logic is negative-true).
The general-purpose input (GPI) functions are still available while the pin is configured as a GPO. In other words, the CNFG_GPIOx.DI (input status) bit still functions and does not collide with the state of the CNFG_GPIOx.DIR bit.

Set CNFG_GPIOx.DIR to have the GPIO function as a GPI. The GPI features a 30ms debounce timer (t_{DBNC_GPI}) that can be enabled or disabled with DBEN_GPI.

Enable the debounce timer (CNFG_GPIOx.DBEN_GPI = 1) if the GPI is connected to a device that can bounce or chatter, like a mechanical switch.
If the GPI is connected to a circuit with clean logic transitions and no risk of bounce, disable the debounce timer (CNFG_GPIOx.DBEN_GPI = 0) to eliminate logic delays. With no debounce timer, the GPI input logic propagates to nIRQ in 10ns.

A dedicated internal oscillator is used to create the 30ms (t_{DBNC_GPI}) debounce timer. To obtain low V_IO supply current, ensure the GPIO voltage is either logic high or logic low. If the GPIO pin is unconnected (either as a GPI or an open-drain GPO) and V_IOis powered, the GPIO voltage trends towards the logic level gray area (0.3 x V_IO< V_GPIO < 0.7 x V_IO). If V_GPIO is in the gray area, V_IO current can be more than 10μA.

The GPI features edge detectors that feed into the the top-level interrupt system of the chip. This allows software to use interrupts to service events associated with a GPI change instead of polling for these changes.

If the application wants nIRQ to go low only on a GPI rising edge, then it should clear the GPI rising edge interrupt mask bit (INTM_GLBL1.GPI_RM = 0) and set the GPI falling edge interrupt mask bit (INTM_GLBL1.GPI_FM = 1).
If the application wants nIRQ to go low only on a GPI falling edge, then it should set the GPI rising edge interrupt mask bit (INTM_GLBL1.GPI_RM = 1) and clear the GPI falling edge interrupt mask bit (INTM_GLBL1.GPI_FM = 0).
If the application wants nIRQ to go low on both GPI falling and rising edges, then it should clear the GPI rising edge interrupt mask bit (INTM_GLBL1.GPI_RM = 0) and clear the GPI falling edge interrupt mask bit (INTM_GLBL1.GPI_FM = 0).

Alternate Mode

Each GPIO in the MAX77654 can be configured to have a different function. Whether a particular GPIO is in GPIO mode or alternate mode can be checked by reading the CNFG_GPIOx.ALT_GPIOx bit. Table 4 summarizes the alternate functions for each GPIO.

Table 4. GPIO Mode
GPIOx	CNFG_GPIOx REGISTER
GPIOx	ALT_GPIOx = 0	ALT_GPIOx = 1
GPIO0	Standard GPIO	Active-high output of SBB2s flexible power sequencer (FPS) slot.
GPIO1	Standard GPIO	Active-high input, enable control for SBB2. SBB2 also still powers up and down according to the FPS.
GPIO2	Standard GPIO	Active-high input, enable control for low-power mode.

In particular, for GPIO1s alternate mode, SBB2 is enabled if GPIO1 = 1 OR the FPS enables SBB2. See the Flexible Power Sequencer section for more details. Table 5 summarizes how to enable or disable SBB2 if GPIO1 is configured to be in its alternate mode.

The value of GPIO2 is OR'd with CNFG_GLBL.SBIA_LPM, so setting SBIA_LPM = 1 or setting GPIO2 HIGH requests bias lower-power mode.

Table 5. Enabling/Disabling SBB2 while GPIO1 is in Alternate Mode
GPIO1	CNFG_SBB2.EN_SBB2[2:0]
GPIO1		0b000 - 0b011, 0b110, 0b111	0b100 to 0b0101
GPIO1 = 0	SBB2 Enabled	SBB2 Disabled
GPIO1 = 1	SBB2 Enabled	SBB2 Enabled

On/Off Controller

The on/off controller monitors multiple power-up (wake-up) and power-down (shutdown) conditions to enable or disable resources that are necessary for the system and its processor to move between its operating modes.

Many systems have one power management controller and one processor and rely on the on/off controller to be the master controller. In this case, the on/off controller receives wake-up events and enables some or all of the regulators to power-up a processor. That processor then manages the system. To conceptualize this master operation, see Figure 6 and Table 6. A typical path through the on/off controller is:

Apply a battery and start in the shutdown state.
Press the system's on-key (nEN = LOW) and follow transitions 4 and 6 to the resource-on state. If any resources are on the FPS, transitions 7A and 7B are followed.
The device performs its desired functions in the resource-on state. when it is ready to turn off, a manual reset first drives the transition through transitions 8A and 8B to the standby state. Afterward, the device automatically follows transition 3 to the shutdown state.

Some systems have several power management blocks, a main processor, and subprocessors. These systems can use this device as a subpower management block for a peripheral portion of circuitry as long as there is an I²C port available from a higher level processor. To conceptualize this operation, see Figure 6 and Table 6. A typical path through the on/off controller used in this way is:

Apply a battery to the system and start in the shutdown state.
When the higher level processor wants to turn on this device's resources, it enables the main bias circuits through I²C (CNFG_GLBL.SBIA_EN = 1) to transition along path 6 to the resource-on state.
The higher level processor can now control this device's resources with I²C commands, e.g., turn on/off regulators.
When the higher level processor is ready to turn this device off, it turns off everything through I²C and then disables the main bias circuits through I²C (CNFG_GLBL.SBIA_EN = 0) to transition along path 5B to the standby state.

Note that in this style of operation, the CNFG_GLBL_SFT_CTRL[1:0] bits should not be used to turn the device off. The CNFG_GLBL_SFT_CTRL[1:0] bits establish directives to the on/off controller itself that does not make sense in this subpower management block operation. If the processor uses I²C commands to enable the device's resources, the processor should also use I²C commands to disable them.

Top Level On/Off Controller

On/Off Controller Transition Table

Table 6. On/Off Controller Transition/State
TRANSITION	CONDITION (TRANSITION HAPPENS WHEN...)
0A	Software cold reset (CNFG_GLBL.SFT_CTRL[1:0] = 0b01) OR Watchdog timer expired and caused reset (ERCFLAG.WDT_RST = 1, CNFG_WDT.WDT_MODE = 1)
0B	Reset actions completed
0C	Software power-off (CNFG_GLBL.SFT_CTRL[1:0] = 0b10) OR Watchdog expired and caused power-off (ERCFLAG.WDT_OFF = 1, CNFG_WDT.WDT_MODE = 0) OR Chip over-temperature lockout (T_J > T_OTLO) OR SYS undervoltage lockout (V_SYS < V_SYSUVLO + V_{SYSUVLO_HYS}) OR SYS overvoltage lockout (V_SYS > V_SYSOVLO) OR Manual reset occurred (ERCFLAG.MRST = 1)
0D	Off actions completed
1	CHGIN inserted and 120ms debounce valid (STAT_CHG_B.CHGIN_DTLS[1:0] = 0b11) OR nEN asserted and debounced (t_FSM-DB) OR Power to the IC is removed (V_BATT < approx. 1.6V) and then reapplied (V_BATT > V_POR)
2	Factory-ship mode requested (CNFG_GLBL.SFT_CTRL[1:0] = 0b11) AND nEN not asserted
3	NOT (Transition 4) Factory-ship mode requested (CNFG_GLBL.SFT_CTRL[1:0] = 0b11) OR Software cold reset (CNFG_GLBL.SFT_CTRL[1:0] = 0b01) OR Software power-off (CNFG_GLBL.SFT_CTRL[1:0] = 0b10) OR Watchdog timer expired OR Manual reset occurred (ERCFLAG.MRT = 1)
4	Main bias requested enabled through I²C (CNFG_GLBL.SBIA_EN = 1) OR Transition 6
5A	Chip over-temperature lockout (T_J > T_OTLO) OR SYS undervoltage lockout (V_SYS < V_SYSUVLO + V_{SYSUVLO_HYS}) OR SYS overvoltage lockout (V_SYS > V_SYSOVLO)
5B	NOT (Transition 6) OR Factory-ship mode requested (CNFG_GLBL.SFT_CTRL[1:0] = 0b11) OR Software cold reset (CNFG_GLBL.SFT_CTRL[1:0] = 0b01) OR Software power-off (CNFG_GLBL.SFT_CTRL[1:0] = 0b10) OR Watchdog timer expired OR Manual reset occurred (ERCFLAG.MRT = 1)
6	AMUX is being used (CNFG_CHG_I.MUX_SEL[3:0] ≠ 0b0000) OR CHGIN inserted and debounced (STAT_CHG_B.CHGIN_DTLS[1:0] = 0b11) OR Any resources force enabled OR Internal wake-up flags are set (see the Internal Wake-Up Flags section)
7A	FPS power-up sequence has not happened yet AND Resources are not forced off AND Internal wake-up flags are set (see the Internal Wake-Up Flags section)
7B	FPS power-up sequence done
8A	FPS power-up sequence completed AND All resources are force disabled OR Factory-ship mode requested (CNFG_GLBL.SFT_CTRL[1:0] = 0b11) OR Software cold reset (CNFG_GLBL.SFT_CTRL[1:0] = 0b01) OR Software power-off (CNFG_GLBL.SFT_CTRL[1:0] = 0b10) OR Watchdog timer expired OR Manual reset occurred (ERCFLAG.MRT = 1)
8B	FPS power-down sequence finished

Internal Wake-Up Flags

After transitioning to the shutdown state because of a reset, to allow the device to power-up again, internal wake-up flags are set to remember the wake-up request. In Figure 6 and Table 6, these internal wake-up flags trigger transitions 6 and 7A. The internal wake-up flags are set when any of the following happen:

nEN is debounced (see the nEN Enable Input section)
- For example, after a push-button is pressed or a slide-switch switched to HIGH.
CHGIN is debounced and valid (STAT_CHG_B.CHGIN_DTLS[1:0] = 0b11)
Software cold reset command sent (CNFG_GLBL.SFT_CTRL[1:0] = 0b01)

Reset and Off Sequences

Figure 7. On/Off Controller Reset and Off-Action Sequences

Power-Up/Down Sequence

Flexible Power Sequencer (FPS)

The FPS allows resources to power up under hardware or software control. Additionally, each resource can power up independently or among a group of other regulators with adjustable power-up/down delays (sequencing). Figure 9 shows four resources powering up under the control of the flexible power sequencer.

The flexible sequencing structure consists of one master sequencing timer and four slave resources (SBB0, SBB1, SBB2 and LDO). When the FPS is enabled, a master timer generates four sequencing events for device power-up/down.

Figure 9. Flexible Power Sequencer Basic Timing Diagram

Startup Timing Diagram Due to nEN

Startup Timing Diagram Due to Charge Source Insertion

Force Enabled/Disabled Channels

Force enable SIMO and LDO output channels by setting CNFG_SBBx_B.EN_SBBx[2:0] (SIMO) or CNFG_LDOx_B.EN_LDOx[2:0] (LDO) = 0x6. Depending on the OTP, output channels may already be force enabled by default. Output channels configured this way are independent of the flexible power sequence and start up as soon as SYS > UVLO rising. The main bias also automatically turns on.

Likewise, output channels can be force disabled by setting EN_SBBx[2:0] or EN_LDOx[2:0] = 0x4.

Factory-Ship Mode State

Factory-ship mode internally disconnects the battery (BATT) from the system (SYS). The battery does not power the system in this mode. Use this mode to preserve battery life if external circuits on SYS cause the battery to leak.

Write CNFG_GLBL.SFT_CTRL[1:0] = 0b11 using I²C to enter factory-ship mode. The IC responds in two different ways depending on the state of the charger input (CHGIN):

If CHGIN is valid (STAT_CHG_B.CHGIN_DTLS[1:0] = 0b11) while CNFG_GLBL.SFT_CTRL[1:0] = 0b11, then the IC enters factory-ship mode (internally disconnects BATT from SYS) but SYS is still powered from CHGIN (regulating to V_SYS-REG). SYS decays to 0V when CHGIN is disconnected.
If CHGIN is invalid (STAT_CHG_B.CHG_DTLS[1:0] ≠ 0b11) while CNFG_GLBL.SFT_CTRL[1:0] = 0b11, then the IC enters factory-ship mode and SYS decays to 0V.

Factory-ship mode causes many configuration registers to reset (SYSRST). See the Register Map section for details. I²C reads and writes cannot happen in factory-ship mode.

Factory-ship mode exits only after SYS decays below approximately 1.8V. Once this condition is met, there are two ways to exit factory-ship mode:

Apply a valid DC source at CHGIN for t_CHGIN-DB (120ms typical). Factory-ship mode is unlatched (exited) when the charger input becomes valid from a previously invalid state (STAT_CHG_B.CHGIN_DTLS[1:0] = 0b00 → 0b11).
Assert nEN for t_FSM-EXDB(250ms typical) + t_{DBNC_nEN}.

Furthermore, this state is unlatched if power is removed from the IC (BATT voltage falls below approximately 1.8V). In all exit cases, the smart power selector controls the interaction between BATT and SYS until factory-ship mode is entered again (see the Smart Power Selector section).

Debounced Inputs (nEN, GPI, CHGIN)

nEN, CHGIN, and GPIO (when operating as an input), are debounced on both rising and falling edges to reject undesired transitions. The input must be at a stable logic level for the entire debounce period for the output to change its logic state. Figure 12 shows an example timing diagram for the nEN debounce.

Watchdog Timer (WDT)

The IC features a watchdog timer function for operational safety. If this timer expires without being cleared, the on/off controller causes the IC to enter the shutdown state and resets configuration registers. See the On/Off Controller and On/Off Controller Transition Table sections (transitions 0A and 0C) for more details.

Write CNFG_WDT.WDT_EN = 1 through I²C to enable the timer. The watchdog timer period (t_WD) is configurable from 16 to 128 seconds in 4 steps with CNFG_WDT.WDT_PER[1:0]. The default timer period is 128 seconds. While the watchdog timer is enabled, the CNFG_WDT.WDT_CLR bit must be set through I²C periodically (within t_WD) to reset the timer and prevent shutdown. See the Register Map and Figure 13 for additional details.

The timer can be factory-programmed to be enabled by default, disabled by default, or locked from accidental disable. The CNFG_WDT.WDT_LOCK bit is read-only and must be configured at the factory. See Table 7 for a full description.

Table 7. Watchdog Timer Factory-Programmed Safety Options
WDT_LOCK	WDT_EN	FUNCTION
0	0	Watchdog timer is disabled by default. Timer can be enabled or disabled by I²C writes.
0	1	Watchdog timer is enabled by default. Timer can be enabled or disabled by I²C writes.
1	0	Watchdog timer is disabled by default. Timer can be enabled by an I²C write, but only a SYSRST can reset the CNFG_WDT.WDT_EN value back to 0. Timer can not be disabled by direct I²C writes to CNFG_WDT.WDT_EN (write from 1 → 0 is ignored, write from 0 → 1 is accepted).
1	1	Watchdog timer is enabled by default. Nothing can disable the timer.

Detailed Description—Smart Power Selector Charger

The linear Li+ charger implements power path with Maxim's Smart Power Selector. This allows separate input current limit and battery charge current settings. Batteries charge faster under the supervision of the Smart Power Selector because charge current is independently regulated and not shared with variable system loads. See the Smart Power Selector section for more information.

The programmable constant-current charge rate (7.5mA to 300mA) supports a wide range of battery capacities. The programmable input current limit (95mA to 475mA) supports a range of charge sources, including USB. The charger's programmable battery regulation voltage range (3.6V to 4.6V) supports a wide variety of cell chemistries. Small battery capacities are supported; the charger accurately terminates charging by detecting battery currents as low as 0.375mA.

Additionally, the robust charger input withstands overvoltages up to 28V. To enhance charger safety, an NTC thermistor provides temperature monitoring in accordance with the JEITA recommendations. See the Adjustable Thermistor Temperature Monitors section for more information.

Charger Symbol Reference Guide

Table 8 lists the names and functions of charger-specific signals and if they can be programmed through I²C serial communication. See the Electrical Characteristics and Register Map for more information.

Table 8. Charger Quick Symbol Reference Guide
SYMBOL	NAME	I²C PROGRAMMABLE?
V_{CHGIN_OVP}	CHGIN overvoltage threshold	No
V_{CHGIN_UVLO}	CHGIN undervoltage-lockout threshold	No
V_CHGIN-MIN	Minimum CHGIN voltage regulation setpoint	Yes, through CNFG_CHG_B.VCHGIN_MIN[2:0]
I_CHGIN-LIM	CHGIN input current limit	Yes, through CNFG_CHG_B.ICHGIN_LIM[2:0]
V_SYS-REG	SYS voltage regulation target	Yes, through CNFG_CHG_D.VSYS_REG[4:0]
V_SYS-MIN	Minimum SYS voltage regulation setpoint	No, tracks V_SYS-REG
V_FAST-CHG	Fast-charge constant-voltage level	Yes, through CNFG_CHG_G.CHG_CV[5:0]
I_FAST-CHG	Fast-charge constant-current level	Yes, through CNFG_CHG_G_E.CHG_CC[5:0]
I_PQ	Prequalification current level	Yes, through CNFG_CHG_B.I_PQ
V_PQ	Prequalification voltage threshold	Yes, through CNFG_CHG_C.CHG_PQ[2:0]
I_TERM	Termination current level	Yes, through CNFG_CHG_C.I_TERM[1:0]
T_J-REG	Die temperature regulation setpoint	Yes, through CNFG_CHG_D.TJ_REG[2:0]
t_PQ	Prequalification safety timer	No
t_FC	Fast-charge safety timer	Yes, through CNFG_CHG_E.T_FAST_CHG[1:0]
t_TO	Top-off timer	Yes, through CNFG_CHG_C.T_TOPOFF[2:0]

Figure 14 indicates the high-level functions of each control circuit within the linear charger.

Figure 14. Charger Simplified Control Loops

Smart Power Selector

The Smart Power Selector seamlessly distributes power from the input (CHGIN) to the battery (BATT) and the system (SYS). The Smart Power Selector basic functions are:

When the system load current is less than the input current limit, the battery is charged with residual power from the input.
When a valid input source is connected, the system regulates to V_SYS-REG to power system loads regardless of the battery's voltage (instant on).
When the system load current exceeds the input current limit, the battery provides additional current to the system (supplement mode).
When the battery is finished charging and an input source is present to power the system, the battery remains disconnected from the system.
When the battery is connected and there is no input power, the system is powered from the battery.

Input Current Limiter

The input current limiter limits CHGIN current to not exceed I_CHGIN-LIM (programmed by CNFG_CHG_B.ICHGIN_LIM[2:0]). A maskable interrupt (INT_CHG.CHGIN_CTRL_I) signals when the input current limit engages. The STAT_CHG_A.ICHGIN_LIM_STAT bit reflects the state of the current limiter loop.

The default value of I_CHGIN-LIM is factory-programmable to either 95mA or 475mA. The decoding of the CNFG_CHG_B.ICHGIN_LIM[2:0] bitfield changes depending on the factory-programmed default value (see Table 9). The reset value of this bitfield is always 0b000 regardless of factory option.

Table 9. Input Current Limit Factory Options
ICHGIN_LIM[2:0]	95mA Factory-Default	475mA Factory-Default
0b000	95mA	475mA
0b001	190mA	380mA
0b010	285mA	285mA
0b011	380mA	190mA
0b100 to 0b111	475mA	95mA

CHGIN is capable of withstanding a maximum of 28V with respect to ground. CHGIN suspends power delivery to the system and battery when V_CHGIN exceeds V_{CHGIN_}_OVP (7.5V, typ). The input circuit also suspends when V_CHGIN falls below V_{CHGIN_}_UVLO minus 500mV of hysteresis (3.5V, typ). While in OVP or UVLO, the charger remains off and the battery provides power to the system.

Power transfer to SYS is delayed by a 120ms debounce timer (t_CHGIN-DB) after a valid DC source is connected to CHGIN. SYS does not begin regulating to V_SYS-REG until after the timer expires.

The STAT_CHG_B.CHGIN_DTLS[1:0] bitfield continuously indicates the state of CHGINs voltage quality. A maskable interrupt (INT_CHG.CHGIN_I) asserts when STAT_CHG_B.CHGIN_DTLS[1:0] changes.

Minimum Input Voltage Regulation

In the event of a poor-quality charge source, the minimum input voltage regulation loop works to reduce input current if V_CHGIN falls below V_CHGIN-MIN (programmed by CNFG_CHG_B.VCHGIN_MIN[2:0]). This is important because many commonly used charge adapters feature foldback protection mechanisms where the adapter completely shuts off if its output drops too low. The minimum input voltage regulation loop also prevents V_CHGIN from dropping below V_{CHGIN_}_UVLO if the cable between the charge source and the charger's input is long or highly resistive.

The input voltage regulation loop improves performance with current limited adapters. If the charger’s input current limit is programmed above the current limit of the given adapter, the input voltage loop allows the input to regulate at the current limit of the adapter. The input voltage regulation loop also allows the charger to perform well with adapters that have poor transient load response times.

A maskable interrupt (INT_CHG.CHGIN_CTRL_I) signals when the minimum input voltage regulation loop engages. The state of this loop is reflected by STAT_CHG_A.VCHGIN_MIN_STAT.

Minimum System Voltage Regulation

The minimum system voltage regulation loop ensures that the system rail remains close to the programmed SYS regulation voltage (V_SYS-REG) regardless of system loading. The loop engages when the combined battery charge current and system load current causes the CHGIN input to current limit at I_CHGIN-LIM. When this happens, the minimum system voltage loop reduces charge current in an attempt to keep the input out of current limit, thereby keeping the system voltage above V_SYS-MIN (V_SYS-REG - 100mV, typ). If this loop reduces battery current to 0 and the system is in need of more current than the input can provide, then the Smart Power Selector overrides the minimum system voltage regulation loop and allows SYS to collapse to BATT for the battery to provide supplement current to the system. The Smart Power Selector automatically reenables the minimum system voltage loop when the supplement event has ended.

A maskable interrupt (INT_CHG.SYS_CTRL_I) asserts to signal a change in STAT_CHG_A.VSYS_MIN_STAT. This status bit asserts when the minimum system voltage regulation loop is active.

Die Temperature Regulation

If the die temperature exceeds T_J-REG (programmed by CNFG_CHG_D.TJ_REG[2:0]) the charger attempts to limit the temperature increase by reducing the battery charge current. The STAT_CHG_A.TJ_REG_STAT bit asserts whenever charge current is reduced due to this loop. The charger's current sourcing capability to SYS remains unaffected when STAT_CHG_A.TJ_REG_STAT is high. A maskable interrupt (INT_CHG.TJ_REG_I) asserts to signal a change in STAT_CHG_A.TJ_REG_STAT. Use the INT_CHG.TJ_REG_I interrupt to signal the system processor to reduce loads on SYS to reduce total system temperature.

Charger State Machine

The battery charger follows a strict state-to-state progression to ensure that a battery is charged safely. The status bitfield STAT_CHG_B.CHG_DTLS[3:0] reflects the charger's current operational state. A maskable interrupt (INT_CHG.CHG_I) is available to signal a change in STAT_CHG_B.CHG_DTLS[3:0].

Charger-Off State

The charger is off when CHGIN is invalid, the charger is disabled, or the battery is fresh.

CHGIN is invalid when the CHGIN input is invalid (V_CHGIN < V_{CHGIN_UVLO} or V_CHGIN > V_{CHGIN_OVP}). While CHGIN is invalid, the battery is connected to the system. CHGIN voltage quality can be separately monitored by the STAT_CHG_B.CHGIN_DTLS[1:0] status bitfield. See the Register Map section for details.

The charger is disabled when the charger enable bit is 0 (CNFG_CHG_B.CHG_EN = 0). The battery is connected or disconnected to the system depending on the validity of V_CHGIN while CNFG_CHG_B.CHG_EN = 0. See the Smart Power Selector section.

The battery is fresh when CHGIN is valid and the charger is enabled (CNFG_CHG_B.B.CHG_EN = 1) and the battery is not low by V_RESTART (V_BATT > V_FAST-CHG - V_RESTART). The battery is disconnected from the system and not charged while the battery is fresh. The charger state machine exits this state and begins charging when the battery becomes low by V_RESTART (150mV, typ). This condition is functionally similar to done state. See the Done State section.

Prequalification State

The prequalification state is intended to assess a low-voltage battery's health by charging at a reduced rate. If the battery voltage is less than the V_PQ threshold, the charger is automatically in prequalification. If the cell voltage does not exceed V_PQ in 30 minutes (t_PQ), the charger faults. The prequalification charge rate is a percentage of I_FAST-CHG and is programmable with CNFG_CHG_B.I_PQ. The prequalification voltage threshold (V_PQ) is programmable through CNFG_CHG_C.CHG_PQ[2:0].

Fast-Charge States

When the battery voltage is above V_PQ, the charger transitions to the fast-charge (CC) state. In this state, the charger delivers a constant current (I_FAST-CHG) to the cell. The constant current level is programmable from 7.5mA to 300mA by CNFG_CHG_E.CHG_CC[5:0].

When the cell voltage reaches V_FAST-CHG, the charger state machine transitions to fast-charge (CV). V_FAST-CHG is programmable with CNFG_CHG_G.CHG_CV[5:0] from 3.6V to 4.6V. The charger holds the battery's voltage constant at V_FAST-CHG while in the fast-charge (CV) state. As the battery approaches full, the current accepted by the battery reduces. When the charger detects that battery charge current has fallen below I_TERM, the charger state machine enters the top-off state.

A fast-charge safety timer starts when the state machine enters fast-charge (CC) or JEITA-modified fast-charge (CC) from a non-fast-charge state. The timer continues to run through all fast-charge states regardless of JEITA status. The timer length (t_FC) is programmable from 3 hours to 7 hours in 2 hour increments with CNFG_CHG_E.T_FAST_CHG[1:0]. If it is desired to charge without a safety timer, program CNFG_CHG_E.T_FAST_CHG[1:0] with 0b00 to disable the feature. If the timer expires before the fast-charge states are exited, the charger faults. See the Fast-Charge Timer Fault State section for more information.

If the charge current falls below 20% of the programmed value during fast-charge (CC), the safety timer pauses. The timer also pauses for the duration of supplement mode events. The STAT_CHG_B.TIME_SUS bit indicates the status of the fast-charge safety timer. See the Register Map section for more details.

Top-Off State

Top-off state is entered when the battery charge current falls below I_TERM during the fast-charge (CV) state. I_TERM is a percentage of I_FAST-CHG and is programmable through CNFG_CHG_C.I_TERM[1:0]. While in the top-off state, the battery charger continues to hold the battery's voltage at V_FAST-CHG. A programmable top-off timer starts when the charger state machine enters the top-off state. When the timer expires, the charger enters the done state. The top-off timer value (t_TO) is programmable from 0 minutes to 35 minutes with CNFG_CHG_C.T_TOPOFF[2:0]. If it is desired to stop charging as soon as battery current falls below I_TERM, program t_TO to 0 minutes.

Done State

The charger enters the done state when the top-off timer expires. The battery remains disconnected from the system during done. The charger restarts if the battery voltage falls more than V_RESTART (150mV, typ) below the programmed V_FAST-CHG value.

Prequalification Timer Fault State

The prequalification timer fault state is entered when the battery's voltage fails to rise above V_PQ in t_TO (30 minutes, typ) from when the prequalification state was first entered. If a battery is too deeply discharged, damaged, or internally shorted, the prequalification timer fault state can occur. During the timer fault state, the charger stops delivering current to the battery and the battery remains disconnected from the system. To exit the prequalification timer fault state, toggle the charger enable (CNFG_CHG_B.CHG_EN) bit or unplug and replug the external voltage source connected to CHGIN.

Fast-Charge Timer Fault State

The charger enters the fast-charge timer fault state if the fast-charge safety timer expires. While in this state, the charger stops delivering current to the battery and the battery remains disconnected from the system. To exit the fast-charge timer fault state, toggle the charger enable bit (CNFG_CHG_B.CHG_EN) or unplug and replug the external voltage source connected to CHGIN.

Battery Temperature Fault State

If the thermistor monitoring circuit reports that the battery is either too hot or too cold to charge (as programmed by CNFG_CHG_A.THM_HOT[1:0] and CNFG_CHG_A.THM_COLD[1:0]), the state machine enters the battery temperature fault state. While in this state, the charger stops delivering current to the battery and the battery remains disconnected from the system. This state can only be entered if the thermistor is enabled (CNFG_CHG_F.THM_EN = 1). Battery temperature fault state has priority over any other fault state, and can be exited when the thermistor is disabled (CNFG_CHG_F.THM_EN = 0) or when the battery returns to an acceptable temperature. When this fault state is exited, the state machine returns to the last state it was in before battery temperature fault state was entered.

All active charger timers (fast-charge safety timer, prequalification timer, or top-off timer) are paused in this state. When the charger exits this state, the prequalification timer resumes while the fast-charge safety and top-off timers reset.

The STAT_CHG_A.THM_DTLS[2:0] bitfield reports battery temperature status. See the Adjustable Thermistor Temperature Monitors and the Register Map sections for more information.

JEITA-Modified States

If the thermistor is enabled (CNFG_CHG_F.THM_EN = 1), then the charger state machine is allowed to enter the JEITA-modified states. These states are entered if the charger's temperature monitors indicate that the battery temperature is either warm (greater than T_WARM) or cool (lesser than T_COOL). See the Adjustable Thermistor Temperature Monitors section for more information about setting the temperature thresholds.

The charger's current and voltage parameters change from I_FAST-CHG and V_FAST-CHG to I_{FAST-CHG_JEITA} and V_{FAST-CHG_JEITA} while in the JEITA-modified states. The JEITA modified parameters can be independently set to lower voltage and current values so that the battery can charge safely over a wide range of ambient temperatures. If the battery temperature returns to normal, or the thermistor is disabled (CNFG_CHG_.THM_EN = 0), the charger exits the JEITA-modified states.

Typical Charge Profile

A typical battery charge profile (and state progression) is illustrated in Figure 16.

Figure 16. Example Battery Charge Profile

Charger Applications Information

Configuring a Valid System Voltage

The Smart Power Selector begins to regulate SYS to V_SYS-REG when CHGIN is connected to a valid source. To ensure the charger's accuracy specified in the Electrical Characteristics table, the system voltage must always be programmed at least 200mV above the charger's constant-voltage level (V_FAST-CHG). If this condition is not met, then the charger's internal configuration logic forces V_FAST-CHG to reduce to satisfy the 200mV requirement. If this happens, the charger asserts the INT_CHG.SYS_CNFG_I interrupt to alert the user that a configuration error has been made and that the bits in CNFG_CHG_G.CHG_CV[5:0] have changed to reduce V_FAST-CHG.

CHGIN/SYS/BATT Capacitor Selection

Bypass CHGIN to GND with a 4.7μF ceramic capacitor to minimize inductive kick caused by long cables between the DC charge source and the product/IC. Larger values increase decoupling for the linear charger, but increase inrush current from the DC charge source when the product/IC is first connected to a source through a cable/plug. If the DC charging source is an upstream USB device, limit the maximum CHGIN input capacitance based on the appropriate USB specification (typically no more than 10μF).

Bypass SYS to GND with a 22μF ceramic capacitor. This capacitor ensures stability of SYS while it is regulated from CHGIN. Larger values of SYS capacitance increase decoupling for all SYS loads. The effective value of the SYS capacitor must be greater than 4μF and no more than 100μF.

Bypass BATT to GND with a 4.7μF ceramic capacitor. This capacitor stabilizes the BATT voltage regulation loop. The effective value of the BATT capacitor must be greater than 1μF.

Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients. All ceramic capacitors derate with DC bias voltage (effective capacitance goes down as DC bias goes up). Generally, small case size capacitors derate heavily compared to larger case sizes (0603 case size performs better than 0402). Consider the effective capacitance value carefully by consulting the manufacturer's data sheet.

Detailed Description—Adjustable Thermistor Temperature Monitors

The optional use of a negative temperature coefficient (NTC) thermistor (thermally coupled to the battery) enables the charger to operate safely over the JEITA temperature range. When the thermistor is enabled (CNFG_CHG_F.THM_EN = 1), the charger continuously monitors the voltage at the THM pin in order to sense the temperature of the battery being charged.

See Figure 17 for a visual example of the following:

If the battery temperature is higher than T_COOL and lower than T_WARM, the battery charges normally with the normal values for V_FAST-CHG and I_FAST-CHG. The charger state machine does not enter JEITA-modified states while the battery temperature is normal.
If the battery temperature is either above T_WARM but below T_HOT, or, below T_COOL but above T_COLD, the battery charges with the JEITA-modified voltage and current values. These modified values, V_{FAST-CHG_JEITA} and I_{FAST-CHG_JEITA}, are programmable through CNFG_CHG_H.CHG_CV_JEITA[5:0] and CNFG_CHG_F.CHG_CC_JEITA[5:0], respectively. These values are independently programmable from the unmodified V_FAST-CHG and I_FAST-CHG values and can even be programmed to the same values if an automatic response to a warm or cool battery is not desired. The charger state machine enters JEITA-modified states while the battery temperature is outside of normal.
If the battery temperature is either above T_HOT or below T_COLD, the charger follows the JEITA recommendation and pauses charging. The charger state machine enters battery temperature fault state while charging is paused due to extreme high or low temperatures.

The battery's temperature status is reflected by the STAT_CHG_A.THM_DTLS[2:0] status bitfield. A maskable interrupt (INT_CHG.THM_I) signals a change in status. See the Register Map for more information. To completely disable the charger's automatic response to battery temperature, disable the feature by programming CNFG_CHG_F.THM_EN = 0.

Figure 17. Safe-Charging Profile Example

The voltage thresholds corresponding to the JEITA temperature thresholds are independently programmable through CNFG_CHG_A.THM_HOT[1:0], CNFG_CHG_A.THM_WARM[1:0], CNFG_CHG_A.THM_COOL[1:0], and CNFG_CHG_A.THM_COLD[1:0]. Each threshold can be programmed to one of four voltage options spanning 15°C for an NTC beta of 3380K. See the Configurable Temperature Thresholds section and the Register for more information.

Thermistor Bias

An external ADC can optionally perform conversions on the THM and TBIAS pins to measure the battery's temperature. An on-chip analog multiplexer is used to route these nodes to the AMUX pin. The operation of the analog multiplexer does not interfere with the charger's temperature monitoring comparators or the charger's automatic JEITA response. See the Analog Multiplexer section for more information.

The NTC thermistor's bias source (TBIAS) follows the simple operation outlined below:

If CHGIN is valid and the thermistor is enabled (CNFG_CHG_F.THM_EN = 1), the thermistor is biased, so the charger can automatically respond to battery temperature changes.
If the analog multiplexer connects THM or TBIAS to AMUX, then the thermistor is biased, so an external ADC can perform a meaningful temperature conversion.

Figure 18. Thermistor Bias State Diagram

The AMUX pin is a buffered output. The operation of the analog multiplexer and external ADC does not collide with the function of the on-chip temperature monitors. Both functions may be used simultaneously with no ill effect.

Configurable Temperature Thresholds

Temperature thresholds for different NTC thermistor beta values are listed in Table 10. The largest possible programmable temperature range can be realized by using an NTC with a beta of 3380K. Using a larger beta compresses the temperature range. The trip voltage thresholds are programmable with the CNFG_CHG_A.THM_HOT[1:0], CNFG_CHG_A.THM_WARM[1:0], CNFG_CHG_A.THM_COOL[1:0], and CNFG_CHG_A.THM_COLD[1:0] bitfields. All possible programmable trip voltages are listed in Table 10.

Table 10. Trip Temperatures vs. Trip Voltages for Different NTC β
TRIP VOLTAGE (V)	TRIP TEMPERATURES (°C)
TRIP VOLTAGE (V)	3380K	3435K	3940K	4050K	4100K	4250K
1.024	-10.0	-9.5	-5.6	-4.8	-4.5	-3.5
0.976	-5.0	-4.6	-1.1	-0.5	-0.2	0.6
0.923	0.0	0.3	3.3	3.8	4.1	4.8
0.867	5.0	5.3	7.7	8.1	8.3	8.9
0.807	10.0	10.2	12.0	12.4	12.5	12.9
0.747	15.0	15.1	16.4	16.6	16.7	17.0
0.511	35.0	34.8	33.5	33.3	33.2	32.9
0.459	40.0	39.8	37.8	37.4	37.3	36.8
0.411	45.0	44.7	42.0	41.5	41.3	40.7
0.367	50.0	49.6	46.2	45.6	45.3	44.6
0.327	55.0	54.5	50.4	49.7	49.3	48.4
0.291	60.0	59.4	54.6	53.7	53.3	52.2

These are theoretical values computed by a formula. Refer to the particular NTC's data sheet for more accurate measured data. In all cases, select the value of R_BIAS to be equal to the NTC's effective resistance at +25°C.

Applications Information

Using Different Thermistor β

If an NTC with a beta larger than 3380K is used and the resulting available programmable temperature range is undesirably small, then two adjusting resistors can be used to expand the temperature range. R_S and R_P can be optionally added to the NTC thermistor circuit shown in Figure 19 to expand the range of programmable temperature thresholds.

Figure 19. Thermistor Circuit with Adjusting Series and Parallel Resistors

Select values for R_S and R_Pbased on the information shown in Table 11.

Table 11. Example R_S and R_P Correcting Values for NTC β Above 3380K
PARAMETER	UNIT	TARGET NTC CASE	CASE 1		CASE 2		CASE 3
NTC thermistor beta	K	3380	3940		4050		4250
25°C NTC resistance	kΩ	10	10		47		100
R_BIAS		10	10		47		100
Adjusting parallel resistor, R_P		open	open	200	open	680	open	1300
Adjusting series resistor, R_S		short	short	0.62	short	3.3	short	9.1
R_NTC at 1.024V_COLD threshold		45.24	45.24	578.5	212.6	306.1	452.4	684.8
R_NTC at 0.867V_COOL threshold		22.61	22.61	248.8	106.3	122.7	226.1	264.7
R_NTC at 0.459V_WARM threshold		5.81	5.81	5.36	27.3	25.1	58.1	51.7
R_NTC at 0.291V_HOT threshold		3.04	3.04	2.46	14.3	112.7	30.4	22.0
T_ACTUAL at V_COLD (-10°C expected)	°C	-10.03	-5.56	-9.96	-4.82	-11.14	-3.55	-10.46
T_ACTUAL at V_COOL (5°C expected)		4.98	7.66	5.76	8.10	5.33	8.86	5.94
T_ACTUAL at V_WARM (40°C expected)		40.02	37.79	39.76	37.43	39.40	36.82	39.48
T_ACTUAL at V_HOT (60°C expected)		60.04	54.56	60.37	53.68	60.02	52.21	60.4

NTC Thermistor Selection

Popular NTC thermistor options are listed in Table 12.

Table 12. NTC Thermistors
MANUFACTURER	PART	β-CONSTANT (25°C/50°C)	R (Ω) AT 25°C	CASE SIZE
TDK	NTCG063JF223HTBX	3380K	22k	0201
Murata	NCP03XH103F05RL	3380K	10k	0201
Murata	NCP15XH103F03RC	3380K	10k	0402
TDK	NTCG103JX103DT1	3380K	10k	0402
Cantherm	CMFX3435103JNT	3435K	10k	0402
Murata	NCP15XV103J03RC	3900K	10k	0402
Panasonic	ERT-JZEP473J	4050K	47k	0201
Panasonic	ABNTC-0402-473J-4100F-T	4100K	47k	0402
Murata	NCP15WF104F03RC	4250K	100k	0402

Detailed Description—Analog Multiplexer

An external ADC can be used to measure the chip's various signals for general functionality or on-the-fly power monitoring. The CNFG_CHG_I.MUX_SEL[3:0] bitfield controls the internal analog multiplexer responsible for connecting the proper channel to the AMUX pin. Each measurable signal is listed in Table 13 with its appropriate multiplexer channel.

The voltage on the AMUX pin is a buffered output that ranges from 0V to V_FS (1.25V, typ). The buffer has 50μA of quiescent current consumption and is only active when a channel is selected (CNFG_CHG_I.MUX_SEL[3:0] ≠ 0b0000). Disable the buffer by programming CNFG_CHG_I.MUX_SEL[3:0] to 0b0000 when not actively converting the voltage on AMUX. The AMUX output is high-impedance while CNFG_CHG_I.MUX_SEL[3:0] is 0b0000.

Table 13 shows how to translate the voltage signal on the AMUX pin to the value of the parameter being measured. See the Electrical Characteristics table and the Register Map for more details.

Table 13. AMUX Signal Transfer Functions
SIGNAL	MUX_SEL[3:0]	TRANSFER FUNCTION	FULL-SCALE SIGNAL MEANING (V_AMUX = 1.25V)	ZERO-SCALE SIGNAL MEANING (V_AMUX = 0V)
CHGIN pin voltage	0b0001	_{$V_{CHGIN} = \frac{V_{AMUX}}{G_{VCHGIN}}$}	7.5V	0V
CHGIN pin current	0b0010	_{$I_{CHGIN} = \frac{V_{AMUX}}{G_{ICHGIN}}$}	0.475A	0A
BATT pin voltage	0b0011	_{$V_{BATT} = \frac{V_{AMUX}}{G_{VBATT}}$}	4.6V	0V
BATT pin charging current	0b0100	$I_{BATT (CHG)} = \frac{V_{AMUX}}{V_{FS}} \times I_{FAST - CHG}$	100% of I_FAST-CHG (CHG_CC[5:0])	0% of I_FAST-CHG
BATT pin discharge current	0b0101	$I_{BATT (DISCHG)} = \frac{(V_{AMUX} - V_{NULL})}{(V_{FS} - V_{NULL})} \times I_{DISCHG - SCALE}$	100% of I_DISCHG-SCALE _{(IMON_DISCHG_SCALE[3:0])}	0% of I_DISCHG-SCALE
BATT pin discharge current NULL	0b0110	_{$V_{NULL} = V_{AMUX}$}	1.25V	0V
THM pin voltage	0b0111	_{$V_{THM} = V_{A M U X}$}	1.25V	0V
TBIAS pin voltage	0b1000	_{$V_{TBIAS} = V_{A M U X}$}	1.25V	0V
AGND pin voltage*	0b1001	_{$V_{AGND} = V_{A M U X}$}	1.25V	0V
SYS pin voltage	0b1010	_{$V_{SYS} = \frac{V_{A M U X}}{G_{VSYS}}$}	4.8V	0V

*AGND pin voltage is accessed through a 100Ω (typ) pulldown resistor.

Measuring Battery Current

Sampling current in the BATT pin is possible at any time or in any mode with an external ADC. For improved accuracy, the analog circuitry used for monitoring battery discharge current is different from the circuitry monitoring battery charge current. Table 14 outlines how to determine the direction of battery current.

Table 14. Battery Current Direction Decode
MEASUREMENT	CHARGING OR DISCHARGING INDICATORS
MEASUREMENT	STAT_CHG_B.CHG	STAT_CHG_B.CHG_DTLS[3:0]	STAT_CHG_B.CHGIN_DTLS[1:0]
Discharging Battery Current (Positive Battery Terminal Sourcing Current)	Don't care	Don't care	0b00 0b01 0b10
Charging Battery Current (Positive Battery Terminal Sinking Current)	1	0b0001 to 0b0111	0b11

Method for Measuring Discharge Current

Program the multiplexer to switch to the discharge NULL measurement by changing CNFG_CHG_I.MUX_SEL[3:0] to 0b0110. A NULL conversion must always be performed first to cancel offsets.
Wait the appropriate channel switching time (0.3μs, typ).
Convert the voltage on the AMUX pin and store as V_NULL.
Program the multiplexer to switch to the battery discharge current measurement by changing CNFG_CHG_I.MUX_SEL[3:0] to 0b0101. A nonnulling conversion should be done immediately after a NULL conversion.
Wait the appropriate channel switching time (0.3μs, typ).
Convert the voltage on the AMUX pin and use the following transfer function to determine the discharge current:

$I_{BATT (DISCHG)} = \frac{(V_{AMUX} - V_{NULL})}{(V_{FS} - V_{NULL})} \times I_{DISCHG - SCALE}$

V_FS is 1.25V typical. I_DISCHG-SCALE is programmable through CNFG_CHG_I.IMON_DISCHG_SCALE[3:0]. The default value is 300mA. If smaller currents are anticipated, then I_DISCHG-SCALE can be reduced for improved measurement accuracy.

Method for Measuring Charge Current

Program the multiplexer to switch to the charge current measurement by changing CNFG_CHG_I.MUX_SEL[3:0] to 0b0100.
Wait the appropriate channel switching time (0.3μs, typ).
Convert the voltage on the AMUX pin and use the following transfer function to determine charging current.

I_{BATT (CHG)} = \frac{V_{AMUX}}{V_{FS}} \times I_{FAST - CHG}

V_FS is 1.25V typical. I_FAST-CHG the charger's fast-charge constant-current setting and is programmable through CNFG_CHG_E.CHG_CC[5:0].

Detailed Description—SIMO Buck-Boost

The device has a micropower single-inductor, multiple-output (SIMO) buck-boost DC-to-DC converter designed for applications that emphasize low supply current and small solution size. A single inductor is used to regulate three separate outputs, saving board space while delivering better total system efficiency than equivalent power solutions using one buck and linear regulators.

The buck-boost configuration utilizes the entire battery voltage range due to its ability to create output voltages that are above, below, or equal to the input voltage. Peak inductor current for each output is programmable to optimize the balance between efficiency, output ripple, EMI, PCB design, and load capability.

To further boost efficiency when the output voltage is always lower than the input, individual channels of the SIMO buck-boost converter can be configured to be in buck mode, reducing switching losses by toggling less switches compared to buck-boost mode. See the Buck Mode section for more details.

SIMO Features and Benefits

Three Output Channels
Ideal for Low-Power Designs
- Delivers 500mA at 1.8V Output in Buck Mode and 3.7V Input
- ±3% Accurate Output Voltage
Small Solution Size
- Multiple Outputs from a Single 1.5μH Inductor
Flexible and Easy to Use
- Buck and Buck-Boost Modes of Operation
- Glitchless Transitions Between Buck and Buck-Boost Modes
- Programmable Peak Inductor Current
- Programmable On-Chip Active Discharge
Long Battery Life
- High Efficiency, > 90% at 1.8V Output in Buck Mode and 3.7V Input
- Higher Total System Efficiency than Buck + LDOs Solution
- Low Quiescent Current, 1μA per Output
- Low Input Operating Voltage, 2.7V (min)

SIMO Detailed Block Diagram

SIMO Control Scheme

The SIMO buck-boost is designed to service multiple outputs simultaneously. A proprietary controller ensures that all outputs get serviced in a timely manner, even while multiple outputs are contending for the energy stored in the inductor. When no regulator needs service, the state machine rests in a low-power rest state.

When the controller determines that a regulator requires service, it charges the inductor (M1 + M4) until the peak current limit is reached (I_LIM= CNFG_SBBx_B.IP_SBB[1:0]). The inductor energy then discharges (M2 + M3_x) into the output until the current reaches zero (I_ZX). In the event that multiple output channels need servicing at the same time, the controller ensures that no output utilizes all of the switching cycles. Instead, cycles interleave between all the outputs that are demanding service, while outputs that do not need service are skipped.

Drive Strength

The SIMO regulator's drive strength for its internal power MOSFETs is adjustable using the CNFG_SBB_TOP.DRV_SBB[1:0] bit field. The ideal value is determined experimentally for each application. For a PCB layout comparable to the MAX77654 EV kit, 0x1 is the best setting and represents a balance between efficiency and EMI. Faster settings result in higher efficiency but generally require stricter layout rules or shielding to avoid additional EMI. Slower settings limit EMI in non-ideal settings (e.g., contained layout, antennae adjacent to the device, etc.). Change the drive strength only once during system initialization.

SIMO Soft-Start

The soft-start feature of the SIMO limits inrush current during startup. The soft-start feature is achieved by limiting the slew rate of the output voltage during startup (dV/dt_SS).

More output capacitance results in higher input current surges during startup. The following set of equations and example describes the input current surge phenomenon during startup.

In buck-boost mode, the current into the output capacitor (I_CSBB) during soft-start is:

$I_{CSBB} = C_{SBB} \frac{dV}{{dt}_{SS}} (Equation 1)$

where:

C_SBB is the capacitance on the output of the regulator
dV/dt_SS is the voltage change rate of the output

The input current (I_IN) during soft-start is:

$I_{IN} = \frac{(I_{CSBB} + I_{LOAD}) \frac{V_{SBBx}}{V_{IN}}}{ξ} (Equation 2)$

where:

I_CSBB is from the calculation above
I_LOAD is current consumed from the external load
V_SBBx is the output voltage
V_IN is the input voltage
ξ is the efficiency of the regulator

For example, given the following conditions, the peak input current (I_IN) during soft-start is ~66.55mA:

Given:

V_IN is 3.5V
V_SBB2 is 3.3V
C_SBB2= 10µF
dV/dt_SS= 5mV/µs
R_LOAD2= 330Ω (I_LOAD2= 3.3V/330Ω = 10mA)
ξ is 85%

Calculation:

I_CSBB = 10µF x 5mV/µs (from Equation 1)
I_CSBB = 50mA
$I_{IN} = \frac{(50 mA + 10 mA) \frac{3.3 V}{3.5 V}}{0.85}$ (from Equation1)
I_IN ~ 66.55mA

SIMO Registers

Each SIMO buck-boost channel has a dedicated register to program its target output voltage (CNFG_SBBx_A.TV_SBBx[6:0]) and its peak current limit (CNFG_SBBx_B.IP_SBBx[1:0]). Additional controls are available for enabling/disabling the active-discharge resistors (CNFG_SBBx_B.ADE_SBBx), buck mode (CNFG_SBBx_B.OP_MODE) as well as enabling/disabling the SIMO buck-boost channels (CNFG_SBBx_B.EN_SBBx[2:0]). For a full description of bits, registers, default values, and reset conditions, see the Register Map.

SIMO Active Discharge Resistance

Each SIMO buck-boost channel has an active-discharge resistor (R_{AD_SBBx}) that is automatically enabled/disabled based on a CNFG_SBBx_B.ADE_SBBx bit and the status of the SIMO regulator. The active discharge feature may be enabled (CNFG_SBBx_B.ADE_SBBx = 1) or disabled (CNFG_SBBx_B.ADE_SBBx = 0) independently for each SIMO channel. Enabling the active discharge feature helps ensure a complete and timely power down of all system peripherals. If the active-discharge resistor is enabled by default, then the active-discharge resistor is on whenever V_SYS is below V_SYSUVLO and above V_POR.

These resistors discharge the output when CNFG_SBBx_B.ADE_SBBx = 1, and their respective SIMO channel is off. If the regulator is forced on through CNFG_SBBx_B.EN_SBBx[2:0] = 0b110 or 0b111, then the resistors do not discharge the output even if the regulator is disabled by the main-bias.

Note that when V_SYS is less than 1.0V, the NMOS transistors that control the active-discharge resistors lose their gate drive and become open.

SIMO Buck Mode

If the input voltage at IN_SBB never falls below the output voltage of one or more SIMO converter channels, individual channels can be configured to be in buck mode with the CNFG_SBBx_B.OP_MODE bit. In buck mode, when an output needs service, switch M3_x remains closed and M4 remains open (see Figure 20). Only M1 and M2 are toggled as in a traditional buck converter. Efficiency is boosted due to three major factors:

Reduced switching loss: Buck mode toggles only two switches versus the four in buck-boost mode. Therefore, there are less switching events during which power is consumed.
Lower inductor core losses: Inductor current changes from 0A to peak current. The larger the change in current the inductor experiences, the more energy is lost in the inductor core in the form of heat. In buck mode, the peak current can be reduced since less inductor current is needed to support a load. Less inductor current is needed because of direct energy transfer. Direct energy transfer occurs while the inductor is charged, when the input (IN_SBB) is connected directly to the output (SBBx) through the inductor. Therefore, the input not only provides energy to charge the inductor, energy is also supplied to the output capacitor and load devices. Therefore, less current is needed to charge the inductor, which is used to charge the output capacitor in the next switching state.
Less frequent charging cycles: In buck mode, the inductor is constantly connected to the serviced output during a switching cycle. In comparison, in buck-boost mode, the inductor is connected to the serviced output only when the inductor discharges. Thus, with the same peak inductor current limit, buck mode is capable of supplying higher load current than buck-boost mode. In addition, with the same load current and peak current limit, the switching frequency can be reduced with buck mode.

Maintain a minimum headroom of 0.7V between IN_SBB and SBBx in buck mode because inductor charge time (dt = L x I_{P_SBBx}/(V_{IN_SBB} - V_SBBx)) increases as the difference between the IN_SBB and SBBx voltages shrinks. As the inductor current takes longer to reach its peak, the output voltage may take too long to reach its target voltage, and the MAX77654 may trigger a fault flag.

Applications Information

SIMO Available Output Current

The available output current on a given SIMO channel is a function of the input voltage, output voltage, the peak current limit setting, and the output current of the other SIMO channels. Maxim offers a calculator (see the Support Material section) that outlines the available capacity for specific conditions. Table 15 is an extraction from the calculator.

Table 15. SIMO Available Output Current for Common Applications
PARAMETERS	EXAMPLE 1	EXAMPLE 2	EXAMPLE 3	EXAMPLE 4
V_{IN_MIN}	2.7V	2.7V	3.2V	3.4V
R_{L_DCR}	0.1Ω	0.1Ω	0.1Ω	0.12Ω
SBB0	1.0V at 100mA	1.0V at 80mA	1.2V at 50mA	1.2V at 20mA
SBB1	1.2V at 75mA	1.2V at 50mA	1.8V at 100mA	1.8V at 80mA
SBB2	1.8V at 50mA	1.8V at 40mA	3.3V at 30mA	3.3V at 10mA
Operating Mode	Buck	Buck	Buck/Buck-Boost	Buck/Buck-Boost
I_{P_SBB0}	0.5A	0.5A	0.5A	0.5A
I_{P_SBB1}	0.75A	0.5A	0.5A	0.5A
I_{P_SBB2}	0.5A	0.5A	0.75A	0.5A
Utilized Capacity	78%	67%	76%	47%

*ESR_{C_IN} = ESR_{C_OUT} = 5mΩ, L = 1.5μH

Inductor Selection

Choose an inductance from 1.0μH to 2.2μH; 1.5μH inductors work best for most designs. Larger inductances transfer more energy to the output for each cycle and typically result in larger output voltage ripple and better efficiency. See the Output Capacitor Selection section for more information on how to size your output capacitor in order to control ripple.

Choose the inductor saturation current to be greater than or equal to the maximum peak current limit setting that is used for all of the SIMO buck-boost channels (I_{P_SBBx}). For example, if SBB0 is set for 0.5A, SBB1 is set for 0.75A, and SBB2 is set for 1.0A, then choose the saturation current to be greater than or equal to 1.0A.

Choose the RMS current rating of the inductor (typically the current at which the temperature rises appreciably) based on the expected load currents for the system. For systems where the expected load currents are not well known, be conservative and choose the RMS current to be greater than or equal to half the higher maximum peak current limit setting [I_RMS≥ MAX(I_{P_SBB0}, I_{P_SBB1}, I_{P_SBB2})/ $\sqrt{3}$ ]. This is a conservative choice because the SIMO buck-boost regulator implements a discontinuous conduction mode (DCM) control scheme, which returns the inductor current to zero each cycle.

Consider the DC-resistance (DCR), AC-resistance (ACR), and solution size of the inductor. Typically, smaller sized inductors have larger DC-resistance and larger AC-resistance that reduces efficiency and the available output current. Note that many inductor manufacturers have inductor families which contain different versions of core material in order to balance trade-offs between DCR, ACR (i.e., core losses), and component cost. For this SIMO regulator, inductors with the lowest ACR in the 1.0MHz to 2.0MHz region tend to provide the best efficiency.

Input Capacitor Selection

Choose the input bypass capacitance (C_{IN_SBB}) to be 10µF. Larger values of C_{IN_SBB} improve the decoupling for the SIMO regulator.

C_{IN_SBB} reduces the current peaks drawn from the battery or input power source during SIMO regulator operation and reduces switching noise in the system. The ESR/ESL of the input capacitor should be very low (i.e., ESR ≤ 5mΩ and ESL ≤ 500pH) for frequencies up to 2MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients.

To fully utilize the available input voltage range of the SIMO (5.5V, max), use a capacitor with a voltage rating of 6.3V at minimum.

Boost Capacitor Selection

Choose the boost capacitance (C_BST) to be 3.3nF. Smaller values of C_BST (< 1nF) result in insufficient gate drive for M3. Larger values of C_BST (> 10nF) have the potential to degrade the startup performance. Ceramic capacitors with 0201 or 0402 case size are recommended.

Output Capacitor Selection

Choose each output bypass capacitance (C_SBBx) based on the target output voltage ripple (∆V_SBBx): typical values are 22μF. Larger values of C_SBBx improve the output voltage ripple but increase the input surge currents during soft-start and output voltage changes. The output voltage ripple is a function of the inductance (L), the output voltage (V_SBBx), and the peak current limit setting (I_{P_SBBx}). See Equation 3 to estimate required, effective capacitance.

$C_{SBBx} = \frac{{I_{P_SBBx}}^{2} * L}{2 * V_{SBBx} * ∆ V_{SBBx} (Equation 3)}$

Maxim also offers a calculator (see the Support Materials section) to aid in the selection of the output capacitance. Note that most designs concern themselves with having enough capacitance on the output but there is also a maximum capacitance limitation that is calculated within the SIMO calculator; take care not to exceed the maximum capacitance.

C_SBBx is required to keep the output voltage ripple small. The impedance of the output capacitor (ESR, ESL) should be very low (i.e., ESR ≤ 5mΩ and ESL ≤ 500pH) for frequencies up to 2MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients.

A capacitor's effective capacitance decreases with increased DC bias voltage. This effect is more pronounced as capacitor case sizes decrease. Due to this characteristic, it is possible for an 0603 case size capacitor to perform well, while an 0402 case size capacitor of the same value performs poorly. The SIMO regulator is stable with low output capacitance (1μF) but the output voltage ripple would be large; consider the effective output capacitance value after initial tolerance, bias voltage, aging, and temperature derating.

Example Component Selection

Pick input/output capacitors and the inductor for the given requirements:

V_{IN_SBB, typical} = 3.7V

Table 16. Design Requirements
	SBB0	SBB1	SBB2
Output Voltage	3.3V	1.8V	1.2V
Maximum Load Current	50mA	60mA	80mA
Maximum Voltage Ripple	50mV	30mV	30mV

Inductor, Peak Current Limit, and Input Capacitor

For the best efficiency, a 2.2μH inductor is chosen. For this example, assume the DFE201612E-2R2M inductor from Murata is used. This particular inductor has 116mΩ of DCR.

Since the load current is low, first choose the inductor current peak to be 0.333A for all outputs. Next, enter these values into Maxim's SIMO calculator as mentioned previously.

Figure 21. Component Selection—High Utilization

As shown in Figure 21, the utilization is over 100%, which leads to output voltage droop. To lower utilization, increase the inductor peak current limits. For this example, 1A is used for SBB0 and 0.5A for SBB1 and SBB2. Figure 22 shows utilization less than 80%. Using 0.5A for the inductor peak current limit has the added benefit of increased efficiency.

Figure 22. Component Selection—Final Current Peak Limits

To support the selected peak currents, choose 22μF for the input capacitor.

Output Capacitors

Using Equation 3 and the selected inductor current peak limits, the minimum output capacitances required are:

$C_{SBB 0_min} = \frac{{I_{P_SBB 0}}^{2} x L}{2 x V_{SBB 0} x ∆ V_{SBB 0}} = \frac{1^{2} x 2.2 x 10^{- 6}}{2 x 3.3 x 0.05} \frac{A^{2} x H}{V^{2}} = 6.67 μF$

$C_{SBB 1_min} = \frac{{I_{P_SBB 1}}^{2} x L}{2 x V_{SBB 1} x ∆ V_{SBB 1}} = \frac{0 . 5^{2} x 2.2 x 10^{- 6}}{2 x 1.8 x 0.03} \frac{A^{2} x H}{V^{2}} = 5.09 μF$

$C_{SBB 2_min} = \frac{{I_{P_SBB 2}}^{2} x L}{2 x V_{SBB 2} x ∆ V_{SBB 2}} = \frac{0 . 5^{2} x 2.2 x 10^{- 6}}{2 x 1.2 x 0.03} \frac{A^{2} x H}{V^{2}} = 7.64 μF$

For this example, the 22μF GRM188R61A226ME15 is chosen for all three outputs. The effective capacitance after derating is the following:

$C_{SBB 0} = 8.113 μF$

$C_{SBB 1} = 13.828 μF$

$C_{SBB 2} = 16.793 μF$

Go back to the calculator and enter the capacitance for each channel. Figure 23 shows the expected ripples, which fit the requirements.

Figure 23. Component Selection—Expected Ripple

Summary

L = 2.2μH
C_{IN_SBB} = 22μF
Total Switching Utilization = 76%

Table 17. Summary of Design for Component Selection Example
	SBB0	SBB1	SBB2
I_{P_SBBx}	1A	0.5A	0.5A
C_SBBx (nominal)	22μF	22μF	22μF
∆V_SBBx	35.3mV	19.4mV	15.7mV

Real applications should also consider the minimum input voltage since the battery discharges. The following is a summary using the same components but an input voltage of 3.0V instead. The switching utilization increased to 77.1%, still below 80%.

L = 2.2μH
C_{IN_SBB} = 22μF
Total Switching Utilization = 77.1%

Table 18. Summary of Design with Lower Input Voltage
	SBB0	SBB1	SBB2
I_{P_SBBx}	1A	0.5A	0.5A
C_SBBx (nominal)	22μF	22μF	22μF
∆V_SBBx	35.3mV	26.9mV	18.6mV

SIMO Switching Frequency

The SIMO buck-boost regulator uses a pulse frequency modulation (PFM) control scheme. The switching frequency for each output is a function of the operating mode, input voltage, output voltage, load current, and inductance. Output capacitance is a minor factor in SIMO switching frequency. Maxim offers a SIMO calculator (see the Support Material section) to estimate expected switching frequency.

At no load, switching frequencies can be as low as 10Hz. For the 3.7V input to 1.2V output channel from the Example Component Selection section, the switching frequency is about 327kHz.

Table 19 lists how different factors increase or decrease switching frequency.

Table 19. Switching Frequency Control
FACTOR	INCREASING FREQUENCY	DECREASING FREQUENCY
Inductor Current Peak Limit	Lower peak limit	Higher peak limit
Operating Mode	Buck-boost mode	Buck mode
Inductor	Decrease inductance	Increase inductance
Output Capacitor	Decrease capacitance	Increase capacitance
Input Voltage	Higher voltage	Lower voltage
Output Voltage	Higher voltage	Lower voltage
Load Current	Higher current	Lower current

Unused Outputs

Do not leave unused outputs unconnected. If an output left unconnected is accidentally enabled, the charged inductor experiences an open circuit, and the output voltage soars above the absolute maximum rating, damaging the device. If an output is not used, do one of the following:

Disable the output (CNFG_SBBx_B.EN_SBBx[2:0] = 0x4 or 0x5) and connect the output to ground. If an unused output is default enabled or can be accidentally enabled, do one of the following recommendations instead.
Bypass the unused output with a 1μF capacitor to ground.
Connect the unused output to IN_SBB or a different output channel if the unused output is programmed to a lower voltage. Since the output voltage is higher than the unused output, the regulator does not service the unused output even if it is unintentionally enabled.
1. Note that some OTP options have the active-discharge resistors enabled by default. Connecting an unused output to IN_SBB is not recommended if the active discharge is enabled by default. If connecting the unused output to a different channel, disable the active-discharge resistor (CNFG_SBBx_B.ADE_SBBx = 0) of the unused channel.

PCB Layout Guide

Capacitors

Place decoupling capacitors as close as possible to the IC such that connections from capacitor pads to pin and from capacitor pads to ground pins are short. Keeping the connections short lowers parasitic inductance and resistance, improving performance and shrinking the physical size of hot loops.

If connections to the capacitors are through vias, use multiple vias to minimize parasitics. Also, connect loads to the capacitor pads rather than the device pins.

Most critical are the capacitors for the switching regulator: input capacitor at IN_SBB and output capacitors at SBBx.

Input Capacitor at IN_SBB

Minimize the parasitic inductance from PGND to input capacitor to IN_SBB to reduce ringing on the LXA voltage.

Output Capacitors at SBBx

The output capacitors experience large changes in current as the regulator charges (buck mode) and discharges (both modes) the inductor. In buck mode, the capacitor current ramps up at the same rate as mentioned in the previous section. In buck-boost mode, the capacitor current ramps up very quickly. In both modes, the capacitor current ramps down at a rate of

\frac{{dI}_{C_SBBx}}{dt} = \frac{V_{SBBx}}{L}

from inductor peak current. Since the ramp down can occur in less than 1μs, and the current increases rapidly for buck-boost mode, minimize parasitic inductance from SBBx to output capacitor to PGND.

Inductor

Keep the inductor close to the IC to reduce trace resistance; however, prioritize any regulator input/output capacitors over the inductor. Use the appropriate trace width from LXA to inductor to LXB to support the peak inductor current. Likewise, if there are vias in the path, use an appropriate amount of vias to support the peak current.

Ground Connections

As the switching regulator charges and discharges the inductor, current flows from PGND to the input capacitor ground, from output capacitor ground to PGND, or from output capacitor ground to input capacitor ground. Therefore, use a wide, continuous copper plane to connect PGND to the capacitor grounds.

When connecting the GND and PGND pins together, ensure noise from the power ground does not enter the analog ground (where GND is connected). For example, assuming the ground pins are connected through a solid ground plane on an internal layer, one via connecting GND to the internal ground plane may be sufficient to protect GND from most of the noise in the power-ground plane. Likewise, if there are other higher current or noisy circuitry near this device, avoid connecting the GND pin directly to their grounds.

For more guidelines on proper grounding, visit: https://www.maximintegrated.com/en/design/partners-and-technology/design-technology/ground-layout-board-designers.html.

Example PCB Layout

Figure 24 shows an example layout of the top layer.

Figure 24. PCB Top-Layer and Component Placement Example

Detailed Description—Low Dropout Linear Regulator (LDO)/Load Switch (LSW)

The device includes two on-chip low-dropout linear regulators (LDO0/1) that can also be configured as load switches. These LDOs are optimized to have low-quiescent current. The input voltage range (V_{IN_LDOx}) allows it to be powered directly from the main energy source such as a Li-Poly battery or from an intermediate regulator. Each linear regulator delivers up to 100mA.

Features and Benefits

2x 100mA LDO
LDO Input Voltage Range: 1.71V to 5.5V
LSW Input Voltage Range: 1.3V to 5.5V
Adjustable Output Voltage
100mV Maximum Dropout Voltage at ECT Conditions
Programmable On-Chip Active Discharge

LDO/LSW Simplified Block Diagram

Each LDO/LSW block has one input (IN_LDOx) and one output (LDOx) and several ports that exchange information with the rest of the device (V_REF, EN_LDOx, ADE_LDOx). V_REF comes from the main bias circuits. CNFG_LDOx_B.EN_LDOx and CNFG_LDOx_B.ADE_LDOx are register bits for controlling the enable and active-discharge feature, respectively. See the Register Map for more information.

LDO/LSW Active-Discharge Resistor

Each LDO/LSW block has an active-discharge resistor (R_{AD_LDOx}) that is enabled if CNFG_LDO_B.ADE_LDOx = 1 and LDOx is disabled. Enabling the active discharge feature helps ensure a complete and timely power down of the resource. During power up, if V_SYS > V_POR and CNFG_LDO_B.ADE_LDOx = 1, the active-discharge resistor is enabled.

LDO/LSW Soft-Start

The soft-start feature limits inrush current during startup, and is achieved by limiting the slew rate of the output voltage during startup (dV_{OUT_LDOx}/dt_SS).

More output capacitance results in higher input current surges during startup. The equation and example describes the input current surge phenomenon during startup.

The input current (I_{IN_LDOx}) during soft-start is:

$I_{IN_LDOx} = C_{LDOx} \frac{{dV}_{OUT_LDOx}}{{dt}_{SS}} + I_{OUT_LDOx}$

where:

C_LDOx is the capacitance on the output of the regulator
dV_{OUT_LDOx}/dt_SS is the voltage change rate of the output

For example, given the following conditions, the input current (I_{IN_LDOx}) during soft start is 13.08mA:

Given:

C_LDOx= 2.2µF
dV_{OUT_LDOx}/dt_SS= 1.4mV/µs
LDOx programmed to 1.85V
R_LDOx= 185Ω (I_{OUT_LDOx}= 1.85V/185Ω = 10mA)

Calculation:

I_IN = 2.2µF x 1.4mV/µs + 10mA
I_IN = 13.08mA

Load Switch Configuration

Both LDO0 and LDO1 can be configured as load switches with the CNFG_LDOx_B.LDOx_MD bit. As shown in Figure 26, the transition from LDO to LSW mode is controlled by a defined slew rate until dropout is detected. Once dropout is detected, the load switch is fully closed and the dropout interrupt flag (INT_GLBL.DODx_R) is set.

Figure 26. LDO to LSW Transition Waveform

Applications Information

Input Capacitor Selection

Make sure the input bypass capacitance (C_{IN_LDOx}) is at least 2.2µF. Larger values of C_{IN_LDOx} improve the decoupling for LDOx. The floor plan of the device is such that SBB0 is adjacent to IN_LDOx and if the SIMO channel 0 output powers the input of LDOx, then its output capacitor (C_SBB0) can also serve as C_{IN_LDOx} such that only one capacitor is required.

C_{IN_LDOx} reduces the current peaks drawn from the battery or input power source during operation. The impedance of the input capacitor (ESR, ESL) should be very low (i.e., ESR ≤ 50mΩ and ESL ≤ 5nH) for frequencies up to 0.5MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients.

Output Capacitor Selection

For both LDO and LSW modes, choose the output bypass capacitance (C_LDOx) to be 1μF.

In LDO mode, larger values of C_LDOx improve output PSRR but increase input surge currents during soft-start and output voltage changes. The effective output capacitance should not exceed 2.8μF to maintain stability.

While in LDO mode, C_LDOx is required to keep stability. The series inductance of the output capacitor and its series resistance should be low (i.e., ESR ≤ 10mΩ and ESL ≤ 1nH) for frequencies up to 0.5MHz. Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature coefficients.

A capacitor's effective capacitance decreases with increased DC bias voltage. This effect is more pronounced with smaller capacitor case sizes. Due to this characteristic, 0603 case size capacitors tend to perform well while 0402 case size capacitors of the same value perform poorly.

Detailed Description—I²C Serial Communication General Description

The IC features a revision 3.0 I²C-compatible, 2-wire serial interface consisting of a bidirectional serial data line (SDA) and a serial clock line (SCL). This device acts as a slave-only device, relying on the master to generate a clock signal. SCL clock rates from 0Hz to 3.4MHz are supported.

I²C is an open-drain bus and therefore SDA and SCL require pullups. Optional resistors (24Ω) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize crosstalk and undershoot on bus signals.

Figure 27 shows the functional diagram for the I²C based communications controller. For additional information on I²C, refer to the "I²C Bus Specification and User Manual" which is available for free through the internet.

Features

I²C Revision 3.0 Compatible Serial Communications Channel
0Hz to 100kHz (Standard Mode)
0Hz to 400kHz (Fast Mode)
0Hz to 1MHz (Fast-Mode Plus)
0Hz to 3.4MHz (High-Speed Mode)
Does not utilize I²C Clock Stretching

I²C Simplified Block Diagram

There are three pins (aside from GND) for the I²C-compatible interface. V_IO determines the logic level, SCL is the clock line, and SDA is the data line. Note that the interface does not have the ability to drive the SCL line.

Figure 27. I2C Simplified Block Diagram — Figure 27. I²C Simplified Block Diagram

I²C System Configuration

The I²C-compatible interface is a multimaster bus. The maximum number of devices that can attach to the bus is only limited by bus capacitance.

A device on the I²C bus that sends data to the bus is called a transmitter. A device that receives data from the bus is called a receiver. The device that initiates a data transfer and generates the SCL clock signals to control the data transfer is a master. Any device that is being addressed by the master is considered a slave. The I²C-compatible interface operates as a slave on the I²C bus with transmit and receive capabilities.

Figure 28. I2C System Configuration — Figure 28. I²C System Configuration

I²C Interface Power

The I²C interface derives its power from V_IO. Typically a power input such as V_IO would require a local 0.1μF ceramic bypass capacitor to ground. However, in highly integrated power distribution systems, a dedicated capacitor might not be necessary. If the impedance between V_IO and the next closest capacitor (≥ 0.1μF) is less than 100mΩ in series with 10nH, then a local capacitor is not needed. Otherwise, bypass V_IO to GND with a 0.1µF ceramic capacitor.

V_IO accepts voltages from 1.7V to 3.6V (V_IO). Cycling V_IO does not reset the I²C registers. When V_IO is less than V_IOUVLO and V_SYS is less than V_SYSUVLO, SDA and SCL are high-impedance.

I²C Data Transfer

One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals. See the I²C Start and Stop Conditions section. Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is nine bits long: eight bits of data followed by the acknowledge bit. Data is transferred with the MSB first.

I²C Start and Stop Conditions

When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high. See Figure 29.

A START condition from the master signals the beginning of a transmission to the device. The master terminates transmission by issuing a not-acknowledge followed by a STOP condition (see the I²C Acknowledge Bit section for information on not-acknowledge). The STOP condition frees the bus. To issue a series of commands to the slave, the master can issue repeated start (Sr) commands instead of a STOP command to maintain control of the bus. In general a repeated start command is functionally equivalent to a regular start command.

Figure 29. I2C Start and Stop Conditions — Figure 29. I²C Start and Stop Conditions

I²C Acknowledge Bit

Both the I²C bus master and slave devices generate acknowledge bits when receiving data. The acknowledge bit is the last bit of each nine bit data packet. To generate an acknowledge (A), the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. See Figure 30. To generate a not-acknowledge (nA), the receiving device allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse.

Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time.

This device issues an ACK for all register addresses in the possible address space even if the particular register does not exist.

I²C Slave Address

The I²C controller implements 7-bit slave addressing. An I²C bus master initiates communication with the slave by issuing a START condition followed by the slave address. See Figure 31. The OTP address is factory-programmable for one of two options. See Table 20. All slave addresses not mentioned in Table 20 are not acknowledged.

Table 20. I²C Slave Address Options
ADDRESS	7-BIT SLAVE ADDRESS	8-BIT WRITE ADDRESS	8-BIT READ ADDRESS
Main Address (ADDR = 1)*	0x48, 0b 100 1000	0x90, 0b 1001 0000	0x91, 0b 1001 0001
Main Address (ADDR = 0)*	0x40, 0b 100 0000	0x80, 0b 1000 0000	0x81, 0b 1000 0001
Test Mode**	0x49, 0b 100 1001	0x92, 0b 1001 0010	0x93, 0b 1001 0011

*Perform all reads and writes on the main address. ADDR is a factory one-time programmable (OTP) option, allowing for address changes in the event of a bus conflict. Contact Maxim for more information.

**When test mode is unlocked, the additional address is acknowledged. Test mode details are confidential. If possible, leave the test mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation with Maxim.

I²C Clock Stretching

In general, the clock signal generation for the I²C bus is the responsibility of the master device. The I²C specification allows slow slave devices to alter the clock signal by holding down the clock line. The process in which a slave device holds down the clock line is typically called clock stretching. The IC does not use any form of clock stretching to hold down the clock line.

I²C General Call Address

This device does not implement the I²C specifications general call address and does not acknowledge the general call address (0b0000_0000).

I²C Device ID

This device does not support the I²C Device ID feature.

I²C Communication Speed

This device is compatible with all four communication speed ranges as defined by the Revision 3.0 I²C specification:

0Hz to 100kHz (Standard Mode)
0Hz to 400kHz (Fast Mode)
0Hz to 1MHz (Fast-Mode Plus)
0Hz to 3.4MHz (High-Speed Mode)

Operating in standard mode, fast mode, and fast-mode plus does not require any special protocols. The main consideration when changing bus speed through this range is the combination of the bus capacitance and pullup resistors. Larger values of bus capacitance and pullup resistance increase the time constant (C x R), slowing bus operation. Therefore, when increasing bus speeds, the pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing section of the I²C bus specification and user manual (available for free on the internet) for detailed guidance on the pullup resistor selection. In general for bus capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup resistors, a 400kHz bus needs about 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω pullup resistors. Remember that, while the open-drain bus is low, the pullup resistor is dissipating power, and lower value pullup resistors dissipate more power (V²/R).

Operating in high-speed mode requires some special considerations. For a full list of considerations, refer to the publicly available I²C bus specification and user manual. Major considerations with respect to this part are:

The I²C bus master uses current source pullups to shorten the signal rise.
The I²C slave must use a different set of input filters on its SDA and SCL lines to accommodate for the higher bus.
The communication protocols need to utilize the high-speed master code.

At power-up and after each stop condition, the bus input filters are set for standard mode, fast mode, and fast-mode plus (i.e., 0Hz to 1MHz). To switch the input filters for high-speed mode, use the high-speed master code protocols that are described in the I²C Communication Protocols section.

I²C Communication Protocols

Both writing to and reading from registers are supported as described in the following subsections.

Writing to a Single Register

Figure 32 shows the protocol for the I²C master device to write one byte of data to this device. This protocol is the same as the SMBus specification’s write byte protocol.

The write byte protocol is as follows:

The master sends a start command (S).
The master sends the 7-bit slave address followed by a write bit (R/W = 0).
The addressed slave asserts an acknowledge (A) by pulling SDA low.
The master sends an 8-bit register pointer.
The slave acknowledges the register pointer.
The master sends a data byte.
The slave updates with the new data.
The slave acknowledges or not acknowledges the data byte. The next rising edge on SDA loads the data byte into its target register and the data becomes active.
The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state.

Figure 32. Writing to a Single Register with the Write Byte Protocol

Writing Multiple Bytes to Sequential Registers

Figure 33 shows the protocol for writing to sequential registers. This protocol is similar to the write byte protocol, except the master continues to write after it receives the first byte of data. When the master is done writing, it issues a stop or repeated start.

The writing to sequential registers protocol is as follows:

The master sends a start command (S).
The master sends the 7-bit slave address followed by a write bit (R/W = 0).
The addressed slave asserts an acknowledge (A) by pulling SDA low.
The master sends an 8-bit register pointer.
The slave acknowledges the register pointer.
The master sends a data byte.
The slave acknowledges the data byte. The next rising edge on SDA loads the data byte into its target register and the data becomes active.
Steps 6 to 7 are repeated as many times as the master requires.
During the last acknowledge related clock pulse, the master can issue an acknowledge or a not acknowledge.
The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state.

Figure 33. Writing to Sequential Registers X to N

Reading from a Single Register

Figure 34 shows the protocol for the I²C master device to read one byte of data. This protocol is the same as the SMBus specification’s read byte protocol.

The read byte protocol is as follows:

The master sends a start command (S).
The master sends the 7-bit slave address followed by a write bit (R/W = 0).
The addressed slave asserts an acknowledge (A) by pulling SDA low.
The master sends an 8-bit register pointer.
The slave acknowledges the register pointer.
The master sends a repeated start command (Sr).
The master sends the 7-bit slave address followed by a read bit (R/W = 1).
The addressed slave asserts an acknowledge by pulling SDA low.
The addressed slave places 8-bits of data on the bus from the location specified by the register pointer.
The master issues a not acknowledge (nA).
The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state.

Note that when this device receives a stop, the register pointer is not modified. Therefore, if the master re-reads the same register, it can immediately send another read command, omitting the command to send a register pointer.

Figure 34. Reading from a Single Register with the Read Byte Protocol

Reading from Sequential Registers

Figure 35 shows the protocol for reading from sequential registers. This protocol is similar to the read byte protocol except the master issues an acknowledge to signal the slave that it wants more data: when the master has all the data it requires it issues a not acknowledge (nA) and a stop (P) to end the transmission. The continuous read from sequential registers protocol is as follows:

The master sends a start command (S).
The master sends the 7-bit slave address followed by a write bit (R/W = 0).
The addressed slave asserts an acknowledge (A) by pulling SDA low.
The master sends an 8-bit register pointer.
The slave acknowledges the register pointer.
The master sends a repeated start command (Sr).
The master sends the 7-bit slave address followed by a read bit (R/W = 1).
The addressed slave asserts an acknowledge by pulling SDA low.
The addressed slave places 8-bits of data on the bus from the location specified by the register pointer.
The master issues an acknowledge (A) signaling the slave that it wishes to receive more data.
Steps 9 to 10 are repeated as many times as the master requires. Following the last byte of data, the master must issue a not acknowledge (nA) to signal that it wishes to stop receiving data.
The master sends a stop condition (P) or a repeated start condition (Sr). Issuing a stop (P) ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state.

Note that when this device receives a stop it does not modify its register pointer. Therefore, if the master re-reads the same register, it can immediately send another read command, omitting the command to send a register pointer.

Figure 35. Reading Continuously from Sequential Registers X to N

Engaging HS-Mode for Operation up to 3.4MHz

Figure 36 shows the protocol for engaging HS-mode operation. HS-mode operation allows for a bus operating speed up to 3.4MHz. The engaging HS-mode protocol is as follows:

Begin the protocol while operating at a bus speed of 1MHz or lower.
The master sends a start command (S).
The master sends the 8-bit master code of 0b0000 1XXX where 0bXXX are don’t care bits.
The addressed slave issues a not acknowledge (nA).
The master may now increase its bus speed up to 3.4MHz and issue any read/write operation.

The master may continue to issue high-speed read/write operations until a stop (P) is issued. To continue operations in high-speed mode, use repeated start (Sr)