Pin Specifications

Pin Description
PIN	NAME	FUNCTION
1	1	DET	Detection Resistor Input. Connect a signature resistor (R_DET= 24.9kΩ) from DET to V_DD.
2	2	V_DD	Positive Supply Input. Connect minimum 68nF bypass capacitor between V_DD and V_SS.
3	3	NC	No Connection. Not internally connected.
4	4	CLSB	Classification Resistor Input. Connect a resistor (R_CLS) from CLSB to V_SSto set classification current for 3bt Standard. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification.
5, 6	5, 6	V_SS	Negative Supply Input. V_SS connects to the source of the integrated isolation n-channel power MOSFET.
7, 8	7, 8	RTN	Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground, as shown in the Typical Application Circuit.
9	9	WAD	Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment V_DD - V_SS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used.
10	10	PG	Open-Drain, Power-Good Indicator Output. PG sinks 230μA to disable the downstream DC-DC converter while turning on the MOSFET switch. PG current sink is disabled during detection, classification, and in the steady-state power mode. The PG current sink is turned on to disable the downstream DC-DC converter when the device is in sleep mode or Ultra-Low-Power sleep mode.
11	11	MEC	Multi-Event Classification or Wall Adapter Indication Output. This pin is an Open-drain output and it generates different duty cycle patterns to indicate 5 different power level allocated by PSE. It also generates specific pattern to indicate when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. MEC is turned off when the device is in sleep mode and Ultra-Low-Power mode.
12	12	CLSA	Classification Resistor Input. Connect a resistor (R_CLS) from CLSA to V_SSto set the classification current for 3at/af. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification
13	—	LED	LED Driver Output. During sleep mode/Ultra-Low-Power sleep mode (MAX5995A/B) and MPS mode (MAX5995B/C), the LED sources a periodic current pulses at 250Hz with 25% duty cycle and the current amplitude is set by the resistor connected from SL to V_SS.
—	13	NC	Not Connected.
14	—	SL	Sleep Mode Enable Input. In the MAX5995B, a falling edge on SL brings the device into sleep mode (V_SL must drop below 0.75V). In the MAX5995A, V_SL must remain below the threshold (0.75V) for a period of at least 6s after falling edge to bring the device into sleep mode. An external resistor (R_SL) connected between SL and V_SS sets the LED current (I_LED) amplitude.
—	14	NC	Not Connected.
15	—	WK	Wake Mode Enable Input. WK has an internal 2.5kΩ pullup resistor to the internal 5V bias rail. A falling edge on WK brings the device out of sleep mode or Ultra-Low-Power sleep mode and resume normal operation.
—	15	AUC	Connect a resistor (no worse than 1% accuracy) between AUC and V_SS to program the duty cycle of MPS current to further reduce the power consumption in MPS mode. There are 4 settings: floating (> 25%), 332kΩ (15%), 121kΩ (10%), and short to V_SS (5%).
16	—	ULP	Ultra-Low-Power Sleep Enable Input (in Sleep Mode). ULP has an internal 50kΩ pullup resistor to the internal 5V bias rail. A falling edge on SL in the MAX5995B (and a 6s period below the SL threshold in the MAX5995A), while ULP is asserted low enables Ultra-Low-Power sleep mode. When Ultra-Low-Power sleep mode is enabled, the power consumption of the device is reduced even lower than normal sleep mode to comply with Ultra-Low-Power sleep power requirements while still generating MPS current.
—	16	NC	Not Connected.
–	–	EP	Exposed Pad. Do not use EP as an electrical connection to V_SS. EP is internally connected to V_SS through a resistive path and must be connected to V_SS externally. To optimize power dissipation, solder the exposed pad to a large copper power plane.

1

DET

Detection Resistor Input. Connect a signature resistor (R_DET= 24.9kΩ) from DET to V_DD.

2

V_DD

Positive Supply Input. Connect minimum 68nF bypass capacitor between V_DD and V_SS.

3

NC

No Connection. Not internally connected.

4

CLSB

Classification Resistor Input. Connect a resistor (R_CLS) from CLSB to V_SSto set classification current for 3bt Standard. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification.

5, 6

V_SS

Negative Supply Input. V_SS connects to the source of the integrated isolation n-channel power MOSFET.

7, 8

RTN

Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground, as shown in the Typical Application Circuit.

9

WAD

Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment V_DD - V_SS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used.

10

PG

Open-Drain, Power-Good Indicator Output. PG sinks 230μA to disable the downstream DC-DC converter while turning on the MOSFET switch. PG current sink is disabled during detection, classification, and in the steady-state power mode. The PG current sink is turned on to disable the downstream DC-DC converter when the device is in sleep mode or Ultra-Low-Power sleep mode.

11

MEC

Multi-Event Classification or Wall Adapter Indication Output. This pin is an Open-drain output and it generates different duty cycle patterns to indicate 5 different power level allocated by PSE. It also generates specific pattern to indicate when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. MEC is turned off when the device is in sleep mode and Ultra-Low-Power mode.

12

CLSA

Classification Resistor Input. Connect a resistor (R_CLS) from CLSA to V_SSto set the classification current for 3at/af. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification

13

—

LED

LED Driver Output. During sleep mode/Ultra-Low-Power sleep mode (MAX5995A/B) and MPS mode (MAX5995B/C), the LED sources a periodic current pulses at 250Hz with 25% duty cycle and the current amplitude is set by the resistor connected from SL to V_SS.

—

13

NC

Not Connected.

14

—

SL

Sleep Mode Enable Input. In the MAX5995B, a falling edge on SL brings the device into sleep mode (V_SL must drop below 0.75V). In the MAX5995A, V_SL must remain below the threshold (0.75V) for a period of at least 6s after falling edge to bring the device into sleep mode. An external resistor (R_SL) connected between SL and V_SS sets the LED current (I_LED) amplitude.

—

14

NC

Not Connected.

15

—

WK

Wake Mode Enable Input. WK has an internal 2.5kΩ pullup resistor to the internal 5V bias rail. A falling edge on WK brings the device out of sleep mode or Ultra-Low-Power sleep mode and resume normal operation.

—

15

AUC

Connect a resistor (no worse than 1% accuracy) between AUC and V_SS to program the duty cycle of MPS current to further reduce the power consumption in MPS mode. There are 4 settings: floating (> 25%), 332kΩ (15%), 121kΩ (10%), and short to V_SS (5%).

16

—

ULP

Ultra-Low-Power Sleep Enable Input (in Sleep Mode). ULP has an internal 50kΩ pullup resistor to the internal 5V bias rail. A falling edge on SL in the MAX5995B (and a 6s period below the SL threshold in the MAX5995A), while ULP is asserted low enables Ultra-Low-Power sleep mode. When Ultra-Low-Power sleep mode is enabled, the power consumption of the device is reduced even lower than normal sleep mode to comply with Ultra-Low-Power sleep power requirements while still generating MPS current.

—

16

NC

Not Connected.

–

EP

Exposed Pad. Do not use EP as an electrical connection to V_SS. EP is internally connected to V_SS through a resistive path and must be connected to V_SS externally. To optimize power dissipation, solder the exposed pad to a large copper power plane.

PIN		NAME	FUNCTION
MAX5995A/B	MAX5995C	NAME	FUNCTION
1	1	DET	Detection Resistor Input. Connect a signature resistor (R_DET= 24.9kΩ) from DET to V_DD.
2	2	V_DD	Positive Supply Input. Connect minimum 68nF bypass capacitor between V_DD and V_SS.
3	3	NC	No Connection. Not internally connected.
4	4	CLSB	Classification Resistor Input. Connect a resistor (R_CLS) from CLSB to V_SSto set classification current for 3bt Standard. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification.
5, 6	5, 6	V_SS	Negative Supply Input. V_SS connects to the source of the integrated isolation n-channel power MOSFET.
5, 6	5, 6	V_SS
7, 8	7, 8	RTN	Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground, as shown in the Typical Application Circuit.
7, 8	7, 8	RTN
9	9	WAD	Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment V_DD - V_SS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used.
10	10	PG	Open-Drain, Power-Good Indicator Output. PG sinks 230μA to disable the downstream DC-DC converter while turning on the MOSFET switch. PG current sink is disabled during detection, classification, and in the steady-state power mode. The PG current sink is turned on to disable the downstream DC-DC converter when the device is in sleep mode or Ultra-Low-Power sleep mode.
11	11	MEC	Multi-Event Classification or Wall Adapter Indication Output. This pin is an Open-drain output and it generates different duty cycle patterns to indicate 5 different power level allocated by PSE. It also generates specific pattern to indicate when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. MEC is turned off when the device is in sleep mode and Ultra-Low-Power mode.
12	12	CLSA	Classification Resistor Input. Connect a resistor (R_CLS) from CLSA to V_SSto set the classification current for 3at/af. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification
13	—	LED	LED Driver Output. During sleep mode/Ultra-Low-Power sleep mode (MAX5995A/B) and MPS mode (MAX5995B/C), the LED sources a periodic current pulses at 250Hz with 25% duty cycle and the current amplitude is set by the resistor connected from SL to V_SS.
—	13	NC	Not Connected.
14	—	SL	Sleep Mode Enable Input. In the MAX5995B, a falling edge on SL brings the device into sleep mode (V_SL must drop below 0.75V). In the MAX5995A, V_SL must remain below the threshold (0.75V) for a period of at least 6s after falling edge to bring the device into sleep mode. An external resistor (R_SL) connected between SL and V_SS sets the LED current (I_LED) amplitude.
—	14	NC	Not Connected.
15	—	WK	Wake Mode Enable Input. WK has an internal 2.5kΩ pullup resistor to the internal 5V bias rail. A falling edge on WK brings the device out of sleep mode or Ultra-Low-Power sleep mode and resume normal operation.
—	15	AUC	Connect a resistor (no worse than 1% accuracy) between AUC and V_SS to program the duty cycle of MPS current to further reduce the power consumption in MPS mode. There are 4 settings: floating (> 25%), 332kΩ (15%), 121kΩ (10%), and short to V_SS (5%).
16	—	ULP	Ultra-Low-Power Sleep Enable Input (in Sleep Mode). ULP has an internal 50kΩ pullup resistor to the internal 5V bias rail. A falling edge on SL in the MAX5995B (and a 6s period below the SL threshold in the MAX5995A), while ULP is asserted low enables Ultra-Low-Power sleep mode. When Ultra-Low-Power sleep mode is enabled, the power consumption of the device is reduced even lower than normal sleep mode to comply with Ultra-Low-Power sleep power requirements while still generating MPS current.
—	16	NC	Not Connected.
–	–	EP	Exposed Pad. Do not use EP as an electrical connection to V_SS. EP is internally connected to V_SS through a resistive path and must be connected to V_SS externally. To optimize power dissipation, solder the exposed pad to a large copper power plane.