| Package Code | T1655+4 |
| Outline Number | 21-0140 |
| Land Pattern Number | 90-0121 |
| Thermal Resistance, Four-Layer Board: | |
| Junction-to-Ambient (θJA) | 35°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 2.7°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opMAX5995BETE%2BT
data-opMAX5995BETE%2B
data-opMAX5995BATE%2B
data-opMAX5995BATE%2BT
Detection Resistor Input. Connect a signature resistor (RDET = 24.9kΩ) from DET to VDD.Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.Not Connected.Classification Resistor Input. Connect a resistor (RCLS) from CLSB to VSS to set classification current for 3bt Standard. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification.Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power MOSFET.Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground, as shown in the Typical Application Circuit.Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment VDD - VSS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used.Open-Drain, Power-Good Indicator Output. PG sinks 230μA to disable the downstream DC-DC converter while turning on the MOSFET switch. PG current sink is disabled during detection, classification, and in the steady-state power mode. The PG current sink is turned on to disable the downstream DC-DC converter when the device is in sleep mode or Ultra-Low-Power sleep mode.Multi-Event Classification or Wall Adapter Indication Output. This pin is an Open-drain output and it generates different duty cycle patterns to indicate 5 different power level allocated by PSE. It also generates specific pattern to indicate when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. MEC is turned off when the device is in sleep mode and Ultra-Low-Power mode.Classification Resistor Input. Connect a resistor (RCLS) from CLSA to VSS to set the classification current for 3at/af. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classificationLED Driver Output. During sleep mode/Ultra-Low-Power sleep mode (MAX5995A/B) and MPS mode (MAX5995B/C), the LED sources a periodic current pulses at 250Hz with 25% duty cycle and the current amplitude is set by the resistor connected from SL to VSS.Sleep Mode Enable Input. In the MAX5995B, a falling edge on SL brings the device into sleep mode (VSL must drop below 0.75V). In the MAX5995A, VSL must remain below the threshold (0.75V) for a period of at least 6s after falling edge to bring the device into sleep mode. An external resistor (RSL) connected between SL and VSS sets the LED current (ILED) amplitude.Wake Mode Enable Input. WK has an internal 2.5kΩ pullup resistor to the internal 5V bias rail. A falling edge on WK brings the device out of sleep mode or Ultra-Low-Power sleep mode and resume normal operation.Connect a resistor (no worse than 1% accuracy) between AUC and VSS to program the duty cycle of MPS current to further reduce the power consumption in MPS mode. There are 4 settings: floating (> 25%), 332kΩ (15%), 121kΩ (10%), and short to VSS (5%).Ultra-Low-Power Sleep Enable Input (in Sleep Mode). ULP has an internal 50kΩ pullup resistor to the internal 5V bias rail. A falling edge on SL in the MAX5995B (and a 6s period below the SL threshold in the MAX5995A), while ULP is asserted low enables Ultra-Low-Power sleep mode. When Ultra-Low-Power sleep mode is enabled, the power consumption of the device is reduced even lower than normal sleep mode to comply with Ultra-Low-Power sleep power requirements while still generating MPS current.Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally connected to VSS through a resistive path and must be connected to VSS externally. To optimize power dissipation, solder the exposed pad to a large copper power plane.