Functional Diagram
Functional Diagrams
MAX5995A/MAX5995B
Detection Resistor Input. Connect a signature resistor (RDET = 24.9kΩ) from DET to VDD.
DET
DET
5V REGULATOR
5V
REGULATOR
CLASSIFICATION
CLASSIFICATION
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
Classification Resistor Input. Connect a resistor (RCLS) from CLSA to VSS to set the classification current for 3at/af. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification
CLSA
CLSA
Classification Resistor Input. Connect a resistor (RCLS) from CLSB to VSS to set classification current for 3bt Standard. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification.
CLSB
CLSB
EN
EN
Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power MOSFET.
VSS
V
SS
Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground, as shown in the Typical Application Circuit.
RTN
RTN
Multi-Event Classification or Wall Adapter Indication Output. This pin is an Open-drain output and it generates different duty cycle patterns to indicate 5 different power level allocated by PSE. It also generates specific pattern to indicate when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. MEC is turned off when the device is in sleep mode and Ultra-Low-Power mode.
MEC
MEC
Event Detection
EVENT
DETECTION
Open-Drain, Power-Good Indicator Output. PG sinks 230μA to disable the downstream DC-DC converter while turning on the MOSFET switch. PG current sink is disabled during detection, classification, and in the steady-state power mode. The PG current sink is turned on to disable the downstream DC-DC converter when the device is in sleep mode or Ultra-Low-Power sleep mode.
PG
PG
Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment VDD - VSS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used.
WAD
WAD
9V
9V
GATE OK
GATE OK
Gate Control
GATE
CONTROL
5V
5V
THERMAL SHUTDOWN
THERMAL
SHUTDOWN
RTN VOLTAGE
RTN
VOLTAGE
SWITCH CURRENT
SWITCH
CURRENT
Logic Control
LOGIC CONTROL
LED Driver Output. During sleep mode/Ultra-Low-Power sleep mode (MAX5995A/B) and MPS mode (MAX5995B/C), the LED sources a periodic current pulses at 250Hz with 25% duty cycle and the current amplitude is set by the resistor connected from SL to VSS.
LED
LED
Sleep Mode Enable Input. In the MAX5995B, a falling edge on SL brings the device into sleep mode (VSL must drop below 0.75V). In the MAX5995A, VSL must remain below the threshold (0.75V) for a period of at least 6s after falling edge to bring the device into sleep mode. An external resistor (RSL) connected between SL and VSS sets the LED current (ILED) amplitude.
SL
SL
5V
5V
2.5KΩ
2.5K
Ω
5V
5V
50KΩ
50K
Ω
Wake Mode Enable Input. WK has an internal 2.5kΩ pullup resistor to the internal 5V bias rail. A falling edge on WK brings the device out of sleep mode or Ultra-Low-Power sleep mode and resume normal operation.
WK
WK
Ultra-Low-Power Sleep Enable Input (in Sleep Mode). ULP has an internal 50kΩ pullup resistor to the internal 5V bias rail. A falling edge on SL in the MAX5995B (and a 6s period below the SL threshold in the MAX5995A), while ULP is asserted low enables Ultra-Low-Power sleep mode. When Ultra-Low-Power sleep mode is enabled, the power consumption of the device is reduced even lower than normal sleep mode to comply with Ultra-Low-Power sleep power requirements while still generating MPS current.
ULP
ULP
PG LOGIC
PG
LOGIC
Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power MOSFET.
VSS
VSS
5V
5V
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
Von/vOFF
V
ON
/
V
OFF
1.5mA
1.5mA
230uA
230uA
46uA
46uA
MAX5995C
Detection Resistor Input. Connect a signature resistor (RDET = 24.9kΩ) from DET to VDD.
DET
DET
5V REGULATOR
5V
REGULATOR
CLASSIFICATION
CLASSIFICATION
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
Classification Resistor Input. Connect a resistor (RCLS) from CLSA to VSS to set the classification current for 3at/af. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification
CLSA
CLSA
Classification Resistor Input. Connect a resistor (RCLS) from CLSB to VSS to set classification current for 3bt Standard. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification.
CLSB
CLSB
EN
EN
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power MOSFET.
VSS
V
SS
Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground, as shown in the Typical Application Circuit.
RTN
RTN
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
1.5mA
1.5mA
Multi-Event Classification or Wall Adapter Indication Output. This pin is an Open-drain output and it generates different duty cycle patterns to indicate 5 different power level allocated by PSE. It also generates specific pattern to indicate when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. MEC is turned off when the device is in sleep mode and Ultra-Low-Power mode.
MEC
MEC
Event Detection
EVENT
DETECTION
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
230µA
230
µ
A
Open-Drain, Power-Good Indicator Output. PG sinks 230μA to disable the downstream DC-DC converter while turning on the MOSFET switch. PG current sink is disabled during detection, classification, and in the steady-state power mode. The PG current sink is turned on to disable the downstream DC-DC converter when the device is in sleep mode or Ultra-Low-Power sleep mode.
PG
PG
Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment VDD - VSS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used.
WAD
WAD
9V
9V
GATE OK
GATE OK
GATE CONTROL
GATE
CONTROL
46µA
46
µ
A
5V
5V
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
VON/VOFF
VON/VOFF
THERMAL SHUTDOWN
THERMAL
SHUTDOWN
RTN VOLTAGE
RTN
VOLTAGE
SWITCH CURRENT
SWITCH
CURRENT
Logic Control
LOGIC CONTROL
Positive Supply Input. Connect minimum 68nF bypass capacitor between VDD and VSS.
VDD
V
DD
Connect a resistor (no worse than 1% accuracy) between AUC and VSS to program the duty cycle of MPS current to further reduce the power consumption in MPS mode. There are 4 settings: floating (> 25%), 332kΩ (15%), 121kΩ (10%), and short to VSS (5%).
AUC
AUC
PG LOGIC
PG
LOGIC
5V
5V
