Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics

(VIN = (VDD - VSS) = 48V, RCLSA = 619Ω, RCLSB  = 619Ω, and RSL = 60.4kΩ. RTN, WAD, PG, MEC, WK and ULP unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40°C to +125°C (MAX5995AATE/BATE/CATE) or -40°C to +85°C (MAX5995AETE/BETE/CETE), unless otherwise noted. Typical values are at TA = +25ºC. (Note 3))
DETECTION MODE
Input Offset Current IOFFSET VIN = 1.4V to 10.1V (Note 4) 10 µA
Effective Differential Input Resistance dR VIN = 1.4V up to 10.1V with 1V step, VDD = RTN = WAD = PG = MEC (Note 5) 23.95 25 25.5 kΩ
CLASSIFICATION MODE
Classification Disable Threshold VTH,CLS VIN rising (Note 6) 22 22.8 23.6 V
Classification Stability Time 0.2 ms
Classification Current ICLASS VIN = 12.5V to 20.5V, VDD = RTN = WAD = PG, RCLS_= 619Ω 0 3.96 mA
VIN = 12.5V to 20.5V, VDD = RTN = WAD = PG, RCLS = 118Ω 9.12 11.88
VIN = 12.5V to 20.5V, VDD = RTN = WAD = PG, RCLS_ = 66.5Ω 17.2 19.8
VIN = 12.5V to 20.5V, VDD = RTN = WAD = PG, RCLS_ = 43.2Ω 26.3 29.7
VIN = 12.5V to 20.5V, VDD = RTN = WAD = PG, RCLS_ = 30.9Ω 36.4 43.6
Mark Event Threshold VTHM VIN falling 10.1 10.7 11.6 V
Hysteresis on Mark Event Threshold 0.82 V
Mark Event Current IMARK VIN falling to enter mark event,
5.2V < VIN < 10.1V 		1.0 3.5 mA
Reset Event Threshold VTHR VIN falling 2.8 3.8 5.2 V
POWER MODE
VIN Supply Voltage Range 60 V
VIN Supply Current IQ Current through internal MOSFET = 0 0.25 0.75 mA
VIN Turn-On Voltage VON VIN rising 34.3 35.4 36.6 V
VIN Turn-Off Voltage VOFF VIN falling 30 V
VIN Turn-On/-Off Hysteresis VHYST_UVLO (Note 7) 4.2 V
VIN Deglitch Time tOFF_DLY VIN falling from 40V to 20V (Note 8) 30 120 µs
Inrush to Operating Mode Delay tDELAY From PG pulled low to high when entering into power mode, VIN = 48V, COUT = 47µF 90 96 102 ms
Isolation Power MOSFET On-Resistance RON_ISO IRTN = 950mA, TJ = +25°C 0.1 0.2 Ω
IRTN = 950mA, TJ = +85°C 0.15 0.25
IRTN = 950mA, TJ = +125°C 0.2
RTN Leakage Current IRTN_LKG VRTN = 12.5V to 30V 10 µA
CURRENT LIMIT
Inrush Current Limit IINRUSH During initial turn-on period, VRTN - VSS = 1.5V 90 135 182 mA
Current Limit During Normal Operation ILIM 5 Event Detected After inrush completed, VRTN = 1V (Note 9) 1800 2400 3000 mA
1 to 4 Event Detected After inrush completed, VRTN = 1V (Note 9) 1600 1800 2250
Current Limit in Foldback Condition ILIM_FLDBK Both during inrush and after inrush completed VRTN - VSS = 7.5V 53 mA
Foldback Threshold VRTN (Note 10) 6.5 7 7.5 V
LOGIC
WAD Detection Threshold VWAD-REF VWAD rising, VIN = 14V to 48V (referenced to RTN) 8 9 10 V
WAD Detection Threshold Hysteresis VWAD rising, VRTN = 0V, VSS unconnected 0.35 V
WAD Input Current IWAD_LKG VWAD = 10V (referenced to RTN) 3.5 µA
PG Sink Current VRTN = 1.5V, VPG = 0.8V, during inrush period 125 230 375 µA
PG Off-Leakage Current VPG = 60V 1 µA
MEC
Pulse Width of START Bit 256 μs
50% Pulse Width 512 μs
75% Pulse Width 768 μs
Repetitive Period 1024 μs
MEC Sink Current VMEC = 3.5V (referenced to RTN), VSS disconnected 1 1.5 2.35 mA
MEC Off-Leakage Current VMEC = 48V 1 µA
SLEEP MODE/ULTRA-LOW-POWER SLEEP MODE (MAX5995A/MAX5995B)
WK and ULP Logic Threshold VTH WK falling and ULP rising and falling 1.5 3 V
SL Logic Threshold SL falling 0.75 0.8 0.85 V
SL Current RSL = 0Ω  140 µA
LED Current Amplitude ILED RSL = 60.4kΩ, VLED = 3.5V (MAX5995A/MAX5995B) 10 10.5 11.5 mA
RSL = 30.1kΩ, VLED = 3.75V  19.5 20.9 22.5
RSL = 30.1kΩ, VLED = 4V 19
LED Current Programmable Range 10 20 mA
LED Current with Grounded SL VSL = 0V 20.5 24.5 28.5 mA
LED Current Frequency fILED Sleep and Ultra-Low-Power sleep modes 250 Hz
LED Current Duty Cycle DILED Sleep and Ultra-Low-Power sleep modes 25 %
VDD Current Amplitude IVDD Normal sleep mode, VLED = 3.5V 10 11 12.2 mA
Internal Current Duty Cycle DIVDD Normal and Ultra-Low-Power sleep modes 75 %
Internal Current Enable Time tULP Ultra-Low-Power sleep mode 80 84 90 ms
Internal Current Disable Time tULP_DIS Ultra-Low-Power sleep mode 217 228 240 ms
SL Delay Time tSL Time VSL must remain below the SL logic threshold to enter sleep and Ultra-Low-Power modes (MAX5995A) 5.4 6 6.6 s
AUTOCLASS (MAX5995C)
AUTOCLASS Detection Time 76 87 ms
AUC (MAX5995C)
AUC Pullup Current IAUC_PUP 8.5 9 9.5 µA
AUC Voltage Threshold VAUC1 0.47 0.5 0.53 V
VAUC2 1.73 1.8 1.87
VAUC3 4.31 4.4 4.49
MAINTAIN POWER SIGNATURE
PoE MPS Current Rising Threshold IMPS_RISE MAX5995B/MAX5995C 28.7 mA
PoE MPS Current Falling Threshold IMPS_FALL MAX5995B/MAX5995C 24 mA
PoE MPS Current Threshold Hysteresis IMPS_HYS MAX5995B/MAX5995C 4.3 mA
PoE MPS Time High tMPS_HIGH Default for MAX5995A/MAX5995B, AUC floating for MAX5995C 80 84 90 ms
PoE MPS Time Low tMPS_LOW Default for MAX5995A/MAX5995B, AUC floating for MAX5995C 217 228 240 ms
PoE MPS Time High tMPS_HIGH AUC 332K 1%tollerance  to VSS (MAX5995C) 45 48 51 ms
PoE MPS Time Low tMPS_LOW AUC 332K 1% tolerance to VSS (MAX5995C) 252 264 275 ms
PoE MPS Time High tMPS_HIGH AUC 121K 1% tolerance to VSS (MAX5995C) 30 32 34 ms
PoE MPS Time Low tMPS_LOW AUC 121K 1% tolerance to VSS (MAX5995C) 268 280 292 ms
PoE MPS Time High tMPS_HIGH AUC short to VSS (MAX5995C) 14 16 18 ms
PoE MPS Time Low tMPS_LOW AUC short to VSS (MAX5995C) 280 296 308 ms
THERMAL SHUTDOWN
Thermal-Shutdown Threshold TSD TJ rising 150 °C
Thermal-Shutdown Hysteresis VCDLY_HYS TJ falling 30 °C
Note 3: All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Detailed Desciption.
Note 5: Effective differential input resistance is defined as the differential resistance between VDD and VSS.
Note 6: Classification current is turned off whenever the device is in power mode.
Note 7: UVLO hysteresis is guaranteed by design, not production tested.
Note 8: A 20V glitch on input voltage, which takes VDD below VON shorter than or equal to tOFF_DLY does not cause the MAX5995A/MAX5995B/MAX5995C to exit power-on mode.
Note 9: Maximum current limit during normal operation is guaranteed by design; not production tested.
Note 10: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload condition across VDD and RTN.

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{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 6\u003c/strong\u003e","data-html":true,"data-content":"Classification current is turned off whenever the device is in power mode."}

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{"data-trigger":"hover","data-placement":"right","data-toggle":"popover","data-original-title":"\u003cstrong\u003eNote 9\u003c/strong\u003e","data-html":true,"data-content":"Maximum current limit during normal operation is guaranteed by design; not production tested."}

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