Detailed Description

In detection mode, the power source equipment (PSE) applies two voltages on V_IN in the 1.4V to 10.1V range (1V step minimum) and then records the current measurements at the two points. The PSE then computes ΔV/ΔI to ensure the presence of the 24.9kΩ signature resistor.

In detection mode, most of device internal circuitry is off and the offset current is less than 10μA. If the voltage applied to the PD is reversed, install protection diodes at the input terminal to prevent internal damage to the devices (see the Typical Application Circuit). Since the PSE uses a slope technique (ΔV/ΔI) to calculate the signature resistance, the DC offset due to the protection diodes is subtracted and does not affect the detection process.

In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. Two external resistors connected CLSA/CLSB to V_SS set classification signature to the PSE and define the power consumption requested from the PD. R_CLSA sets classification current for the 1st and 2nd class events for 0~4 class PD complaint with IEEE 802.3af/at standard, and R_CLSB set classification current for the 3rd to 5th class event for 0~8 class PD complaint with IEEE 802.3bt standard.

The PSE classifies the PD by applying a voltage at the PD input and measuring the current sourced out of the PSE. When the PSE applies a voltage between 12.5V and 20.5V, the devices exhibit a series of events with current characteristic. Table 1 shows the R_CLSA and R_CLSB resistor values needed to set for PD class and the PD power consumption defined by standards. The PSE uses the number of class events and classification current information to classify the power requirement of the PD. The classification current includes the current drawn by R_CLSA and R_CLSB and the supply current of the devices so the total current drawn by the PD is within the IEEE 802.3bt standard. The classification current is turned off whenever the device is in power mode.

IEEE 802.3bt defines physical classification to allow a PD to communicate its power classification to the connected PSE and to allow the PSE to inform the PD of the PSE’s available power. The PD classes (0~8) and PD power requests during Multi-Event Classification is configured by setting the R_CLSA and R_CLSB resistor values in Table 1. This configuration is compatible with IEEE 802.3af/at standard.

In a 1-Event classification, the PD is a 3af/at Class 0~3 PD. In a 2-Event classification, the PD is 3at Class 4 PD. In a 3-Event classification, the PD can be a 3bt PD at Class 0 to Class 4 depending on the classification current levels, and in this case the PD can take as high as 30W power from a 3bt PSE. In a 4-Event classification, the PD can be 3bt Class 5 PD with 45W, or 3bt Class 6 PD with 60W input power from PSE. If the third and fourth event the classification current are 10mA/20mA, it means PD power requests gets demotion from PSE. In a 5-Event classification, the PD can be 3bt PD Class 7 with 75W, Or a 3bt PD Class 8 with 90W input power from PSE.

The power demotion feature is provided for the situation where the power level PD requested is not available at the PSE. When power demotion occurs, the PD must operate in a reduced power mode while connected to lower power PSE. In Power Demotion mode, the PSE is going to provide the power that its classification indicates. For example, a 3af PSE only issue a single event even there is a Class 4 PD connected.

This feature is applicable in 4P PoE as well. For example, when a Class 5/6 PD connected to a PSE, the PSE only initiate 3-Event. It indicated the PSE supports 4P operation but can only deliver power up to 30W. Refer to Table 1 for more details.

The device communicates its available power level to the system user through the MEC pin. The MEC pin state is a result of the number of classification/mark events, and whether the PD is in PoE or auxiliary power operation. The MEC pin can indicate power allocated from PSE to PD in 5 different cases.The devices uses a unique encoding method on the MEC pin to indicate the power levels that are higher than 12.95W. First pulse sent from MEC is START bit (256µs, 25% duty) for system to detect. Then the pattern of 2nd, 3rd, and 4th pulse width that is double or triple pulse width of the START bit (50% and 75% duty) is issued to indicate the type of PSE and power allocated from PSE. This pulse train is repeatable at certain frequency.

Number of event and the maximum power granted from the PSE at PD input are listed in Table 2. 1-Event and 2-Event are with IEEE802.3af/at standard. 3-Event, 4-Event, and 5-Event indicate PD Class (0~8) in IEEE802.3bt standard.

MEC is enabled after the isolation MOSFET is fully on until V_IN drops below the UVLO threshold. The MEC is turned off when the device is in sleep mode and Ultra-Low-Power mode.

The intelligent MPS feature is provided by MAX5995B/MAX5995C. It enables applications that require low power standby modes. The MPS current is generated to comply with the IEEE 802.3bt standard for PSE to maintain power on in standby modes. A minimum current (10mA) of the port is able to be maintained with MPS mode to avoid the power disconnection from the PSE. The devices automatically enter MPS mode when the port current is lower than 24mA (typ) and exit MPS mode when the port current is greater than 28.7mA (typ).

Below drawing shows intelligent MPS behavior. The MPS comparator is autozero comparator and it will sample the port current every 32µs. The MPS comparator is always switched on when the MOSFET is fully turned on. If MPS comparator falling threshold is triggered continuously within 320µs, the part enters MPS mode and MPS current is generated. Once the part enter MPS mode it waits for the TMPS timer to elapse before check the MPS comparator again.

In MPS mode, Intelligent MPS modulation scheme is shown in Figure 3 (MPS Duty Cycle is 25% or 84ms), and the LED driver output (LED) sources periodic current pulses at 250Hz with 25% duty cycle and current amplitude can be configured by an resistor (R_SL) on SL pin. PG remains high to enable downstream dc-dc converter in MPS mode. Once MPS mode is entered, sleep mode or Ultra-Low-Power sleep mode will not take effect (MAX5995B).

The MAX5995A/MAX5995B feature a sleep mode, which pulls PG low to disable downstream DC-DC converters to minimize the power consumption of the overall PD system, while at the same time still keeps the internal MOSFET turned on and generate a MPS current at V_DD to remain the PSE connection. However, when MAX5995B Intelligent MPS is enabled, and once the device enters MPS mode, sleep mode or Ultra-Low-Power sleep mode will not take effect. In sleep mode, the LED driver output (LED) sources a pulsating current and current amplitude can be configured by an external resistor (R_SL) on SL pin. To enable sleep mode, apply a falling edge to SL pin (MAX5995B) or hold SL pin low for a minimum of 6 seconds after a falling edge (MAX5995A).

An Ultra-Low-Power sleep mode allows the MAX5995A/MAX5995B to further reduce power consumption while still maintaining pulsed MPS current required by standard at V_DD. In Ultra-Low-Power sleep mode, the LED driver output (LED) sources periodic current pulses at 250Hz with 25% duty cycle and current amplitude can be configured by an resistor (R_SL) on SL pin; the Ultra-Low-Power sleep enable input ULP is internally held high with a 50kΩ pullup resistor to the internal 5V bias of the MAX5995A/MAX5995B. To enable Ultra-Low-Power sleep mode, set ULP pin to logic-low and apply a falling edge to SL (MAX5995B) or hold SL low for a minimum of 6s (MAX5995A).

Apply a falling edge on the wake-mode enable input (WK) to disable sleep or Ultra-Low-Power sleep mode and resume normal operation. The PG pin is pulled low when the devices are in sleep mode or Ultra-Low-Power sleep mode, and pulled high once enable WK to resume normal operation.

The MAX5995A/MAX5995B drive an LED connected from the LED pin to V_SS. During sleep mode and Ultra-Low-Power sleep mode, the LED pin sources periodic current pulses at 250Hz with 25% duty cycle. The current amplitudes in both cases can be programmed from 10mA to 20mA by the resistor connected from SL to V_SS according to the following formula.

$I_{\mathrm{LED}}=\frac{645.75}{R_{\overline{\text{SL}}}+1200}$

In AUTOCLASS mode, the PSE is allowed to determine the actual maximum power consumption from the connected PD. When AUTOCLASS mode is enabled, during the first class event, the PD drops its current to class signature ‘0’ no earlier than 76ms (min) and no later than 87ms (max). The AUTOCLASS feature is only enabled in MAX5995C.

In AUTOCLASS mode, connect a resistor (no worse than 1% accuracy) between AUC and V_SS to program the duty cycle of MPS current to further reduce the power consumption in MPS mode. There are four settings: floating (> 25%), 332kΩ (15%), 121kΩ (10%), and short to V_SS (5%)

The device will start a 82ms Timer On the first Classification Event. If the PSE does not provide the Long First Event, then the PD will not be in AUTOCLASS mode and will not modulate IMPS duty-cycle current according the AUC status. In this case, I_MPS duty-cycle is the default value (> 25% pulses, as shown in Figure 6). If the PSE provide the Long First Event, the PD will truncate the classification current after 82ms to signature AUTOCLASS mode to the PSE, and then the PD will modulate the I_MPS duty-cycle current according to AUC status. I_MPS modulation scheme is shown in Figure 6.