| Package Code | T822Y+3C |
| Outline Number | 21-100185 |
| Land Pattern Number | 90-100070 |
| Thermal Resistance, Multilayer Board: | |
| Junction-to-Ambient (θJA) | 85.3°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 8.9°C/W |
SW is side-wettable and EP is exposed pad.
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opMAX49017ATA%2FVY%2BT
data-opMAX49017ATA%2FVY%2B
Comparator A OutputInternal Reference Output. Internally connected to the inverting input of comparator A. Bypass REF pin with a 0.1µF capacitor to GND as close as possible to the device.Comparator A Noninverting InputGroundComparator B Noninverting InputComparator B Inverting Input. A 3.3nF capacitor is optional to be added at INB-.Comparator B OutputVDD Supply Voltage. Bypass VDD with a 0.1μF capacitor to GND as close as possible to the device pin.Exposed Pad. Connect EP to GND.