Package Information

Package Information
12 TQFN
Package Code T1244+4
Outline Number 21-0139
Land Pattern Number 90-0068
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA) 59.3°C/W
Junction to Case (θJC) 6°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 41°C/W
Junction to Case (θJC) 6°C/W

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

data-opMAX41470GTC%2B
data-opMAX41470GTC%2BT
GroundGround for Low-Noise AmplifierLow-Noise Amplifier InputPower-Down, Active-High. When the pin is controlled by external MCU, apply logic-high for shutdown mode or logic-low to enable the device. After a falling edge of PWRDN, the internal registers are reset to default values. When the pin is connected to GND, the device cannot enter the lowest current shutdown state. Proper start-up timing is for MCU to drive PWRDN high and wait for 1ms, then drive PWRDN low and wait for 0.2ms before writing to registers.Serial Interface Chip Select. Active low.Serial Interface Clock Input for Register ProgrammingSerial Interface Data Input/Output for Register Programming. When CSB is at logic-low.Data Output of Demodulated Received SignalFirst Crystal Input. Can be driven single-ended.Second Crystal InputRecovered Clock Output. If the clock output is disabled, connect to GND. If the clock output is enabled, tie the pin to GND through a 10kΩ resistor.Power-Supply Voltage. Connect a 0.01μF capacitor to ground.