Functional Diagram
Functional Diagrams
LNA
Low-Noise Amplifier Input
LNA
Low-Noise Amplifier Input
LO SYNTHESIZER
MIXER/
VGA
BPF
IF = 200kHz
OR 400kHz
DATA
Data Output of Demodulated Received Signal
PGA
FREQUENCY
DSP
GAIN CTRL
STATE MACHINE
SDIO
Serial Interface Data Input/Output for Register Programming. When CSB is at logic-low.
SCLK
Serial Interface Clock Input for Register Programming
XTAL
OSC
DEVICE
CONFIGURATION
PWRDN
Power-Down, Active-High. When the pin is controlled by external MCU, apply logic-high for shutdown mode or logic-low to enable the device. After a falling edge of PWRDN, the internal registers are reset to default values. When the pin is connected to GND, the device cannot enter the lowest current shutdown state. Proper start-up timing is for MCU to drive PWRDN high and wait for 1ms, then drive PWRDN low and wait for 0.2ms before writing to registers.
CSB
Serial Interface Chip Select. Active low.
POWER
CONTROL
DOUT
XTAL1
First Crystal Input. Can be driven single-ended.
XTAL2
Second Crystal Input
CLK
Recovered Clock Output. If the clock output is disabled, connect to GND. If the clock output is enabled, tie the pin to GND through a 10kΩ resistor.
ADC
