Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics

(Typical Application Circuit, typical values are at VDD = +3.0V, TA = +25°C, ASK at input frequency = 433.92MHz, Manchester encoded, IF = 400kHz, RXBW = 340kHz with 16MHz crystal oscillator, unless otherwise noted. (Note 1))
DC SPECIFICATIONS
Supply Voltage VDD 1.8 3.6 V
Supply Current IVDD_RCV 9 14 mA
Shutdown Current ISHDN 10 1000 nA
Standby Current ISDBY 320 μA
Sleep Current IDD_SLEEP 1 μA
AC SPECIFICATIONS
Frequency Range 287 to 320,
425 to 480,
860 to 960 		MHz
Maximum Receiver Input Level PRFIN_MAX Modulation depth > 20dB -20 0 dBm
Maximum Channel Bandwidth -3dB bandwidth at 400kHz IF 300 kHz
Minimum Polling Mode Duty Cycle 0.775 %
AC SPECIFICATIONS / SENSITIVITY / FSK
Sensitivity Limit FSK (Note 2) RXBW = 340kHz, 100kbps, FSK deviation = ±80kHz, fRF = 868MHz -100 dBm
RXBW = 340kHz, 62.5kbps, FSK deviation = ±40kHz -106
RXBW = 24kHz, 10kbps, FSK deviation = ±8kHz -116
RXBW = 12kHz, 2kbps, FSK deviation = ±2kHz -120
RXBW = 12kHz, 250bps, FSK deviation = ±2kHz -127
AC SPECIFICATIONS / SENSITIVITY / ASK
Sensitivity Limit ASK (Note 2) RXBW = 340kHz, 62.5kbps, fRF = 868MHz, modulation depth ≥ 20dB -103 dBm
RXBW = 120kHz, 5kbps -116
RXBW = 120kHz, 2kbps -118
RXBW = 24kHz, 1kbps -122
RXBW = 12kHz, 250bps -127
AC SPECIFICATIONS / Startup Time
Maximum Receiver Start-Up Time (Note 2) Self-polling mode (DATA high), ASK, 10kbps 450 μs
Slave receiver mode, from sleep state to receive ready (including crystal startup time), 10kbps 860
AC SPECIFICATIONS / PLL TURN-ON TIME
Minimum Synthesizer Frequency Step fXTAL/216 Hz
AC SPECIFICATIONS / IMAGE REJECTION
Image Rejection IR_UNCAL Uncalibrated 30 dB
IR_CAL Calibrated 33
AC SPECIFICATIONS / BLOCKERS
Minimum Blocking Level 3dB desense (Note 3) ±2MHz offset -58 dBm
±10MHz offset -40
Selectivity 3dB desense (Note 3) ±300kHz offset, IF = 200kHz 47 dBc
AC SPECIFICATIONS / MAXIMUM DATA RATE
Maximum data rate Manchester encoded 100 kbps
Nonreturn to zero (NRZ) 200
AC SPECIFICATIONS / RSSI
RSSI Resolution ±0.5 dB
RSSI Linear Dynamic Range 70 90 dB
AC SPECIFICATIONS / LNA
Input Impedance 50 Ω
CRYSTAL OSCILLATOR
Crystal Frequency fXTAL 12.8 16 19.2 MHz
Crystal Oscillator Startup Time tXO 380 μs
Crystal Load Capacitance CL 6 pF
CMOS INPUT/OUTPUT (SCLK, SDIO, CSB, PWRDN, DATA)
Input Low Voltage VIL 1.8V compatible 0.36 V
Input High Voltage VIH 1.8V compatible 1.44 V
Input Current IIL/IIH ±10 μA
Output Low Voltage VOL ISINK = 650μA 0.25 V
Output High Voltage VOH ISOURCE = 350μA VDD - 0.25 V
Maximum Load Capacitance at SDIO/DATA Pins CLOAD 10 pF
PWRDN Pin Glitch Suppression tGLITCH Glitches suppressed by PWRDN pin 1 ns
SERIAL INTERFACE / SPI (FIGURE 1)
SCLK Frequency fSCLK 1/tSCLK 20 MHz
SCLK to CSB Setup Time tCSS 10 ns
SCLK to CSB Hold Time tCSH 0 ns
SDIO to SCLK Hold Time tSDH Write 0 ns
SDIO to SCLK Setup Time tSDS Write 5 ns
Minimum SCLK to SDIO Data Delay tSDD_MIN Read, 10pF load from SDIO to ground 1.5 ns
Read, 100pF load from SDIO to ground 3.5
Maximum SCLK to SDIO Data Delay tSDD_MAX Read, 10pF load from SDIO to ground 8 ns
Read, 100pF load from SDIO to ground 11
Note 1: 100% tested at TA = +25°C. Limits over operating temperature and relevant supply voltage are guaranteed by design and characterization over temperature.
Note 2: All data rates are Manchester encoded, where 1kbps is equivalent to a 1kHz square wave representing a continuous string of "1" data bits. Average sensitivity at 433.92MHz, BER ≤ 0.2%.
Note 3: Power referred to LNA input. Manchester 10kbps data rate, unless otherwise noted.
Figure 1. SPI Serial Timing Interface Timing Diagram

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