Detailed Description

The MAX41470 sub-GHz ISM RF receiver requires very few external components to complete the receiver signal chain from RF to bits. Depending on the signal power, data rates as high as 100kbps Manchester (200kbps NRZ) can be achieved.

This part is designed to receive ASK/OOK or FSK/GFSK modulated data in the 287MHz to 320MHz (nominally 315MHz), 425MHz to 480MHz (nominally 434MHz), and 860MHz to 960MHz (nominally 868MHz or 915MHz) ISM frequency bands.

The architecture of the MAX41470 is a low intermediate frequency (low-IF) receiver with digital demodulation. The antenna received signal is amplified and downconverted to a 400kHz or 200kHz IF. The local oscillator (LO) signal for downconversion is generated from an internal fractional-N PLL synthesizer and an external 16MHz crystal.

The analog receiver bandwidth is 350kHz (when IF = 400kHz) or 175kHz (when IF = 200kHz), corresponding to the IF selection. Digital channel filtering with programmable bandwidth is applied before demodulation. When the data rate is low, a narrow bandwidth channel filter can be selected to achieve high receiver sensitivity. Post-demodulation filtering with a programmable bandwidth is implemented in the digital domain where that filtered output is compared against an adaptive decision threshold to generate a 1-bit oversampled output on the DATA pin.

Supported features of the MAX4147x receiver family include: automatic gain control (AGC), a received signal strength indicator (RSSI), automatic frequency control (AFC), and a frequency error indicator (FEI).

The MAX41470 has an SPI interface to program the internal registers for full control of the device. For I²C programmability or preset capability, refer to the MAX41473/MAX41474 data sheet. When in programming mode, the MAX41470 can support self-polling operation based on a Manchester-encoded preamble detection to provide an interrupt signal on the DATA pin.

The MAX41470 receivers have four power states: Shutdown, Sleep, Standby, and Receive Active. Set the PWRDN pin low to enable (power on) the device and set PWRDN high to disable the radio. When the device is enabled, the device operational states are controlled through the serial interface by the internal registers.

Typically, PWRDN is driven by a GPIO pin from an MCU and must be driven high or low. When PWRDN is connected to GND, the device cannot enter Shutdown state.

While in programming mode, the MAX41470 has two major operational states: slave-receiver and self-polling. While operating as a slave-receiver (SlaveRX), the MAX41470 is fully controlled by an external "master" MCU through the serial interface. In the self-polling operation (PollingRX), the MAX41470 periodically switches between standby and receiving states according to preprogrammed times, interrupts, and MCU control.

Figure 2 is a simplified state diagram of the MAX41470. When the PWRDN pin is set high, the device will enter the low-current Shutdown state. The PWRDN should be held high for at least 1ms before transitioning to low. When the PWRDN pin is driven low, the internal supply is turned on and the device enters the Sleep state with all the internal registers reset to default values. Programming through the serial interface is allowed after a typical turn-on time of 400μs to allow settling of the device. Programming while in the Sleep state is not recommended, except for writing a 1 to the EN_XO bit in order to change the device to the Standby state. It is recommended the user perform serial communications while in the Standby state. To enable SlaveRX operation from the Standby state, the user writes a 0 to the WUT_EN bit and a 1 to the SLAVE_RX_EN bit. All three register bits used to control the power state (EN_XO, WUT_EN, and SLAVE_EN) can be found in the STATE_CTRL1 (0x14) register.

While in the SlaveRX state, the user can read but not write values to the DIG_RX registers and, in general, the device configuration cannot be changed while the receiver is active (SlaveRX or PollingRX states). The SlaveRX state does support access to the STATE_CTRL1 (0x14) register, for example, when writing SLAVE_RX_EN = 0 to turn off the receiver and change the device state back to Standby.

Self-polling operation is enabled by writing a 1 to the WUT_EN bit while the device is in the Standby state. This allows the user to place the master MCU into a low-power mode, allowing the MAX41470 to automatically toggle between a low-current Wait state and the higher-current PollingRX state. The periodic toggling is controlled by the internal wake-up timer (WUT) signal, which is a pulse chain as illustrated in Figure 3.

The duration the receiver is in the PollingRX state (detection time or t_DET) is adjustable from 0.48ms to 20.88ms, in 0.08ms steps, by programming the TDET[7:0] field in the WUT1 (0x17) register. This detection time should be set to a value longer than the receiver turn-on time (Table 2) plus the preamble pattern duration. For guaranteed detection, refer to the details under the Preamble Detector section. The WUT period is defined as:

T_WUT = t_DET + t_WAIT = t_DET + N_RATIO x t_DET = (1 + N_RATIO) x t_DET

where T_WUT is the wake-up time period, t_DET is the programmed detection time, t_WAIT is the wait time, and N_RATIO is the programmed ratio of t_DET/t_WAIT, thus T_WUT is an integer multiple (≥2) of t_DET.

The ratio of t_WAIT to t_DET (N_RATIO) is adjustable from 1 to 128 in step size of 1 by programming the TSBY_TDET_RATIO[6:0] field in the WUT2 (0x18) register. Therefore, the WUT duty cycle is programmable from 1/2 to 1/129. The WUT response time (t_1WUT) is approximately the same as t_WAIT.

In self-polling mode, the DATA pin serves as an interrupt source for an MCU. Once a preamble bit pattern is received and validated in the PollingRX state, the PREAMB_DET bit in the interrupt status register ISR (0x13) will be set to 1, and a falling edge will be generated on the DATA pin to wake up an MCU at the completion of the polling cycle. After wakeup, the user must read the ISR (0x13) register to automatically clear the PREAMB_DET bit and WUT_EN bit in the STATE_CTRL1 (0x14) register. The MAX41470 will thus exit self-polling mode and assert the DATA output pin to logic 1. With the read to the ISR register, the resulting state is Standby and a write to the SLAVE_RX_EN bit is required to transition into the SlaveRX state.

The MAX41470 provides a preamble detector to be used with the self-polling operation. The preamble must be Manchester encoded as shown in Table 3. The pattern length, from 1 to 16 bits, is set in the PREAMB_LEN[3:0] register field where 0x0 = 1 bit in length and 0xF = 16 bits in length. The non-encoded or raw bit pattern is programmed into PREAMB_WORD[15:0] (addresses 0x0E and 0x0D) noting that PREAMB_WORD[0] is the LSB of the bit pattern and this is the most recent or last bit received from the RF bit stream. As bits are received and demodulated, they are effectively shifted in and compared to the PREAMB_WORD from the LSB to the MSB.

For guaranteed preamble detection within the first t_DET cycle, the t_DET width would allow margin for the case where the first bit of the preamble was not received when t_DET state was entered. The resulting equation would be:

PREAM_LEN + PREAM_LEN − 1 = 2 × PREAM_LEN − 1

Due to the t_DET time range of 0.48ms to 20.88ms, the number of bits that can fit into this range and comply with the guaranteed t_DET detection equation of 2 x PREAM_LEN - 1 dictates a limitation on the number of bits detectable given a defined bit rate. For example, if the Manchester data rate is 250bps and guarantee detection with PREAM_LEN = 16, this would equate to 2 x 16 - 1 = 31 bits required. To receive 31 bits at 250bps, it would take the following:

But the maximum t_DET allowed is 20.88ms. The table below states the limitations for the lower data rates if using the guaranteed timing. If the data rate is above those listed, there is no limitation.

For example, if PREAMB_LEN[3:0] is programmed to 0xA (decimal value 10), then the preamble bit pattern is specified by PREAMB_WORD[10:0], and the preamble is 22 bits after decoding the Manchester edges (or 11 raw bits before encoding). In this example, the five MSBs in the PREAMB_WORD field [15:11] are not used.

The preamble detector is triggered when the received bit stream matches the Manchester version of the PREAMB_WORD without regard to the phase of the pattern. For example, a non-Manchester preamble word of 0xFF = Manchester 0101 0101 0101 0101_b and a non-Manchester preamble word of 0x00 = Manchester 1010 1010 1010 1010_b would both trigger a matching RF bit stream of 0101... 0101_b.

The DATA pin toggles while in the SlaveRX state to output a digital binary representation of received data. The digital base band system has a minimum requirement to oversample the signal by 16x thus limiting the data rate of received signal to no more than 100kbps Manchester (200kbps NRZ).

In self-polling operation, the DATA pin serves as both an interrupt source and the data stream from the digital baseband system. The DATA pin is driven to logic 1 while in the PollingRX state. If no match is made to the preamble pattern, the device will move to the Wait state and the DATA pin will continue to be driven high. Once the preamble pattern is detected in the PollingRX state, a falling edge will be generated on the DATA pin right after the device switches to the Wait state and DATA will be held at logic 0. After the ISR register has been read, the DATA pin will be driven back to logic 1 and the device will be placed into the Standby state (as the WUT_EN bit is cleared automatically).

To begin streaming data from the DATA pin, the receiver needs to be moved from Standby to the SlaveRX state by writing a 1 to the SLAVE_RX_EN bit in the STATE_CTRL (0x14) register. This operation can be performed right after reading the ISR register.

If the ISR register is not read (cleared) within the initial t_WAIT time, the receiver will automatically re-enter the PollingRX state and set the DATA pin back to logic 1. Since the ISR was not cleared during the previous cycle, the preamble detect is still triggered and once the t_DET time expires, the receiver will again indicate an interrupt by driving the DATA pin to 0 after it re-enters the Wait state. This cycle will continue until the ISR register is cleared.

The IF can be selected between two values by programming the IF_SEL bit in the IF_CHF_SEL (0x02) register.

The digital channel filter (CHF) can be selected by programming the CHF_SEL[2:0] field in the IF_CHF_SEL (0x02) register. Aggregate receiver bandwidth also depends on the IF selection. See Table 6 for digital channel filter settings.

The modulation mode is selected by programming the ASK_FSK_SEL bit in the IF_CHF_SEL (0x0) register. Write a 0 to the ASK_FSK_SEL bit for ASK modulation, or a 1 to the ASK_FSK_SEL bit for FSK modulation.

The ASK/FSK demodulator configuration depends on the DEMOD_TCTRL[2:0] and DEMOD_FSK[2:0] fields in the DEMOD (0x00) register. DEMOD_TCTRL should be programmed according to the formulas in Table 7:

The DEMOD_FSK field is used only in FSK mode. There are a total of 28 options for configuring the FSK demodulator, as seen in the following tables:

* Default setting

The MAX41470 provides a dual-step feedback AGC, as illustrated in Figure 4. AGC attack, or high-to-low gain switching, happens when the raw RSSI value is higher than a threshold. AGC release, or low-to-high gain switching, happens when the raw RSSI value is lower than a second threshold. The difference between the attack and release thresholds should be large enough to provide hysteresis.

The AGC operation mode is controlled by the AGC_EN_BO[1:0] field in the AGC (0x01) register.

*Default setting

The release threshold of AGC can be fine-tuned by programming the AGC_THREL[3:0] field.

PD_SLOPE = 1.67 x 2^N (μs/div)

where N = max(IF_SEL + CHF_SEL + DEMOD_TCTRL + RSSI_DT - 1, 0).

Because the RSSI scale is 0.5dB/div, the time constant of 3dB discharge is (10 x 2^N) μs.

A feedback control loop is used to adjust the PLL synthesizer frequency within a programmable range. The center of the AFC range is programmed by 24-bit frequency word LO_CTR_FREQ[23:0], which can be calculated from the following equation with the default LO injection setting when MIX_HS_LSBAR = 0:

$\mathrm{LO\_CTR\_FREQ}=\mathrm{INT}\left(65536\frac{\left(f_{\mathrm{RF}}-f_{\mathrm{IF}}\right)}{f_{\mathrm{XTAL}}}\right)$

where f_RF is the target RF frequency, f_IF is the 200kHz or 400kHz setting programmed with the IF_SEL bit, and f_XTAL is the crystal frequency (typically 16MHz).

When MIX_HS_LSBAR = 1, the equation for LO_CTR_FREQ[23:0] is:

$\mathrm{LO\_CTR\_FREQ}=\mathrm{INT}\left(65536\frac{\left(f_{\mathrm{RF}}+f_{\mathrm{IF}}\right)}{f_{\mathrm{XTAL}}}\right)$

where f_RF is the target RF frequency, f_IF is the 200kHz or 400kHz setting programmed with the IF_SEL bit, and f_XTAL is the crystal frequency (typically 16MHz).

The AFC loop generates a frequency offset from the programmed LO center frequency. The maximum frequency offset is limited by the receiver bandwidth and the AFC_MO[2:0] field setting in the AFC_CFG1 (0x07) register. This maximum offset can be expressed as:

$f_{\mathrm{OFFSET}-\mathrm{MAX}}=\mathrm{AFC\_MO}\times \frac{f_{\mathrm{XTAL}}}{2^{\left(\mathrm{IF\_SEL}+\mathrm{CHF\_SEL}+10\right)}}$

where AFC_MO, IF_SEL, and CHF_SEL are programmed register values. When AFC_MO = 0, the PLL synthesizer frequency is fixed and AFC is disabled.

Without AFC, the frequency mismatch between an RF transmitter (Tx) and this receiver (Rx) can be estimated from the crystal accuracy ratings and the operating frequency band. For example, assume the crystal accuracy is ±50ppm for both the Tx and Rx systems and the operating frequency is 434MHz, then the Tx/Rx frequency mismatch can be as high as ±100ppm of the operating frequency, or ±43kHz.

In ASK mode, AFC is not necessary when the receiver bandwidth is sufficiently wide, but AFC is required when a narrow channel filter is selected to achieve a high receiver sensitivity. In FSK mode, AFC is required when the Tx/Rx frequency mismatch is higher than 25% of the frequency deviation.

When a wide channel-filter option is selected (for example CHF_SEL = 0), AFC_MO can be programmed based on an estimate of the Tx/Rx frequency mismatch. For example, when using the 315MHz band, a 16MHz crystal, the wide channel filter (CHF_SEL = 0), and  200kHz IF (IF_SEL = 1), the user can program for a maximum AFC offset of 31.3kHz (AFC_MO = 4). This would be sufficient to allow for a ±100ppm Tx/Rx frequency mismatch in the 315MHz band.

The AFC_LG[1:0] field in AFC_CFG1 (0x07) register controls the AFC loop gain and settling time. This should typically be set to AFC_LG = 3 in ASK mode and AFC_LG = 2 in FSK mode.

In programmable mode, the user can read the FEI (0x11) register to determine the frequency error. This value is an 8-bit, signed integer, in two's complement format. The frequency offset generated by AFC can be calculated as:

$f_{\mathrm{OFFSET}}=\mathrm{FEI}\times \frac{f_{\mathrm{XTAL}}}{2^{\left(\mathrm{IF\_SEL}+\mathrm{CHF\_SEL}+14\right)}}$

where FEI, IF_SEL, and CHF_SEL are register values and f_XTAL is the crystal frequency (typically 16MHz)

Because the maximum offset is limited by the AFC_MO register field, the absolute value of FEI output is no more than 16 x AFC_MO. For the purpose of frequency tracking, the user can iteratively adjust the LO_CTR_FREQ register value based on an FEI reading.

The operation of AFC relies on an internal frequency detector, which senses errors in the RF frequency and averages the value over a number of received bits.

The changes in frequency inherent in FSK modulation introduces a bit-pattern-dependent, self-noise effect. Therefore, in FSK mode, it is recommended the AFC only be used when employing Manchester encoding and not with NRZ. In a typical data packet, the preamble is Manchester encoded but the payload may not be. With the MAX41470, a form of Manchester encoding must be used for proper preamble detection in the PollingRX mode.

Since the preamble is often an alternating 1 and 0 (or MARK and SPACE), setting PAD_FREEZE_AFC = 1 and AFC_LG = 3 will result in a fast settling of the AFC in roughly 5 bits of RF data.

The AFC starts automatically when the receiver is active (entering the SlaveRX or PollingRX state). While using FSK modulation and in the SlaveRX state, the AFC can be 'frozen' just after a valid preamble pattern is detected. This feature is enabled by setting the PAD_FREEZE_AFC bit to 1 in the AFC_CFG2 (0x08) register. See the Preamble Detector section for how to program the preamble bit pattern. The PAD_FREEZE_AFC bit is not available when using ASK modulation (ASK_FSK_SEL = 0).

The post-demodulation filter (PDF) is a digital filter with programmable bandwidth. The PDF bandwidth selection is closely related to the data rate of the received signal. For example, the bandwidth needed for Manchester encoding is twice that needed for the same bit rate when sending NRZ data. (See Table 3 for more information.)

For a given configuration of IF_SEL, CHF_SEL[2:0], SRC_SM[2:0], and SRC_LG[2:0] fields, the recommended decoded bit rate R_b for Manchester is defined as:

where integer values of registers are used in the expression.

Given the difference in NRZ format vs. Manchester data, the recommended decoded bit rate R_b for NRZ would be adjusted to:

where integer values of registers are used in the expression.

For additional guidance on setting the SRC_SM and SRC_LG values based on the desired configuration, see the ASK Receiver Configurations and FSK Receiver Configurations sections. The SRC_SM[2:0] and SRC_LG[2:0] fields are located in the PDF_CFG (0x03) register.

The PDF bandwidth is provided in Table 12:

* Default setting

Regardless of the LD_BW setting, the actual transmission data rate should not exceed 1.03 x R_b and should not be any lower than 0.6 x R_b in any configuration.

The digital signal out of the post-demodulation filter is compared with a threshold to make a binary decision, which is subsequently represented as a 0 or 1 on the DATA output pin. When using FSK modulation, the decision threshold is fixed at zero, where a positive value signal represents the MARK frequency and a negative value represents the SPACE frequency. With ASK modulation, the comparison threshold will automatically be adjusted to accommodate changes in signal strength based on user settings.

The MAX41470 provides two ASK threshold adjustment methods set by the user with the ATH_TYPE bit in the ATH_CFG3 (0x06) register. The precharged lowpass filter (preLPF) method is strongly recommended when using Manchester encoding. In the case where Manchester encoding is not used (e.g., in NRZ format, which can result in long consecutive strings of 0s or 1s), the adaptive peak detector (aPD) method should be selected.

The ATH_BW bit in ATH_CFG3 (0x06) register is used only with the preLPF method to control the filter bandwidth. Program ATH_BW to 0 when the Manchester data rate is close to the recommended rate R_b (suggested close values are 1.03R_b < data rate < 0.75R_b; see the Recommended Data Rate and Post Demodulation Filter section for the definition of R_b). Use ATH_BW = 1 if the transmitter data rate is expected to go as low as 0.6R_b.

The ATH_DT[1:0] field in the ATH_CFG2 (0x05) register is used only with the aPD method to adjust the peak detector's discharge time. If using Manchester encoding, set ATH_DT to 0 whenever the data rate is close to the recommended R_b value. Set ATH_DT to 1 if the transmitter's Manchester data rate is expected to go as low as 0.6R_b. In the case of NRZ encoding, set ATH_DT to 3.

The ATH_TC[4:0] field in the ATH_CFG2 (0x05) register is also used only with the aPD method to control the peak detector time constant. Set ATH_TC according to the SRC_LG value using Table 13:

The ATH_GC[4:0] field in the ATH_CFG3 (0x06) register should be set based on the values in the IF_SEL and CHF_SEL fields according to Table 14:

In both methods of decision threshold generation (preLPF and aPD), the lower bound of the decision threshold is set by the ATH_LB[7:0] field in the ATH_CFG1 (0x04) register. ATH_LB has a range of valid values from -128 to 0 and is represented in two's complement format (e.g., 0x9C = -100_dec).

To achieve the highest ASK receiver sensitivity combined with fast receiver settling within 2 bits, the optimum ATH_LB value can be found by calibrating the PDF through a collection of output noise statistics. For this calibration process, the LNA input pin must be terminated with 50Ω to ground while the user acquires random samples of the PDF by reading the PDF_OUT(0x12) register when the receiver is in the SlaveRX state. Without the termination, the standard deviation of the PDF_OUT values is much larger than actual. The calculated values below should be used if not terminated properly. The value of ATH_LB should be set using the following formula:

where σ is the standard deviation of PDF_OUT and μ = MEAN(PDF_OUT - 16) when AGC_EN_BO[0] = 0, or  μ = MEAN(PDF_OUT) when AGC_EN_BO[0] = 1.

Here, AGC_EN_BO[0] is the LSB of the 2-bit field in the AGC (0x01) register.

In the absence of a calibration value, ATH_LB should be set by calculating a recommended value based on the following formula and tables:

where MU1 and MU2 are found using Table 15 and Table 16.

Find a value for MU1 based on the receiver filter settings.

Calculate the SRC_Ratio using the following formula:

where SRC_LG and SRC_SM are fields in the PDF_CFG (0x03) register.

When the SRC_RATIO is not an integer (SRC_SM is non-zero), a linear interpolation should be used to determine the best value for MU2 from the lookup table. The final MU2 value must be rounded to the nearest integer. For example, if SRC_SM = 2 and SRC_LG = 4, the  SRC_Ratio is calculated to be 4.3. Using a linear interpolation between SRC_RATIO and MU2, the raw value for MU2 would be 7.4, rounded to a final value of MU2 = 7.

When preLPF is selected (ATH_TYPE = 0), the ATH_LB value may be lower than MU1 + MU2 - 6. As an example, set the ATH_LB field to a value of -127 (0x81 in two's complement) regardless of the IF_SEL and CHF_SEL settings. In this case, each device can deliver its highest sensitivity without calibration, but the receiver settling slows down when the signal power is close to the receiver sensitivity. Because some applications require fast receiver settling, the use case of ATH_LB = -127 is not always recommended, although it is convenient, as a trade-off between sensitivity and settling time.

Receiver sensitivity is measured and specified as the average LNA input power at a 2x10^-3 bit-error rate (0.2% BER) when testing with Manchester-encoded data which is equivalent to 1x10^-3 bit-error rate (0.1% BER) for NRZ data. For ASK modulation, average power is approximately 3dB lower than peak power.

There are many ways to optimize the sensitivity of the device, such as reducing the channel filter bandwidth, using lower data rates, ensuring that the carrier frequency is not a multiple of the crystal frequency, or even using a high-side LO injection configuration to avoid noise or spurs in the environment.

The configuration tables, Table 17, Table 18, Table 19, and Table 20, identify possible configurations where the highest or best sensitivity is identified in the top rows of each table. Table 19 and Table 20 provide guidance to those systems targeting a 0.8 modulation index.

The MAX41470 utilizes a 3-wire SPI protocol for programming its receiver registers. The digital I/Os in Table 23 control the operation of the SPI.

Figure 5 shows the general SPI Write transaction. Figure 6 shows the 3-wire SPI Read transaction. In a read transaction, the dummy byte is required to switch the SDIO line from input mode to output mode.

The serial interface also allows a burst write or read. Figure 7 shows the data for the sequential addresses occupying the bytes following first data byte.

The XTAL oscillator in the MAX41470 is designed to present a capacitance of approximately 12pF from the XTAL1 and XTAL2 pins to ground. In most cases, this corresponds to a 6pF load capacitance (C_L) applied to the external crystal when typical PCB parasitics are included. It is very important to use a crystal with a C_L equal to the capacitance of the MAX41470 crystal oscillator plus PCB parasitics. If a crystal designed to oscillate with a different C_L is used, the crystal is pulled away from its specified oscillation frequency, introducing an error in the reference. The crystal’s natural frequency is typically below its specified frequency. However, when loaded with the C_L, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the C_L. Accounting for typical board parasitics, a 16MHz crystal with 6pF specified C_L is recommended. Please note that adding discrete capacitance on the crystal also increases the startup time, and adding too much capacitance could prevent oscillation altogether.

Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by:

where: f_P is the amount the crystal frequency pulled in ppm, C_M is the motional capacitance of the crystal (often referred to as C₁), C_CASE is the case capacitance, C_L is the specified load capacitance, C_ACTUAL is the actual load capacitance. When the crystal is loaded as specified (i.e., C_ACTUAL = C_L), the frequency pulling equals zero. For additional details on crystal pulling and load capacitance affects, refer to Maxim Tutorial 5422 – Crystal Calculations for ISM RF Products.

The available crystal frequencies are 12.8MHz, 16.0MHz (default), and 19.2MHz. An internal clock of 3.2MHz ± 0.05MHz frequency is required. To maintain the internal 3.2MHz time base, the XOCLKDIV[1:0] register field in the AFE_CTL1 (0x19) register byte must be programmed based on the crystal frequency, as shown in Table 24.

* Default value

The MAX41470 utilizes a fully integrated fractional-N PLL as its frequency synthesizer. All PLL components, including the loop filter, are on-chip. The internal local oscillator (LO) frequency can be tuned in increments of f_XTAL/65536 (~244Hz with a 16MHz crystal) from 286MHz to 320MHz, 425MHz to 480MHz, and 860MHz to 960MHz.

The desired frequency can be configured by programming the LO_CTR_FREQ[23:0] (address 0x09, 0x0A, and 0x0B). To calculate the LO_CTR_FREQ bits assuming default low-side LO injection, use the following equation:

$\mathrm{LO\_CTR\_FREQ}[23:0]=\mathrm{ROUND}\left(\frac{65536(f_{\mathrm{RF}}-f_{\mathrm{IF}})}{f_{\mathrm{XTAL}}}\right)$

where f_IF = 400kHz (IF_SEL = 0) or f_IF = 200kHz (IF_SEL = 1), f_XTAL is the crystal frequency (typically 16.0MHz), and f_RF is the carrier frequency of the RF input. For FSK modulation, f_RF is defined as the middle point between the MARK and SPACE frequencies.

For optimum sensitivity, avoid carrier frequencies (f_RF) values that are multiples of the crystal frequency (f_XTAL).

See Table 25 to program the LODIV[1:0] register field in the AFE_CTL1 (0x19) register byte when choosing a LO frequency. Always set bit FRACMODE = 1 in the AFE_CTL1 byte to select fractional-N PLL mode.

In programmable mode and when SRC_LG and SRC_SM are not both equal to zero, a clock output is available on pin 11, which is recovered from the demodulated data stream. This clock assists with sampling of the DATA pin output by providing a rising edge for the user to latch the DATA signal. Optionally, the output data on the DATA pin can be re-timed internally, which reduces the pulse-width variation of the demodulated bits and thus opens the data eye. The operational mode of the clock data recovery (CDR) function is configured through the CDR_MODE[1:0] register bits in the CDR_CFG1 register (0x35). The use of these bits is shown in the following table:

* Default programming mode

In the default case, the CDR function is disabled. When CDR_MODE = 1, the recovered clock becomes available on the CLK pin while the DATA output remains unchanged (not re-timed). When CDR_MODE = 2, there is no clock available on the pin, but it is used internally to re-time the DATA output. When CDR_MODE = 3, the recovered clock output is available on the CLK pin and the DATA output is re-timed.

The recovered clock is twice the frequency of the data rate of the received data. For example, a 2kbps received data stream results in a 4kHz recovered clock where the rising edge of each clock is centered on each DATA output bit.

The mixer is a double-balanced architecture that performs a downconversion of the RF signal to the 400kHz or 200kHz intermediate frequency. The mixer output drives an IF filter and, depending on the value of the MIX_HS_LSBAR bit in the AFE_CTL1 (0x19) register, the LO frequency can be either lower (low-side injection) or higher (high-side injection) than the RF signal.

In normal receiver operation, it is recommended to use low-side injection, thus placing the target RF signal frequency higher than the LO frequency by programming the MIX_HS_LSBAR bit to 0 (default value). The MIX_HS_LSBAR bit can be set to 1 during image rejection (IR) calibration.

Some applications require a low latency or short demodulation time delay of the receiver. For those applications, the LD_BW and LD_BUF bits in the PDF_CFG (0x03) register can be programmed to non-default settings.

The case of LF_BW = 0 and LD_BUF = 1 is reserved. One of the Table 27 combinations above should be configured.

The setting of LD_BW = 1 increases the bandwidth of the receiver and hence reduces the group delay of the PDF at a cost of 0.5dB sensitivity degradation. Also see Table 12.

A lowest-delay buffer is selected when LD_BUF = 1, but this setting is invalid when SRC_LG is set to 1 or 0. Lowest-delay buffer is also invalid when SRC_LG = 2 and SRC_SM is odd.

For example, the data rate is 1.4kbps after Manchester encoding, and the device is configured to IF_SEL = 1, CHF_SEL = 0, SRC_LG = 5, and SRC_SM = 1. The receiver latency from LNA input to DATA output can be reduced from 380μs (default settings) to 200μs (lowest delay settings) by setting LD_BD and LD_BUF to 1.

To use a non-return-to-zero (NRZ) data stream with ASK modulation, program ATH_TYPE = 1, ATH_DT = 3, and ATH_TC as noted in Table 13. The length of consecutive 1's (ON) or 0's (OFF) should not exceed 16 bits.

With FSK modulation, the setting of AFC_LG = 0 may be used to support NRZ modulation while avoiding any more than 10 consecutive MARK or SPACE bits. AFC settling requires roughly 100 symbols when AFC_LG = 0, thus this setting is recommended only for cases requiring long data streams at relatively high data rates (e.g., ≥100kbps NRZ).

When using FSK modulation and NRZ encoding in the payload, see the recommended AFC Freeze upon Preamble Detection section.

For applications where image rejection is important, the user can calibrate the MAX41470 for improved image rejection. The following procedure can be executed in the user's factory. Throughout the process, the device will be switched between Standby for programming of the IR_ADJUST register in 0x1A and SlaveRX for the active state when the RSSI value is read. The idea of the calibration is to find the minimum point of the RSSI value while sweeping the phase. Based on the increase or decrease of the RSSI values indicates whether the sweep will increase from 0x00 or increase from 0x11. To calibrate the image rejection, use the following procedure:

1. Program the MAX41470 for the desired frequency.
2. Apply an RF tone at the LNA input at the desired frequency and record the RSSI value.
3. Disable the SLAVE_RX_EN bit in register 0x14.
4. Program the MIX_HS_LSBAR bit (register 0x19, bit 3) to the opposite polarity.
   1. This effectively turns the desired frequency into the image frequency.
5. Set the SLAVE_RX_EN bit to enable SlaveRX mode and record the RSSI value.
6. Reset the SLAVE_RX_EN bit to disable SlaveRX mode and program register 0x1A to 0x01.
7. Set the SLAVE_RX_EN bit to enable SlaveRX mode and record the RSSI value.
8. Based on the RSSI values:
   1. If RSSI decreased, image rejection improved. Continue increasing 0x1A from the value of 0x01.
   2. If RSSI increased, image rejection degraded. Continue increasing 0x1A from the value of 0x11.
9. Set the SLAVE_RX_EN bit to enable SlaveRX mode and record the RSSI value
   1. Note:  If the RSSI value was higher at 0x01 and 0x11 than 0x00, then the best calibration code is 0x00 - procedure complete.
10. Reset the SLAVE_RX_EN bit to disable SlaveRX mode and increase register 0x1A by 1.
11. Set the SLAVE_RX_EN bit to enable SlaveRX mode and record the RSSI value.
12. If the RSSI went down, continue to increase the register value one code at a time, repeating steps 10 and 11 until there is an increase in the RSSI.
13. When there is an increase in RSSI, subtract 1 from register 0x1A as the final code - procedure complete.

The final code for register 0x1A must be saved in the MCU. It must be programmed each time the MAX41470 enters Standby state.