Applications Information

The suggested procedure for operating the device is outlined below.

1)  Power on the device with the PWRDN pin controlled by an external MCU. Drive PWRDN to logic-high and wait for at least 1ms, then drive PWRDN to logic-low and wait for at least 0.4ms.

2)  Write 0x04 to the STATE_CTRL1 (0x14) register. This will turn on the crystal oscillator and place the device into Standby.

3)  Select a quick start configuration of the DIG_RX register bank from Table 28, and write the 16 defined registers from address 0x00-0x0E and 0x19. The configurations provided within the Quick Start Configurations table and other examples assume a crystal frequency of 16MHz and the use of a Manchester-encoded RF signal unless otherwise noted.

4)  Setup a modulated RF signal source at the data rate matching the selected Quick Start Configuration.

5)  Write 0x05 to the STATE_CTRL1 (0x14) register. This will turn on the receiver and place the device into the SlaveRX state.

6)  Turn on the modulated RF signal and observe the DATA pin output.

7)  Write 0x00 to the STATE_CTRL1 (0x14) register. This will turn off the receiver and place the device into Sleep.

For this setup, the input signal should be Manchester encoded at a data rate close to the recommended bit rate (R_b). Keep ATH_TYPE = 0 (default value) to select the precharged lowpass filter (preLPF) method for ASK decision threshold generation.

For simplicity, program ATH_LB = -127 regardless of the selection of IF_SEL and CHF_SEL. The ASK decision threshold is generated from lowpass filter averaging. The ASK receiver settling time can be as long as 12 bits when the expected signal power is same as receiver sensitivity.

For example, assume an ASK signal at 5kbps centered at 433.92MHz where the 170kHz receiver bandwidth option is selected (IF_SEL = 1, CHF_SEL = 0). The programming to match this configuration would result in the DIG_RX register bank (15 consecutive bytes from address 0x00) as decimal [69, 38, 8, 26, 129, 13, 10, 31, 0, 27, 27, 133, 15, 0, 0] or hexidecimal [0x45, 0x26, 0x08, 0x1A, 0x81, 0x0D, 0x0A, 0x1F, 0x00, 0x1B, 0x1B, 0x85, 0x0F, 0x00, 0x00]. In addition, write decimal value 149 or hexidecimal 0x95 to AFE_CTL1 (0x19). Here, the decimal value of LO_CTR_FREQ is 1776517, calculated from f_XTAL = 16MHz, f_RF = 433.92MHz, and f_IF = 200kHz. In addition, in the ATH_LB (0x04) byte, the unsigned 8-bit value of 129 represents a signed 8-bit value of -127 as noted above. For this configuration, the receiver sensitivity might be approximately -115dBm.

If the receiver settling time is a concern, then the ATH_LB can be modified to accommodate a faster time. According to Table 15 and Table 16, the MU1+MU2 value is -80. In order to get nearly optimum sensitivity as well as fast receiver settling, ATH_LB can be programmed to MU1+MU2 - 6, or a value of -86 in this example (equivalent to a decimal value of 170 or hexadecimal value of 0xAA).

The AFC can only support a limited adjustment of the LO frequency away from the center frequency given by $\mathrm{LO\_CTR\_FREQ}\times \frac{f_{\mathrm{XTAL}}}{2^{16}}$. The maximum range of adjustment, referred to as an AFC pull-in range, is $\frac{\pm \mathrm{AFC\_MO}\hspace{0.17em}\times \hspace{0.17em}{f}_{\mathrm{XTAL}}}{2^{(\mathrm{IF\_SEL}+\mathrm{CHF\_SEL}+10)}}=\frac{\pm 7\hspace{0.17em}\times \hspace{0.17em}{f}_{\mathrm{XTAL}}}{2^{(\mathrm{IF\_SEL}+\mathrm{CHF\_SEL}+10)}}$. The actual range of adjustment is programmable from 0 to the pull-in range by setting AFC_MO between 0 and 7. In this section, all examples assume f_XTAL = 16MHz.

The initial value of Tx/Rx frequency mismatch can exceed the AFC pull-in range for a narrow-bandwidth configuration. For example, a 100ppm mismatch at 434MHz is ±43.4kHz, which exceeds the AFC pull-in range when (IF_SEL + CHF_SEL) ≥ 2. To address the limited pull-in range issue, we can employ software-aided frequency acquisition.

The LO_CTR_FREQ can be adjusted to correct for the mismatch. This can be done by modifying the frequency until a data packet is successfully recognized. However, the FEI can also be utilized to determine the magnitude and direction of offset. To program different center frequencies, the device must be taken out of active SlaveRX mode by programming the SLAVE_RX_EN to zero prior to reconfiguration of the LO_CTR_FREQ register. Then the device can be programmed to enter the SlaveRX state again.

In this setup, the expected signal is ASK at a 433.92MHz nominal frequency at 5kbps and the 60kHz bandwidth option (IF_SEL = 1 and CHF_SEL = 1).

Observation 1: Program the DIG_RX register bank (15 consecutive bytes from address 0x00) as decimal [68, 38, 9, 18, 162, 16, 7, 31, 0, 27, 27, 133, 15, 0, 0] or hexadecimal [0x44, 0x26, 0x09, 0x12, 0xA2, 0x10, 0x07, 0x1F, 0x00, 0x1B, 0x1B, 0x85, 0x0F, 0x00, 0x00]. In addition, write decimal value 149 or hexadecimal 0x95 to AFE_CTL1 (0x19). Here, the decimal value of LO_CTR_FREQ is 1776517, calculated from f_XTAL = 16MHz, f_RF = 433.92MHz, and f_IF=200kHz. When initial Tx/Rx frequency mismatch is less than the AFC pull-in range of ±27kHz, a typical receiver sensitivity of -116dBm can be achieved.

Observation 2: This has the same receiver configuration as Observation 1, but the initial Tx/Rx mismatch increases to ±43.4kHz. In this case, the receiver sensitivity degrades to -112dBm, and the frequency error indicator (FEI) reading saturates at ±112 (decimal value).

Observation 3: Adjust the LO_CTR_FREQ to account for the offset; otherwise, it has the same receiver configuration as Observation 1. Run the receiver with the three bytes of LO_CTR_FREQ programmed to decimal [27, 27, 43] and [27, 27, 223] or hexadecimal [0x1B, 0x1B, 0x2B] and [0x1B, 0x1B, 0xDF]. The typical -116dBm sensitivity can be achieved in at least one case of the receiver running, even if the initial Tx/Rx mismatch is as high as ±43.4kHz.

In this example, the signal is FSK at a 868.3MHz nominal frequency at 10kbps and the 24kHz bandwidth option (IF_SEL = 0 and CHF_SEL = 3). The FSK deviation is at ±8kHz.

Assume that the Tx/Rx frequency mismatch is unknown, but could be as high as ±86.8kHz. In this case, test the receiver running at seven equally spaced frequency points with 24.8kHz spacing. For this setup, the seven LO_CTR_FREQ values would be decimal [3555223, 3555122, 3555020, 3554918, 3554817, 3554715, 3554614].

Assuming the starting point of LO_CTR_FREQ = 3554918, the DIG_RX register bank is programmed as decimal  [97, 38, 19, 2, 0, 0, 0, 30, 0, 54, 62, 102, 15, 0, 0] or hexadecimal [0x61, 0x26, 0x13, 0x02, 0x00, 0x00, 0x1E, 0x00, 0x36, 0x3E, 0x66, 0x0F, 0x00, 0x00]. In addition, write decimal value 147 or hexadecimal 0x93 to AFE_CTL1 (0x19). To change LO_CTR_FREQ, exit the SlaveRX state into Standby, write three consecutive addresses from address 0x09, and re-enter the SlaveRX state.

The MCU should be able to recognize a data packet on the DATA pin at one of the seven frequency points. A typical receiver sensitivity of -115dBm should be seen.

For this setup, the ASK signal at 433.92MHz nominal frequency is at 1kbps and configured with the 170kHz bandwidth option (IF_SEL = 1, CHF_SEL = 0). Program the DIG_RX register bank (15 consecutive bytes from address 0x00) as decimal [71, 38, 8, 44, 165, 7, 10, 31, 0, 27, 27, 133, 15, 0, 0] or hexadecimal [0x47, 0x26, 0x08, 0x2C, 0xA5, 0x07, 0x0A, 0x1F, 0x00, 0x1B, 0x1B, 0x85, 0x0F, 0x00, 0x00]. In addition, write decimal value 149 or hexadecimal 0x95 to AFE_CTL1 (0x19). When initial Tx/Rx frequency mismatch is less than ±43.4kHz, typical receiver sensitivity of -118dBm can be achieved. In this example, the frequency mismatch can be determined to ±3kHz accuracy by reading the FEI (0x11) byte.

The next step is to correct the frequency mismatch by reprogramming LO_CTR_FREQ. Increase (or decrease) LO_CTR_FREQ if the FEI reading is positive (or negative). For example, if the FEI reading is -93, then decrease the LO_CTR_FREQ value by 186 counts in this example. In addition, a narrow bandwidth option such as IF_SEL = 1 and CHF_SEL = 3 can be selected to improve sensitivity to approximately -122dBm.

Once frequency acquisition is achieved, the MCU can read FEI and reprogram LO_CTR_FREQ to track the drift of Tx/Rx frequency mismatch. Such frequency tracking is useful when a narrow bandwidth option is selected.

The frequency offset generated by AFC is expressed as:

$\mathrm{FEI}\times \frac{f_{\mathrm{XTAL}}}{2^{(\mathrm{IF\_SEL}+\mathrm{CHF\_SEL}+14)}}$

where FEI is an integer in the range of [-112, 112]. The MCU can read FEI right after a data packet is recognized in the SlaveRX state, but cannot modify LO_CTR_FREQ unless SLAVE_RX_EN is cleared to move the device state to Standby. Because the resolution of the LO synthesizer is $f_{\mathrm{XTAL}}/2^{16}$, the MCU can make an incremental change of $\mathrm{FEI}\times \frac{4}{2^{(\mathrm{IF\_SEL}+\mathrm{CHF\_SEL})}}$ on the LO_CTR_FREQ counts.

In this example, a 1% polling setup is defined. The configuration is set up for ASK at 433.92MHz at a 2kbps data rate, 200kHz IF, and 170kHz CHF. The preamble length (PREAM_LEN[3:0] in the PREAMBLE_CFG1 register at 0x0C) is set to 15 for a final preamble length of 16 bits.

To accommodate the targeted 1% polling cycle, the TSBY_TDET_RATIO[6:0] bits should be set to 0x62 for a value of 98, resulting in a duty cycle of 1/(2 + TSBY_TDET_RATIO) = 1/100 or 1%. For proper detection of the 16-bit preamble, the guaranteed length targeted is calculated as:

To meet this requirement, the WUT1 (0x17) register bits TDET[7:0] should be set to exceed this duration. Therefore, with WUT1 at 0xBC or 188, the resulting wait duration is:

This duration exceeds the 15.5ms requirement. To match a Manchester 0x0000 (alternating 1's and 0's), the PREAMBLE_WORD1 and PREAMBLE_WORD2 is each set to 0x00. For this configuration, write the 15 consecutive bytes from address 0x00 as decimal [70, 38, 8, 36, 167, 9, 10, 31, 0, 27, 27, 133, 15, 0, 0] or hexadecimal [0x46, 0x26, 0x08, 0x24, 0xA7, 0x09, 0x0A, 0x1F, 0x00, 0x1B, 0x1B, 0x85, 0x0F, 0x00, 0x00]. In addition, write decimal values of [188, 98, 149] or hexadecimal [0x23, 0x62, 0x95] to registers 0x17, 0x18, and 0x19, respectively.

This full configuration results in a PollingRX time of 15.52ms and a wait time of 1.552s.