Preset Mode
To ensure the MAX41461/MAX41462 device enters shutdown state after power-on, the DATA pin must be held low at power-on. If the DATA pin cannot be guaranteed low at power-on, then a high-value pulldown resistor is recommended. After VDD has settled, a logic-low-high-low transition on DATA must occur in the preset mode. If the pulse duration of low-high-low transition is longer than tXO + tPLL, it is a valid wake-up pulse before data transmission. It is also allowed to have a short pulse duration between 5μs and 20μs. The short pulse will not wake up the device.
Programming Mode
After turning on power supply in I2C mode, a logic-high-low-high transition on SDA must occur to minimize leakage current in shutdown state. It is highly recommended that the I2C resistors are connected to the MAX41461/MAX41462 VDD.
Two I2C transactions are required to initialize the PLL frequency synthesizer. The first transaction ensures register ADDL2 at address 0x1A is written to its default of 0x80. The second transaction burst-writes 20 consecutive registers from address 0x00 to 0x13. The device is programmed to transmit a dummy packet with 8 zero bits in ASK mode. There is no RF emission at PA output. See Initial Programming section.
For example, the crystal frequency is 16MHz, the RF frequency is 315MHz, the 20 consecutive registers from address 0x00 to 0x13 can be configured as:
[0x90, 0x81, 0x03, 0x00, 0x00, 0x04, 0x80, 0x80, 0x60, 0x00, 0x00, 0xC4, 0xDE, 0x98, 0x28, 0x04, 0x04, 0x00, 0xFF, 0x00]
After initial programming, the device will enter the shutdown, standby, or programming state according to the setting of PWDN_MODE[1:0] (register CFG4, address 0x03, bit[1:0]). Configuration register values are retained in all states unless changed by programming, or if the device is powered off or undergoes a SOFTRESET. See Startup section for directions to program the device for data transmission.
The ASK carrier frequency is set by the FREQ bits in registers 0x0B, 0x0C, and 0x0D. The user calculates the divide ratio based on the carrier frequency and crystal frequency. The following equation shows how to determine the correct value to be loaded into the FREQ registers.
For example, the desired ASK transmit frequency is 315MHz and the crystal frequency is 16MHz. 315/16 is 19.6875. 19.6875 x 65536 is 1290240. Converted into hex, the value is 0x13B000. This value is loaded into FREQ[23:0]. In the case where the value is non-integer, the value may be rounded to the nearest integer.
In order to avoid integer boundary spurs in fractional-N PLL synthesizers, the crystal should be selected so that the RF carrier frequency is more than 0.4MHz apart from the nearest integer multiple of crystal frequency.
For example, the 16±0.002MHz crystals can be selected for the 433.92MHz RF carrier, which is more than 0.4MHz apart from the nearest integer multiple of crystal frequency at 432±0.054MHz. However, the 16±0.002MHz crystals are not suitable for a RF carrier at 912MHz or 928MHz.
In the programming mode, the crystal divider ratio is programmable. The crystal divider ratio should be configured so that the divided clock frequency is 3.2±0.1MHz. In addition, the PLL synthesizer requires a reference frequency (same as crystal frequency) between 12.8MHz and 19.2MHz. Therefore, when crystal divider ratio is 4, 5, or 6, allowed range of crystal frequency is 12.8MHz~13.2MHz, 15.5MHz~16.5MHz, or 18.6MHz~19.2MHz.
In another example, desired RF frequencies are 319.5MHz, 345.0MHz, and 433.92MHz, and recommended crystal selection is 13±0.002MHz so that integer boundary spurs are completely suppressed for three desired RF frequencies. Nevertheless, the 16±0.002MHz and 19.2±0.002MHz crystals are also acceptable.
In the preset mode, the crystal divider ratio is preset at 5. When the RF carrier frequency is very close to an integer multiple of 16MHz, the crystal selection can change to 16.384MHz or 16.128MHz, and the RF carrier frequency should be preset through OTP memory in production.