| Package Code | W60D1+1 |
| Outline Number | 21-100296 |
| Land Pattern Number | Refer to Application Note 1891 |
| Thermal Resistance, Four-Layer Board: | |
| Junction-to-Ambient (θJA) | 95.15°C/W |
| Junction-to-Case Thermal Resistance (θJC) | N/A |
| Package Code | T822Y+3 |
| Outline Number | 21-100185 |
| Land Pattern Number | 90-100070 |
| Thermal Resistance, Single-Layer Board: | |
| Junction-to-Ambient (θJA) | 130°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 8°C/W |
| Thermal Resistance, Four-Layer Board: | |
| Junction-to-Ambient (θJA) | 102°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 8°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+â€, “#â€, or “-†in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opMAX40025CAWT%2BT
data-opMAX40025CAWT%2B
data-opMAX40026ATA%2BT
data-opMAX40026ATA%2B
data-opMAX40025AAWT%2B
data-opMAX40025AAWT%2BT
data-opMAX40026ATA%2FVY%2BT
data-opMAX40026ATA%2FVY%2B
Inverting LVDS Output. Connect a 100Ω termination resistor between OUT- and OUT+. OUT- is at logic-low if VIN+ is at higher voltage compared to VIN-.Ground. Signal and power return (for TDFN-8: connect pins 2 and 3 together externally).Inverting InputNon-Inverting InputPositive Supply. For TDFN-8, connect pins 6 and 7 together externally.Non-Inverting LVDS Output. Connect a 100Ω termination resistor between OUT+ and OUT-. OUT+ is at logic-high if VIN+ is at higher voltage compared to VIN-.Exposed Pad (TDFN-8 Only). This pad must be connected to ground.