Applications Information

Applications InformationCapacitor Selection

Capacitors at the SYS and CAP pins reduce current peaks and increase efficiency. Ceramic capacitors are recommended because they have the lowest equivalent series resistance (ESR), smallest size, and lowest cost. Choose an acceptable dielectric such as X5R where the ambient temperature is less than +85°C or X7R where the ambient temperature is less than +125°C. Due to the ceramic capacitor’s capacitance derating at higher DC bias voltages, 2x47μF and 2x22μF ceramic capacitors are recommended at the SYS side and a 22μF ceramic capacitor at the CAP side for most applications. In addition, it is recommended to place a high-frequency filter capacitor of 1μF across the SYS and PGND pins as mentioned in the PCB Layout Guidelines.

Supercapacitor Selection

When the power source supplying the V_SYS voltage is removed, power to the output is provided by the MAX38889 operating in the backup or boost mode of operation using the supercapacitor as its source. In order to ensure that the supply voltage stays in regulation, the amount of power the supercapacitor can deliver at its minimal voltage should be greater than that required by the system. The MAX38889 presents a constant power load to the supercapacitor where smaller current is pulled out of the supercapacitor near its maximum V_CAP voltage. However, current drawn from the supercapacitor increases as it discharges to maintain constant power at the load. The amount of energy required in backup mode is the product of the constant backup power and time defined as backup time, T_BACKUP.

The amount of energy available in the supercapacitor (C_SC) is calculated using the following formula:

$E = \frac{1}{2} \times C_{S C} \times ({V^{2}}_{C A P M A X} - {V^{2}}_{C A P M I N}) (J)$

The amount of energy required to complete the backup equals to:

$E = V_{S Y S} \times I_{S Y S} \times T_{B A C K U P} (J)$

where I_SYS is the system load during backup.

Since the energy required at the system side during the backup event comes from the available energy in the supercapacitor, assuming conversion efficiency η and the given T_BACKUP, the required C_SCAP is determined by the following equation:

$C_{S C} = \frac{2 \times V_{S Y S} \times I_{S Y S} \times T_{B A C K U P}}{[({V^{2}}_{C A P M A X} - {V^{2}}_{C A P M I N}) \times η]} (F)$

For example, in the Figure 1 application circuit, assuming a 200mA system load and an average efficiency of 93%, the minimum value of the supercapacitor required for a 10s backup time is:

$C_{S C} = \frac{2 \times 3.0 V \times 0.2 A \times 10 s}{[({(2.7 V)}^{2} - {(1.5 V)}^{2}) \times 0.93]} = 2.56 F$

Figure 3. Charging/Discharging Waveforms\

Inductor Selection

The recommended inductor value for the MAX38889 is 0.47μH.

Status Flags

The MAX38889 has two dedicated pins to report the device status to the host processor. Both of these output pins are open-drain type and require external pullup resistors. The recommended value for the pullup resistors is 1MΩ. The pins should be pulled up to the SYS rail.

BKB Flag

The BKB flag indicates that the converter is in backup mode, and it is low when the part is in backup mode and V_FBS is regulating at 1.2V. This pin is high when V_FBS is above 1.23V. BKB is high when V_ENC and V_ENB are both low.

RDY Flag

The RDY flag helps the external processor to detect that the supercapacitor is ready to back up the SYS voltage. The RDY flag is high when V_FBCR > 0.5V and low when V_FBCR < 0.5V. The RDY threshold can be set using external resistor divider from the supercapacitor to GND.

Enabling the Device

The MAX38889 has dedicated enable pins for both charging and backup modes. Both of the pins can either be driven individually by a digital signal, pulled up, or strapped to the SYS rail.

Charger Enable Input (ENC)

Drive this pin high to enable charging of the supercapacitor while V_SYS is above the charging threshold. Drive it low to disable charging and reduce quiescent current. The ENC voltage applied should be more than 950mV.

Backup Enable Input (ENB)

Drive this pin high to enable system backup when V_SYS drops below the backup threshold. Drive it low to disable backup and reduce quiescent current. The ENB voltage applied should be more than 950mV.

PCB Layout Guidelines

Minimize trace lengths to reduce parasitic capacitance, inductance and resistance, and radiated noise. Keep the main power path from SYS, LX, CAP, and PGND as tight and short as possible. Minimize the surface area used for LX, since this is the noisiest node. It is recommended to place a filter capacitor close to the part across the SYS and GND pins to minimize voltage spikes on account of trace inductance, as shown in Figure 4.

Figure 4. High-Frequency Filter Capacitor

The trace between the feedback resistor-dividers should be as short as possible and should be isolated from the noisy power path. Refer to the EV kit layout for best practices.

The PCB layout is important for robust thermal design. The junction-to-ambient thermal resistance of the package greatly depends on the PCB type, layout, and pad connections. Using thick PCB copper and having a SYS, LX, CAP, and PGND copper pour will enhance the thermal performance. The TQFN package has a large, exposed pad under the package, which creates an excellent thermal path to the PCB. This pad is electrically connected to the analog GND of the controller (AGND). Its PCB pad should have multiple thermal vias connecting the pad to the internal ground plane. The thermal vias should either be capped or have a small diameter in order to minimize solder wicking and voids.