| Package Code | L1266M+1 |
| Outline Number | 21-100222 |
| Land Pattern Number | 90-100078 |
| Thermal Resistance, Single-Layer Board: | |
| Junction-to-Ambient (θJA) | 157°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 31°C/W |
| Thermal Resistance, Four-Layer Board: | |
| Junction-to-Ambient (θJA) | 115°C/W |
| Junction-to-Case Thermal Resistance (θJC) | 31°C/W |
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
data-opMAX33251EELC%2BT
data-opMAX33251EELC%2B
data-opMAX33250EELC%2B
data-opMAX33250EELC%2BT
Supply Voltage of Logic Side A. Bypass VCCA with a 0.1μF ceramic capacitor to GNDATTL/CMOS Transmitter Input 1TTL/CMOS Transmitter Input 2TTL/CMOS Receiver Output 1TTL/CMOS Receiver Output 2Ground for Logic Side AGround for Field Side BRS-232 Receiver Input 2RS-232 Receiver Input 1RS-232 Transmitter Output 2RS-232 Transmitter Output 1Supply Voltage of Logic Side B. Bypass VCCB with a 0.1μF ceramic capacitor to GNDB