Pin Specifications

Pin Configuration 68 TQFN
PIN NAME FUNCTION MODE FUNCTION
Primary Signal (Default) Alternate Function 1 Alternate Function 2 Alternate Function 3 Alternate Function 4
Pin Description
POWER (See the Applications Information section for bypass capacitor recommendations.)
65 VCORE — — — — — Digital Power-Supply Input. Bypass with 100nF to VSS and 1μF with 10mΩ to 150mΩ ESR to VSS.
64 VDD18 — — — — — This device pin can be configured as a LDO output or a voltage supply input. Bypass with 100nF to VSS. Do not connect this device pin to any other external circuitry.
63 VDDIO — — — — — Power Supply Input. This pin must always be connected to the VDDA device pin at the PCB level. Bypass this pin with 100nF to VSS and 1μF with 10mΩ to 150mΩ ESR to VSS.
27 VDDA — — — — — Analog Supply Voltage. This pin must always be connected to the VDDIO device pin at the PCB level. Bypass this pin to VSSA with 1.0μF and 0.01μF capacitors as close as possible to the package.
58 VREG1 — — — — — Bypass with 4.7nF to VSS. Do not connect this device pin to any other external circuitry.
30, 62 VSS — — — — — Digital Ground
26 VSSA — — — — — Analog Ground
EP Exposed Pad — — — — — Exposed Pad. This pad must be connected to VSS. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
RESET AND CONTROL
61 RSTN — — — — — Active-Low, External System Reset Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR reset (resetting all logic on all supplies) and begins execution.
This pin has an internal pullup to the VDDIO supply.
CLOCK
59 HFXIN — — — — — RF Crystal Oscillator Input. Connect the crystal between HFXIN and HFXOUT. Optionally, this pin can be configured as the input for an external square-wave source. See the Electrical Characteristics table for details of the crystal requirements.
60 HFXOUT — — — — — RF Crystal Oscillator Output. Connect the crystal between HFXIN and HFXOUT. See the Electrical Characteristics table for details of the crystal requirements.
N.A. EXT_CLK — — — — — See Pin Description P0.10 for details.
16-/24-BIT DELTA-SIGMA ADC WITH PGA
68 ADC0_RDY — — — — — ADC0 Ready
1 ADC1_RDY — — — — — ADC1 Ready
17 REF0P — — — — — Positive Differential Reference 0 Input. REF0P must be more positive than REF0N.
19 REF0N — — — — — Negative Differential Reference 0 Input. REF0P must be more positive than REF0N.
36 REF1P — — — — — Positive Differential Reference 1 Input. REF1P must be more positive than REF1N.
35 REF1N — — — — — Negative Differential Reference 1 Input. REF1P must be more positive than REF1N.
15 CAP0P — — — — — ADC0 PGA Positive Output. Connect 1nF capacitor across CAP0P and CAP0N.
16 CAP0N — — — — — ADC0 PGA Negative Output. Connect 1nF capacitor across CAP0P and CAP0N.
38 CAP1P — — — — — ADC1 PGA Positive Output. Connect 1nF capacitor across CAP1P and CAP1N.
37 CAP1N — — — — — ADC1 PGA Negative Output. Connect 1nF capacitor across CAP1P and CAP1N.
20 AIN0 — — — — — Channel 0 Analog Input/Positive Differential Reference Input. When used as an analog input, may serve as either the positive or negative differential input. May also serve as current source output. When used as a reference input paired with AIN1, AIN0 must be more positive than AIN1.
21 AIN1 — — — — — Channel 1 Analog Input/Negative Differential Reference Input. When used as an analog input, may serve as either the positive or negative differential input. May also serve as current source output. When used as a reference input paired with AIN0, AIN0 must be more positive than AIN1.
22 AIN2 — — — — — Channel 2 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
23 AIN3 — — — — — Channel 3 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
24 AIN4 — — — — — Channel 4 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
25 AIN5 — — — — — Channel 5 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
28 AIN6 — — — — — Channel 6 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
29 AIN7 — — — — — Channel 7 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
31 AIN8 — — — — — Channel 8 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
32 AIN9 — — — — — Channel 9 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
33 AIN10 — — — — — Channel 10 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
34 AIN11 — — — — — Channel 11 Analog Input. May serve as either the positive or negative differential input paired with any of the other AINx analog inputs. May also serve as current source output.
12-BIT DAC
40 DAC12_OUT — — — — — 12-Bit DAC Analog Voltage Output
INTERNAL REFERENCE
39 INT_REF — — — — — Internal Reference Output. It must be bypassed to VSSA with a 4.7μF capacitor.
GPIO AND ALTERNATE FUNCTION
9 P0.0 P0.0 SWDIO — TMR0C_IA — Single-Wire Debug I/O; Timer0 Port Map C Input
10 P0.1 P0.1 SWDCLK — TMR0C_OA — Single-Wire Debug Clock; Timer0 Port Map C Output
11 P0.6 P0.6 I2C0A_SCL LPTMR0B_IA TMR3C_IA — I2C0 Port Map A Serial Clock; Low-Power Timer0 Port Map B Input 2 Bits or Lower 16 Bits; Timer3 Port Map C Input 32 Bits or Lower 16 Bits
12 P0.7 P0.7 I2C0A_SDA LPTMR0B_OA TMR3C_OA — I2C0 Port Map A Serial Data; Low-Power Timer0 Port Map B Output 32 Bits or Lower 16 Bits; Timer3 Port Map C Output 32 Bits or Lower 16 Bits
41 P0.8 P0.8 UART0A_RX I2S0B_SDO TMR0C_IA — UART0 Port Map A Rx; I2S0 Port Map B Serial Data Output; Timer0 Port Map C Input 32 Bits or Lower 16 Bits
42 P0.9 P0.9 UART0A_TX I2S0B_LRCLK TMR0C_OA — UART0 Port Map A Tx; I2S0 Port Map B Left/Right Clock; Timer0 Port Map C Output 32 Bits or Lower 16 Bits
43 P0.10 P0.10 UART0A_CTS I2S0B_BCLK TMR1C_IA EXT_CLK UART0 Port Map A CTS; I2S0 Port Map B Bit Clock; Timer1 Port Map C Input 32 Bits or Lower 16 Bits. This pin can be used to source a clock signal. It can also be used to receive a clock signal. This clock signal can be used for the 16-/24-bit delta-sigma converters. See the Electrical Characteristics table for the External _Clock parameters.
44 P0.11 P0.11 UART0A_RTS I2S0B_SDI TMR1C_OA — UART0 Port Map A RTS; I2S0 Port Map B Serial Data Input; Timer1 Port Map C Output 32 Bits or Lower 16 Bits
45 P0.13 P0.13 — — TMR2C_OA SPI1D_SS0 Timer2 Port Map C Output 32 Bits or Lower 16 Bits; SPI1 Port Map D Slave Select 0
46 P0.14 P0.14 SPI1A_MISO UART2B_RX TMR3C_IA — SPI1 Port Map A Master In Slave Out; UART2 Port Map B Rx; Timer3 Port Map C Input 32 Bits or Lower 16 Bits
47 P0.15 P0.15 SPI1A_MOSI UART2B_TX TMR3C_OA — SPI1 Port Map A Master Out Slave In; UART2 Port Map B Tx; Timer3 Port Map B Output 32 Bits or Lower 16 Bits
48 P0.16 P0.16 SPI1A_SCK UART2B_CTS TMR0C_IA — SPI1 Port Map A Serial Clock; UART2 Port Map B CTS; Timer0 Port Map C Input 32 Bits or Lower 16 Bits
53 P0.17 P0.17 SPI1A_SS0 UART2B_RTS TMR0C_OA — SPI1 Port Map A Slave Select 0; UART2 Port Map B RTS; Timer0 Port Map C Output 32 Bits or Lower 16 Bits
54 P0.18 P0.18 I2C2A_SCL — TMR1C_IA — I2C2 Port Map A Serial Clock; Timer1 Port Map C Input 32 Bits or Lower 16 Bits
55 P0.19 P0.19 I2C2A_SDA — TMR1C_OA — I2C2 Port Map A Serial Data; Timer1 Port Map C Output 32 Bits or Lower 16 Bits
66 P0.21 P0.21 CM4_TX — TMR2C_OA — CM4 Tx Event Output; Timer2 Port Map C Output 32 Bits or Lower 16 Bits
57 P0.31 P0.31 - — TMR3C_OA — Timer3 Port Map C Output 32 Bits or Lower 16 Bits
49 P1.7 P1.7 — — — — GPIO Only
51 P1.8 P1.8 UART2A_RX UART2B_RTS — — UART2 Port Map A Rx; UART2 Port Map B RTS
5 P1.9 P1.9 UART2A_TX — — — UART2 Port Map A Tx
6 P1.10 P1.10 UART2A_CTS — — — UART2 Port Map A CTS
7 P1.11 P1.11 UART2A_RTS — TMR2C_OA — UART2 Port Map A RTS; Timer2 Port Map C Output 32 Bits or Lower 16 Bits
8 P1.12 P1.12 — — — — GPIO Only
NO CONNECT
3 FSK_IN — — — — — Do Not Connect. Internally connected. Do not make any electrical connection to this pin, including power supply grounds.
4 FSK_OUT — — — — — Do Not Connect. Internally connected. Do not make any electrical connection to this pin, including power supply grounds.
2 HART_REF — — — — — This pin must be connected to a 0.1µF capacitor.
13, 14, 18, 50, 52, 56, 67 N.C. — — — — — No Connection. Not internally connected.