Electrical Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics

(Limits are 100% tested at TA = +25°C and TA = +105°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. Specifications to the minimum operating temperature are guaranteed by design and are not production tested.)

POWER / BOTH SINGLE-SUPPLY AND MULTISUPPLY OPERATION
Supply Voltage, Digital VDDIO The VDDIO device pin must be connected to the VDDA device pin. 2.7 3.3 3.63 V
VDD18 1.71 1.8 1.98
Supply Voltage, Core VCORE OVR = [00] 0.855 0.9 0.945 V
OVR = [01] 0.95 1.0 1.05
Default OVR = [10] 1.045 1.1 1.155
Supply Voltage, Analog VDDA The VDDIO device pin must be connected to the VDDA device pin. 2.7 3.3 3.63 V
Power-Fail Reset Voltage VRST Monitors VDDIO 1.55 2.4 V
Monitors VCORE during multisupply operation 0.76 0.86
Power-On-Reset (POR) Voltage VPOR Monitors VDDIO 1.4 V
Monitors VCORE during multisupply operation 0.6
POWER / SINGLE-SUPPLY OPERATION (VDDIO ONLY)
VDDIO Current ACTIVE Mode IDD_DACTS Dynamic, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in ACTIVE mode, executing Coremark, ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10], internal regulator set to 1.1V, fSYS_CLK(MAX) = 100MHz 64.5 μA/MHz
OVR = [01], internal regulator set to 1.0V, fSYS_CLK(MAX) = 50MHz 62.5
OVR = [00], internal regulator set to 0.9V, fSYS_CLK(MAX) = 12MHz 59.5
Dynamic, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10], internal regulator set to 1.1V, fSYS_CLK(MAX) = 100MHz 49.4
OVR = [01], internal regulator set to 1.0V, fSYS_CLK(MAX) = 50MHz 47
OVR = [00], internal regulator set to 0.9V, fSYS_CLK(MAX) = 12MHz 44.1
IDD_FACTS Fixed, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in ACTIVE mode, 0MHz execution, ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10], internal regulator set to 1.1V 796 μA
OVR = [01], internal regulator set to 1.0V 647
OVR = [00], internal regulator set to 0.9V 475
VDDIO Current SLEEP Mode IDD_DSLPS Dynamic, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10], internal regulator set to 1.1V 39.2 μA/MHz
OVR = [01], internal regulator set to 1.0V, fSYS_CLK(MAX) = 50MHz 37.5
OVR = [00], internal regulator set to 0.9V, fSYS_CLK(MAX) = 12MHz 36.1
Dynamic, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in SLEEP mode, ECC disabled, DMA disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10], internal regulator set to 1.1V, fSYS_CLK(MAX) = 100MHz 21.1
OVR = [01], internal regulator set to 1.0V, fSYS_CLK(MAX) = 50MHz 19
OVR = [00], internal regulator set to 0.9V, fSYS_CLK(MAX) = 12MHz 17.2
IDD_FSLPS Fixed, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in SLEEP mode, ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10], internal regulator set to 1.1V 796 μA
OVR = [01], internal regulator set to 1.0V 647
OVR = [00], internal regulator set to 0.9V 475
VDDIO Fixed Current, DEEPSLEEP Mode IDD_FDSLS Standby state with full data retention and 160KB SRAM retained VDDIO = 3.3V 4.0 μA
VDDIO Fixed Current, BACKUP Mode IDD_FBKUS VDDIO = 3.3V 0KB SRAM retained, retention regulator disabled 0.32 μA
VDDIO Fixed Current, BACKUP Mode IDD_FBKUS VDDIO = 3.3V 20KB SRAM retained 1.04 μA
40KB SRAM retained 1.37
80KB SRAM retained 1.90
160KB SRAM retained 2.84
VDDIO Fixed Current, STORAGE Mode IDD_FSTOS VDDIO = 3.3V 0.362 μA
SLEEP Mode Resume Time tSLP_ONS 2.1 μs
DEEPSLEEP Mode Resume Time tDSL_ONS fast_wk_en = 1 89 us
fast_wk_en = 0 129
BACKUP Mode Resume Time tBKU_ONS Includes system initialization and ROM execution time 1.25 ms
STORAGE Mode Resume Time tSTO_ONS Includes system initialization and ROM execution time 1.5 ms
POWER / MULTISUPPLY OPERATION
VCORE Current, ACTIVE Mode ICORE_DACTD Dynamic, IPO enabled, total current into VCORE pin, CPU in ACTIVE mode, executing Coremark, ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10],
VCORE = 1.1V,
fSYS_CLK(MAX) = 100MHz 		63.7 μA/MHz
OVR = [01], VCORE = 1.0V, fSYS_CLK(MAX) = 50MHz 61.9
OVR = [00], VCORE = 0.9V, fSYS_CLK(MAX) = 12MHz 59.4
Dynamic, IPO enabled, total current into VCORE pin, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10], VCORE = 1.1V, fSYS_CLK(MAX) = 100MHz 48.9
OVR = [01], VCORE = 1.0V, fSYS_CLK(MAX) = 50MHz 46.6
OVR = [00], VCORE = 0.9V, fSYS_CLK(MAX) = 12MHz 44.5
ICORE_FACTD Fixed, IPO enabled, total current into VCORE pin, CPU in ACTIVE mode, 0MHz execution, ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10],
VCORE = 1.1V 		362 μA
OVR = [01],
VCORE = 1.0V 		217
OVR = [00],
VCORE = 0.9V 		109
VDDIO Current, ACTIVE Mode IDD_DACTD Dynamic, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in ACTIVE mode, executing Coremark, ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10], fSYS_CLK(MAX) = 100MHz 0.51 μA/MHz
OVR = [01], fSYS_CLK(MAX) = 50MHz 0.51
OVR = [00], fSYS_CLK(MAX) = 12MHz 0.51
Dynamic, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in ACTIVE mode, executing While(1), ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10], fSYS_CLK(MAX) = 100MHz 0.51
OVR = [01], fSYS_CLK(MAX) = 50MHz 0.51
OVR = [00], fSYS_CLK(MAX) = 12MHz 0.51
IDD_FACTD Fixed, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in ACTIVE mode, 0MHz execution, ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10],
VCORE = 1.1V 		367 μA
OVR = [01],
VCORE = 1.0V 		367
OVR = [00],
VCORE = 0.9V 		307
ICORE_DSLPD Dynamic, IPO enabled, total current into VCORE pin, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10],
VCORE = 1.1V,
fSYS_CLK(MAX) = 100MHz 		39.2 μA/MHz
VCORE Current, SLEEP Mode ICORE_DSLPD Dynamic, IPO enabled, total current into VCORE pin, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [01],
VCORE = 1.0V,
fSYS_CLK(MAX) = 50MHz 		37.5 μA/MHz
OVR = [00],
VCORE = 0.9V,
fSYS_CLK(MAX) = 12MHz 		37
Dynamic, IPO enabled, total current into VCORE pin, CPU in SLEEP mode, ECC disabled, DMA disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10],
VCORE = 1.1V,
fSYS_CLK(MAX) = 100MHz 		21.1
OVR = [01],
VCORE = 1.0V,
fSYS_CLK(MAX) = 50MHz 		19.2
OVR = [00],
VCORE = 0.9V,
SYS_CLK(MAX) = 12MHz 		17.9
ICORE_FSLPD Fixed, IPO enabled, total current into VCORE pin, CPU in SLEEP mode, ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR [10],
VCORE = 1.1V 		362 μA
OVR [01],
VCORE = 1.0V 		217
OVR [00],
VCORE = 0.9V 		109
VDDIO Current, SLEEP Mode IDD_DSLPD Dynamic, IPO enabled, total current into VDD pin, VDDIO = 3.3V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10],
VCORE = 1.1V,
fSYS_CLK(MAX) = 100MHz 		0.001 μA/MHz
Dynamic, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in SLEEP mode, ECC disabled, standard DMA with two channels active, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [01],
VCORE = 1.0V,
fSYS_CLK(MAX) = 50MHz 		0.001
OVR = [00],
VCORE = 0.9V,
fSYS_CLK(MAX) = 12MHz 		0.001
IDD_FSLPD Fixed, IPO enabled, total current into VDDIO pin, VDDIO = 3.3V, CPU in SLEEP mode, ECC disabled, inputs tied to VSS or VDDIO, outputs source/sink 0mA OVR = [10],
VCORE = 1.1V 		367 μA
OVR = [01],
VCORE = 1.0V 		367
OVR = [00],
VCORE = 0.9V 		307
VCORE Fixed Current, DEEPSLEEP Mode ICORE_FDSLPD VDDIO = 3.3V, VCORE = 1.1V 10 μA
VDDIO = 3.3V, VCORE = 0.855V 3.8
VDD Fixed Current, DEEPSLEEP Mode IDD_FDSLPD VDDIO = 3.3V, VCORE = 1.1V 0.34 μA
VDDIO = 3.3V, VCORE = 0.855V 0.34
VCORE Fixed Current, BACKUP Mode ICORE_FBKUD 0KB SRAM retained, retention regulator disabled VDDIO = 3.3V, VCORE = 1.1V 0.225 μA
VDDIO = 3.3V, VCORE = 0.855V 0.13
20KB SRAM retained VDDIO = 3.3V, VCORE = 1.1V 1.256
VDDIO = 3.3V, VCORE = 0.855V 0.507
40KB SRAM retained VDDIO = 3.3V, VCORE = 1.1V 2.243
VDDIO = 3.3V, VCORE = 0.855V 0.877
80KB SRAM retained VDDIO = 3.3V, VCORE = 1.1V 3.97
VDDIO = 3.3V, VCORE = 0.855V 1.49
160KB SRAM retained VDDIO = 3.3V, VCORE = 1.1V 7.22
VDDIO = 3.3V, VCORE = 0.855V 2.61
VDDIO Fixed Current, BACKUP Mode IDD_FBKUD 0KB SRAM retained, retention regulator disabled VDDIO = 3.3V, VCORE = 1.1V 0.34 μA
VDDIO = 3.3V, VCORE = 0.855V 0.34
20KB SRAM retained VDDIO = 3.3V, VCORE = 1.1V 0.32
VDDIO = 3.3V, VCORE = 0.855V 0.32
40KB SRAM retained VDDIO = 3.3V, VCORE = 1.1V 0.32
VDDIO = 3.3V, VCORE = 0.855V 0.108
80KB SRAM retained VDDIO = 3.3V, VCORE = 1.1V 0.32
VDDIO = 3.3V, VCORE = 0.855V 0.32
160KB SRAM retained VDDIO = 3.3V, VCORE = 1.1V 0.32
VDDIO = 3.3V, VCORE = 0.855V 0.32
VCORE Fixed Current, STORAGE Mode ICORE_FSTOD VDDIO = 3.3V, VCORE = 1.1V 0.226 μA
VDDIO = 3.3V, VCORE = 0.855V 0.112
VDDIO Fixed Current, STORAGE Mode IDD_FSTOD VDDIO = 3.3V; VCORE = 1.1V 0.335 μA
VDDIO = 3.3V; VCORE = 0.855V 0.335
SLEEP Mode Resume Time tSLP_OND 2.1 μs
DEEPSLEEP Mode Resume Time tDSL_OND fast_wk_en = 1 81 μs
fast_wk_en = 0 129
BACKUP Mode Resume Time tBKU_OND Includes system initialization and ROM execution time 1.25 ms
STORAGE Mode Resume Time tSTO_OND Includes system initialization and ROM execution time 1.5 ms
GENERAL-PURPOSE I/O
Input Low Voltage for All GPIO, RSTN VIL_GPIO Pin configured as GPIO 0.3 × VDDIO V
Input High Voltage for All GPIO, RSTN VIH_GPIO Pin configured as GPIO 0.7 × VDDIO V
Output Low Voltage for All GPIO Except P0.6, P0.7, P0.13, P0.18, P0.19 VOL_GPIO VDDIO = 2.7V, IOL = 1mA, DS[1:0] = 00 0.2 0.4 V
VDDIO = 2.7V, IOL = 2mA, DS[1:0] = 10 0.2 0.4
VDDIO = 2.7V, IOL = 4mA, DS[1:0] = 01 0.2 0.4
VDDIO = 2.7V, IOL = 6mA, DS[1:0] = 11 0.2 0.4
Output Low Voltage for GPIO P0.6, P0.7, P0.13, P0.18, P0.19 VOL_I2C VDDIO = 2.7V, IOL = 2mA, DS = 0 0.2 0.4 V
VDDIO = 2.7V, IOL = 10mA, DS = 1 0.2 0.4
Output High Voltage for All GPIO Except P0.6, P0.7, P0.13, P0.18, P0.19 VOH_GPIO VDDIO = 2.7V, IOH = -1mA, DS[1:0] = 00 VDDIO - 0.4 V
VDDIO = 2.7V, IOH = -2mA, DS[1:0] = 10 VDDIO - 0.4
VDDIO = 2.7V, IOH = -4mA, DS[1:0] = 01 VDDIO - 0.4
VDDIO = 2.7V, IOH = -6mA, DS[1:0] = 11 VDDIO - 0.4
Output High Voltage for GPIO P0.6, P0.7, P0.13, P0.18, and P0.19 VOH_I2C VDDIO = 2.7V, IOH = -2mA, DS = 0 VDDIO - 0.4 V
VDDIO = 2.7V, IOH = -10mA, DS = 1 VDDIO - 0.4
Combined IOL, All GPIO IOL_TOTAL 100 mA
Combined IOH, All GPIO IOH_TOTAL -100 mA
Input Hysteresis (Schmitt) VIHYS 300 mV
Input/Output Pin Capacitance for All Pins CIO 4 pF
Input Leakage Current Low IIL VIN = 0V, internal pullup disabled -500 +500 nA
Input Leakage Current High IIH VIN = 3.6V, internal pulldown disabled -500 +500 nA
Input Pullup Resistor to RSTN RPU_VDD Pullup to VDDIO = VRST, RSTN at VIH 18.7 kΩ
Pullup to VDDIO = 3.63V, RSTN at VIH 10.0
Input Pullup Resistor for All GPIO RPU Device pin configured as GPIO, pullup to VDDIO = VRST, device pin at VIH 18.7 kΩ
Device pin configured as GPIO, pullup to VDDIO = 3.63V, device pin at VIH 10.0
Input Pulldown Resistor for All GPIO RPD Device pin configured as GPIO, pulldown to VSS, VDDIO = VRST, device pin at VIL 17.6 kΩ
Device pin configured as GPIO, pulldown to VSS, VDDIO = 3.63V, device pin at VIL 8.8
CLOCKS
System Clock Frequency fSYS_CLK 100 MHz
System Clock Period tSYS_CLK 1/fSYS_CLK μs
Internal Primary Oscillator (IPO) fIPO Default OVR = [10] 100 MHz
External RF Oscillator (ERFO) fERFO Required crystal characteristics: CL = 12pF, ESR ≤ 50Ω, C0 ≤ 7pF, temperature stability ±20ppm, initial tolerance ±20ppm 16 32 MHz
Internal Baud Rate Oscillator (IBRO) fIBRO 7.3728 MHz
Internal NanoRing Oscillator (INRO) fINRO Measured at VDDIO = 2.7V 70 kHz
External Clock fEXT_CLK External clock selected (P0.10) 25 MHz
FLASH MEMORY
Flash Erase Time tM_ERASE Mass erase 30 ms
tP_ERASE Page erase 30
Flash Programming Time Per Word tPROG 32-bit programming mode,
fFLC_CLK = 1MHz 		42 μs
Flash Endurance 10 kcycles
Data Retention tRET TA = +125°C 10 years
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—16-/24-Bit Δ-Σ ADC with PGA

(VDDA = +3.3V, REFP - REFN = VDDA, TA = TMIN to TMAX, unless otherwise noted. TA = +25°C for typical specifications, unless otherwise noted. Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)

ANALOG INPUTS
Full-Scale Input Voltage FS ±VREF/
Gain
Absolute Input Voltage Buffers disabled VSSA - 30mV VDDA + 30mV V
Input Voltage Range Unipolar 0 VREF V
Bipolar -VREF VREF
Common-Mode Voltage Range VCM AIN buffers/PGA disabled VSSA VDDA V
Buffers enabled VSSA + 0.1 VDDA - 0.1
PGA gain = 1 to 16 VSSA + 0.1 + (VIN)(Gain)/2 VDDA - 0.1 - (VIN)(Gain)/2
PGA gain = 32 to 128 VSSA + 0.2 + (VIN)(Gain)/2 VDDA - 0.2 - (VIN)(Gain)/2
Differential Input Current Buffer disabled ±1 µA/V
Buffer enabled 0 to 50 nA
PGA enabled ±1
Absolute Input Current Buffer disabled ±1 µA/V
Buffer enabled 20 to 80 nA
PGA enabled, -40°C to +105°C -2 2
Input Capacitance Bypass mode 10 pF
SYSTEM PERFORMANCE
Resolution 24 bits
Data Rate 50hZ/60Hz FIR filter, single-cycle conversions 1, 2, 4, 8, 16 sps
50Hz FIR filter, single-cycle conversions 1.3, 2.5, 5, 10, 20, 35.6
60Hz FIR filter, single-cycle conversions 1.3, 2.5, 5, 10, 20, 36.5
SINC4 filter, single-cycle conversions 1, 2.5, 5, 10, 15, 30, 60, 120, 240, 480, 960, 1920
SINC4 filter, continuous conversions 4, 10, 20, 40, 60, 120, 240, 480, 960, 1920, 3840, 7680
SINC4 filter, duty cycle conversions 0.25, 0.0625, 1.25, 2.5, 3.75, 7.7, 15, 30, 60, 120, 240, 480
Data Rate Tolerance Determined by internal clock accuracy -6 6 %
Integral Nonlinearity (Note 2) INL Differential input, reference buffer enabled, PGA = 1, tested at 16sps, measured at +25°C, VDDA = 3.3V -12 +2 +12 ppmFS
Differential input, PGA = 2 - 16 6
Differential input, PGA = 32 - 64 11
Differential input, PGA = 128 15
Offset Error Referred to modulator input. After self and system calibration; VREFP - VREFN = 2.5V, tested at 16sps, VDDA = 3.3V -25 ±0.5 +25 μV
Offset Error Drift ±50 nV/°C
PGA Gain Settings 1, 2, 4, 8, 16, 32, 64, 128
Digital Gain Settings 2, 4
PGA Gain Error (Note 1) No calibration ±0.3 %
Gain = 1, after calibration -0.012 +0.012
PGA Gain Drift 32 ppmFS/
°C
Input Noise Vn FIR50Hz/60Hz, 16.8sps, PGA = 128 208 nVRMS
Noise-Free Resolution NFR FIR50Hz/60Hz, 16.8sps, PGA = 1 17.3 bits
Normal-Mode Rejection (Internal Clock) NMR 50Hz/60Hz FIR filter, 50Hz ±1%, 16sps conversion, ​GBD 88 dB
50Hz/60Hz FIR filter, 60Hz ±1%, 16sps single-cycle conversion, ​GBD 88
50Hz FIR filter, 50Hz ±1%, 35.6sps single-cycle conversion, ​GBD 49
60Hz FIR filter, 60Hz ±1%, 35.6sps single-cycle conversion, ​GBD 55.6
SINC4 filter, 50Hz ±1%, 10sps single-cycle conversion, ​GBD 88
SINC4 filter 60Hz ±1%, 10sps single-cycle conversion, ​GBD 91
Normal-Mode Rejection (External Clock) NMR 50Hz/60Hz FIR filter, 50Hz or 60Hz ±1%, 16sps single-cycle conversion 91 dB
50Hz FIR filter, 50Hz ±1%, 35.6sps single-cycle conversion 49.4
60Hz FIR filter, 60Hz ±1%, 35.6sps single-cycle conversion 55.6
SINC4 filter, 50Hz ±1%, 10sps single-cycle conversion 92.4
SINC4 filter, 60Hz ±1%, 10sps single-cycle conversion 92.6
Common-Mode Rejection CMR DC rejection, any PGA gain 100 dB
Common-Mode Rejection CMR60 50Hz/60Hz rejection, PGA enabled 104
Power Supply Rejection PSRRA 94 dB
REFERENCE INPUTS
Reference Voltage Range Reference buffer(s) disabled VSSA - 30m VDDA + 30m V
Reference buffer(s) enabled VSSA + 0.1 VDDA - 0.1
Reference Voltage Input VREF = VREFP - VREFN 0.75 2.5 VDDA V
Reference Input Current Reference buffer disabled 2.1 µA/V
Reference buffer enabled -200 61 +200 nA
Reference Input Capacitance Reference buffers disabled 15 pF
MATCHED CURRENT SOURCES
Matched Current Source Outputs 10, 50, 75, 100, 125, 150, 175, 200, 225, 250, 300, 400, 600, 800, 1200, 1600 µA
Current Source Output Voltage Compliance IDAC ≤ 250µA 0 VDDA - 0.7 V
IDAC = 1.6mA 0 VDDA - 1.2
Initial Tolerance TA = +25°C, GBD -5 ±1 +5 %
Current Matching Between IDACs ±0.1 %
Temperature Drift Matching Between IDACs 10 ppm/C
Current Source Output Noise IN Output current = 250µA; SINC4 filter, 60sps continuous; noise is referred to input 0.47 pA rms
VBIAS OUTPUTS
VBIAS Voltage VDDA/2 V
VBIAS Voltage Output Impedance 125k (active), 20k (passive), 125k (passive) Ω
SYSTEM TIMING
Power-On Wake-Up Time From VDDA > VPOR 240 µs
PGA Power-Up Time CFILTER = 0 0.25 ms
CFILTER = 20nF 2
CFILTER = 100nF 10
PGA Settling Time After changing gain settings to Gain = 1, CFILTER = 0 0.25 ms
After changing gain settings to Gain = 1, CFILTER = 100nF 10
After changing gain settings to Gain = 128, CFILTER = 0 2
Input Multiplexer Power-Up Time Settled to 21 bits with 10pF load 2 µs
Input Multiplexer Channel-to-Channel Settling Time Settled to 21 bits with 2kΩ external source resistor 2 µs
VBIAS Power-Up Time Active generator; settled within 1% of final value; CLOAD = 1µF 10 ms
125K passive generator; settled within 1% of final value; CLOAD = 1µF 575
20K passive generator; settled within 1% of final value; CLOAD = 1µF 90
VBIAS Settling Time Active generator; settled within 1% of final value; CLOAD = 1µF 10 ms
125K passive generator; settled within 1% of final value; CLOAD = 1µF 605
20K passive generator; settled within 1% of final value; CLOAD = 1µF 100
Matched Current Source Startup Time 110 µs
Matched Current Source Settling Time 12.5 µs
POWER SPECIFICATIONS
VDDA Current ADC0 only Standby mode, VDDA = VREF = VIN = 3.3V 92 µA
Bypass mode, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 60sps 166
Buffered mode, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 60sps 193
PGA enabled, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 60sps 292
ADC1. ADC0 must be in Standby mode Bypass mode, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 60sps 167
Buffered mode, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 60sps 193
PGA enabled, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 60sps 292
VDDA Duty Cycle Power Mode ADC0 only Bypass mode, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 15sps 74 µA
Buffered mode, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 15sps 89
PGA enabled, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 15sps 196
ADC1. ADC0 must be enabled in Standby mode Bypass mode, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 15sps 74
Buffered mode, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 15sps 89
PGA enabled, IDAC, VBIAS sources off, VDDA = VREF = VIN = 3.3V, SINC4 filter, continuous conversions at 15sps 196
LDO
VDD18 Output Capacitance 100 nF
VDD18 Output Voltage VDD18 configured as an output 1.71 1.8 1.98 V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—12-Bit DAC

(VDDA = 3.3V, RL = 10kΩ and CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. TA = +25°C for typical specifications, unless otherwise noted. VREF = 1.5V. Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)

Resolution DACR 12 bits
Differential Nonlinearity DNL Power mode = 2 or 3, noise filter enabled GBD ±1 LSB
Integral Nonlinearity INL Power mode = 2 or 3, noise filter enabled GBD ±1 LSB
Offset Error EO Measure at VDDA = 3.3V 4 mV
Output Voltage Range VO DAC12_OUT device pin; min code to max code, GBD VSSA + EO VDDA - 0.5 V
Output Impedance Power mode = 3 6.1 kΩ
Power mode = 2 8.9
Power mode = 1 16.3
Power mode = 0 97.7
Voltage Output Settling Time tSFS Noise filter enabled, code 400h to C00h, rising or falling, to ±0.5 LSB 4 ms
Noise filter disabled, code 400h to C00h, rising or falling, to ±0.5 LSB 0.03
Glitch Energy Power mode = 0, 1, or 2 12 V x ns
Power mode = 3, code 000h to A50h 12
Active Current IDAC12 Static,
VREF = 2.5V 		Power mode = 3 680 μA
Power mode = 2 570
Power mode = 1 458
Power mode = 0 347
Static,
VREF = 2.0V 		Power mode = 3 601
Power mode = 2 509
Power mode = 1 418
Power mode = 0 327
Static,
VREF = 1.5V 		Power mode = 3 497
Power mode = 2 431
Power mode = 1 364
Power mode = 0 297
Static,
VREF = 1.0V 		Power mode = 3 407
Power mode = 2 361
Power mode = 1 304
Power mode = 0 284
Power-On Time Excluding reference 10 μs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—Internal Voltage Reference

(VDDA = 3.3V, TA = TMIN to TMAX unless otherwise noted. Internal reference mode, 4.7μF at INT_REF; VREF = 1.5V. TA = +25°C for typical specifications, unless otherwise noted. Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)

Output Voltage at INT_REF VINT_REF TA = +25°C INT_REF 1.024V 1.024 V
INT_REF 1.50V 1.500
INT_REF 2.048V 2.048
INT_REF 2.50V 2.500
Internal Reference Temperature Coefficient TCREF TA =  -40°C to +105°C ±50 ppm/°C
Turn-On Time tON GBD 0.1 + (INT_VREF x 1.8) 10 ms
Leakage Current with INT_REF Output Disabled IINT_REF GBD 15 50 nA
INT_REF Line Regulation ±50 μV/V
INT_REF Load Regulation INT_Load ISOURCE = 0 to 500μA, TA = +25°C 10 μV/μA
Reference Supply Current Buffer enabled 270 μA
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—SPI

(Timing specifications are guaranteed by design and not production tested.)

MASTER MODE
SPI Master Operating Frequency fMCK fSYS_CLK = 100MHz,
fMCK(MAX) = fSYS_CLK/2 		50 MHz
SPI Master SCK Period tMCK 1/fMCK ns
SCK Output Pulse-Width High/Low tMCH, tMCL tMCK/2 ns
MOSI Output Hold Time After SCK Sample Edge tMOH tMCK/2 ns
MOSI Output Valid to Sample Edge tMOV tMCK/2 ns
MOSI Output Hold Time After SCK Low Idle tMLH tMCK/2 ns
MISO Input Valid to SCK Sample Edge Setup tMIS 5 ns
MISO Input to SCK Sample Edge Hold tMIH tMCK/2 ns
SLAVE MODE
SPI Slave Operating Frequency fSCK 50 MHz
SPI Slave SCK Period tSCK 1/fSCK ns
SCK Input Pulse-Width High/Low tSCH, tSCL tSCK/2
SSx Active to First Shift Edge tSSE 10 ns
MOSI Input to SCK Sample Edge Rise/Fall Setup tSIS 5 ns
MOSI Input from SCK Sample Edge Transition Hold tSIH 1 ns
MISO Output Valid After SCLK Shift Edge Transition tSOV 5 ns
SCK Inactive to SSx Inactive tSSD 10 ns
SSx Inactive Time tSSH 1/fSCK μs
MISO Hold Time After SSx Deassertion tSLH 10 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—I2C

(Timing specifications are guaranteed by design and not production tested.)

STANDARD MODE
Output Fall Time tOF Standard mode, from VIH(MIN) to VIL(MAX) 150 ns
SCL Clock Frequency fSCL 0 100 kHz
Low Period SCL Clock tLOW 4.7 μs
High Time SCL Clock tHIGH 4.0 μs
Setup Time for Repeated Start Condition tSU;STA 4.7 μs
Hold Time for Repeated Start Condition tHD;STA 4.0 μs
Data Setup Time tSU;DAT 300 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and SCL tR 800 ns
Fall Time for SDA and SCL tF 200 ns
Setup Time for a Stop Condition tSU;STO 4.0 μs
Bus Free Time Between a Stop and Start Condition tBUS 4.7 μs
Data Valid Time tVD;DAT 3.45 μs
Data Valid Acknowledge Time tVD;ACK 3.45 μs
FAST MODE
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 150 ns
Pulse Width Suppressed by Input Filter tSP 75 ns
SCL Clock Frequency fSCL 0 400 kHz
Low Period SCL Clock tLOW 1.3 μs
High Time SCL Clock tHIGH 0.6 μs
Setup Time for Repeated Start Condition tSU;STA 0.6 μs
Hold Time for Repeated Start Condition tHD;STA 0.6 μs
Data Setup Time tSU;DAT 125 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and SCL tR 30 ns
Fall Time for SDA and SCL tF 30 ns
Setup Time for a Stop Condition tSU;STO 0.6 μs
Bus Free Time Between a Stop and Start Condition tBUS 1.3 μs
Data Valid Time tVD;DAT 0.9 μs
Data Valid Acknowledge Time tVD;ACK 0.9 μs
FAST MODE PLUS
Output Fall Time tOF From VIH(MIN) to VIL(MAX) 80 ns
Pulse Width Suppressed by Input Filter tSP 75 ns
SCL Clock Frequency fSCL 0 1000 kHz
Low Period SCL Clock tLOW 0.5 μs
High Time SCL Clock tHIGH 0.26 μs
Setup Time for Repeated Start Condition tSU;STA 0.26 μs
Hold Time for Repeated Start Condition tHD;STA 0.26 μs
Data Setup Time tSU;DAT 50 ns
Data Hold Time tHD;DAT 10 ns
Rise Time for SDA and SCL tR 50 ns
Fall Time for SDA and SCL tF 30 ns
Setup Time for a Stop Condition tSU;STO 0.26 μs
Bus Free Time Between a Stop and Start Condition tBUS 0.5
  		μs
Data Valid Time tVD;DAT 0.45 μs
Data Valid Acknowledge Time tVD;ACK 0.45 μs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Electrical Characteristics—I2S

(Timing specifications are guaranteed by design and not production tested.)

Bit Clock Frequency fBCLKS 25 MHz
Bit Clock Period tBCLKS 1/fBCLKS ns
BCLK High Time tWBCLKHS 0.5 1/fBCLKS
BCLK Low Time tWBCLKLS 0.5 1/fBCLKS
LRCLK Setup Time tLRCLK_BCLKS 25 ns
Delay Time, BCLK to SD (Output) Valid tBCLK_SDOS 12 ns
Setup Time for SD (Input) tSU_SDIS 6 ns
Hold Time SD (Input) tHD_SDIS 3 ns
Note 1: Gain error does not include zero-scale errors. It is calculated as (full-scale error – offset error).
Note 2: ppmFS is parts per million of full scale.
Figure 1. SPI Master Mode Timing Diagram
Figure 2. SPI Slave Mode Timing Diagram
 
Figure 3. I2C Timing Diagram
   
Figure 4. I2S Timing Diagram

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