The MAX32675 is a highly integrated, mixed-signal, ultra-low-power microcontroller for industrial applications and is especially suitable for 4-20mA loop-powered sensors and transmitters. It is based on an ultra-low-power Arm Cortex-M4 with FPU and includes 384KB of flash and 160KB of SRAM. ECC, capable of SEC-DED, is implemented over the entire flash, SRAM, and cache to ensure ultra-reliable code execution for demanding applications.
An AFE provides two 12-channel Δ-Σ ADCs with features and specifications that are optimized for precision sensor measurement. Each Δ-Σ ADC can digitize external analog signals as well as system temperature and supplies. A PGA with gains of 1x to 128x precedes each ADC. ADC outputs can be optionally converted on the fly from integer to single-precision floating-point format. A 12-bit DAC is also included. The integrated temperature sensor can be used with the internal sense element or an external diode for temperature compensation of sensor outputs.
The device also includes a trust protection unit (TPU), providing robust security features such as an AES engine, TRNG, and secure boot.
The Arm Cortex-M4 processor with FPU combines high-efficiency signal processing functionality with low power, low cost, and ease of use.
The Arm Cortex-M4 processor with FPU supports single instruction multiple data (SIMD) path DSP extensions, providing:
- Four parallel 8-bit add/sub
- Floating point single precision
- Two parallel 16-bit add/sub
- Two parallel MACs
- 32- or 64-bit accumulate
- Signed, unsigned, data with or without saturation
Multiple clock sources can be selected as the system clock:
- Internal primary oscillator (IPO) at a nominal frequency of 100MHz
- Internal nanoring oscillator at 80kHz
- Internal baud rate oscillator at 7.3728MHz (IBRO)
- External RF oscillator at 16MHz to 32MHz (ERFO) (external crystal required)
The AFE is configured by SPIO and is clocked by the built-in Δ-Σ clock generation or the EXT_CLK signal. The APB clock or the INRO can clock the LPTMR0 in the AOD.
Most general-purpose I/O (GPIO) pins share both a firmware-controlled I/O function and one or more special function signals associated with peripheral modules. Pins can be individually enabled for GPIO or peripheral special function use. Configuring a pin as a special function usually supersedes its use as a firmware-controlled I/O. Though this multiplexing between peripheral and GPIO functions is usually static, it can also be done dynamically. The electrical characteristics of a GPIO pin are identical whether the pin is configured as an I/O or special function, except where explicitly noted in the Electrical Characteristics tables.
In GPIO mode, each pin of a port has an interrupt function that can be independently enabled and configured as a level- or edge-sensitive interrupt. All GPIOs share the same interrupt vector. Some packages do not have all of the GPIOs available.
When configured as GPIOs, the following features are provided. These features can be independently enabled or disabled on a per-pin basis.
- Configurable as input, output, bidirectional, or high-impedance
- Optional internal pullup resistor or internal pulldown resistor when configured as input
- Exit from low-power modes on rising or falling edge
- Selectable standard- or high-drive modes
The MAX32675 provides up to 23 GPIOs.
The PMU provides the optimal mix of high-performance and low-power consumption. It exercises intelligent, precise control of power distribution to the CPU and peripheral circuitry.
The PMU provides the following features:
- User-configurable system clock
- Automatic enabling and disabling of crystal oscillators based on power mode
- Multiple clock domains
- Fast wakeup of powered-down peripherals when activity detected
In this mode, CPU and critical peripheral configuration settings and all volatile memory are preserved.
The device status is as follows:
- CPU is powered down. System state and all SRAM is retained.
- The GPIO pins retain their state.
- The transition from DEEPSLEEP to ACTIVE mode is faster than the transition from BACKUP mode because system initialization is not required.
- The system oscillators are all disabled to provide additional power savings over SLEEP mode.
- LPTMR0 can be active and are optional wake-up sources
This mode corresponds to the Arm Cortex-M4 with FPU DeepSleep mode. The power mode of the AFE is software-controlled.
This mode places the CPU in a static, low-power state. The BACKUP mode supports the same wake-up sources as the DEEPSLEEP mode.
The device status is as follows:
- CPU is powered down.
- SRAM retention as per Table 1. Each of the RAM blocks can be retained.
- LPTMR0 can be active and is an optional wake-up source.
The power mode of the AFE is software-controlled.
| RAM BLOCK | RAM SIZE WITHOUT ECC (KB) | RAM SIZE WITH ECC (KB) |
| SYSRAM0 | 20 | 16 |
| SYSRAM1 | 20 | 16 |
| SYSRAM2 | 40 | 32 |
| SYSRAM3 | 80 | 64 |
The device status is as follows:
- CPU is powered off.
- All peripherals are powered off.
- Wake-up from GPIO interrupt.
- No SRAM retention.
The power mode of the AFE is software-controlled.
The standard direct memory access (DMA) controller provides a means to offload the CPU for memory/peripheral data transfer leading to a more power-efficient system. It allows automatic one-way data transfer between two entities. These entities can be either memories or peripherals. The transfers are done without using CPU resources. The following transfer modes are supported:
- 8 channel
- Peripheral to data memory
- Data memory to peripheral
- Data memory to data memory
- Event support
All DMA transactions consist of an AHB burst read into the DMA FIFO followed immediately by an AHB burst write from the FIFO.
Microcontrollers are often used in harsh environments where electrical noise and electromagnetic interference (EMI) are abundant. Without proper safeguards, these hazards can disturb device operation and corrupt program execution. One of the most effective countermeasures is the windowed watchdog timer (WDT), which detects runaway code or system unresponsiveness.
The WDT is a 32-bit, free-running counter with a configurable prescaler. When enabled, the WDT must be periodically reset by the application software. Failure to reset the WDT within the user-configurable timeout period indicates that the application software is not operating correctly and results in a WDT timeout. A WDT timeout can trigger an interrupt, system reset, or both. Either response forces the instruction pointer to a known good location before resuming instruction execution. The windowed timeout period feature provides more detailed monitoring of system operation, requiring the WDT to be reset within a specific window of time.
The WDT supports multiple clock option:
- 100MHz IPO
- 16MHz to 32MHz ERFO (external crystal required)
- 7.3728MHz IBRO
- 80kHz INRO
- PCLK
The MAX32675 provides two instances of the windowed watchdog timer (WDT0, WDT1).
General-purpose, 32-bit timers provide timing, capture/compare, or generate pulse-width modulated (PWM) signals with minimal software interaction.
The timers provide the following features:
- 32-bit up/down auto-reload
- Programmable prescaler
- PWM output generation
- Capture, compare, and capture/compare capability
- External pin multiplexed with GPIO for timer input, clock gating, or capture
- Timer output pin
- TMR0–TMR3 can be configured as 2 × 16-bit general-purpose timers
- Timer interrupt
The MAX32675 provides timer instances as shown in Table 2. LPTMRx is capable of operation in the Low Power, SLEEP, DEEPSLEEP, and BACKUP modes.
I/O functionality is supported for all of the timers. Note that the function of a port can be multiplexed with other functions on the GPIO pins, so it might not be possible to use all the ports depending on the device configuration.
| INSTANCE | SINGLE 32 BIT |
DUAL 16 BIT |
POWER MODE | CLOCK SOURCE | ||||||
| AOD_PCLK | PCLK | IBRO | ERFO | INRO | ||||||
| TMR0 | Yes | Yes | ACTIVE SLEEP |
No | Yes | Yes | Yes | No | ||
| TMR1 | Yes | Yes | ACTIVE SLEEP |
No | Yes | Yes | Yes | No | ||
| TMR2 | Yes | Yes | ACTIVE SLEEP |
No | Yes | Yes | Yes | No | ||
| TMR3 | Yes | Yes | ACTIVE SLEEP |
No | Yes | Yes | Yes | No | ||
| LPTMR0 | Yes | No | ACTIVE SLEEP |
Yes | No | No | No | Yes | ||
| DEEPSLEEP BACKUP |
No | |||||||||
The I2C interface is a bidirectional, two-wire serial bus that provides a medium-speed communications network. It can operate as a one-to-one, one-to-many, or many-to-many communications medium. These engines support standard-mode, fast-mode, fast-mode plus, and high-speed mode I2C speeds. It provides the following features:
- Master or slave mode operation
- Supports up to four different slave addresses in slave mode
- Supports standard 7-bit addressing or 10-bit addressing
- RESTART condition
- Interactive receive mode
- Transmit FIFO preloading
- Support for clock stretching to allow slower slave devices to operate on higher speed busses
- Multiple transfer rates
- Standard mode: 100kbps
- Fast mode: 400kbps
- Fast mode plus: 1000kbps
- High-speed mode: 3400kbps
- Internal filter to reject noise spikes
- Receiver FIFO depth of 8 bytes
- Transmitter FIFO depth of 8 bytes
The MAX32675 provides I2C instances as shown in Table 3.
| INSTANCE |
| I2C0, I2C2 |
The serial peripheral interface (SPI) is a highly configurable, flexible, and efficient synchronous interface among multiple SPI devices on a single bus. The bus uses a single clock signal and multiple data signals and one or more slave select lines to address only the intended target device. The SPI operates independently and requires minimal processor overhead.
The provided SPI peripherals can operate in either slave or master mode and provide the following features:
- SPI modes 0, 1, 2, 3 for single-bit communication
- 3- or 4-wire mode for single-bit slave device communication
- Full-duplex operation in single-bit, 4-wire mode
- Multimaster mode fault detection
- Programmable interface timing
- Programmable SCK frequency and duty cycle
- 32-byte transmit and receive FIFOs
- Slave select assertion and de-assertion timing with respect to leading/trailing SCK edge
The MAX32675 provides SPI instances as shown in Table 4.
| INSTANCE | DATA | SLAVE SELECT LINES | MAXIMUM FREQUENCY MASTER MODE (MHz) | MAXIMUM FREQUENCY SLAVE MODE (MHz) |
| SPI1 | 3 wire, 4 wire | 1 | 50 | 50 |
The I2S interface is a bidirectional, four-wire serial bus that provides serial communications for codecs and audio amplifiers compliant with the I2S Bus Specification, June 5, 1996. It provides the following features:
- Master and slave mode operation
- Support for 4 channels
- 8, 16, 24, and 32 bit frames
- Receive and transmit DMA support
- Wakeup on FIFO status (full/empty/threshold)
- Pulse density modulation support for receive channel
- Word-select polarity control
- First bit position selection
- Interrupts generated for FIFO status
- Receiver FIFO depth of 32 bytes
- Transmitter FIFO depth of 32 bytes
The MAX32675 provides one instance of the I2S peripheral (I2S0).
The universal asynchronous receiver-transmitter (UART) interface supports full-duplex asynchronous communication with optional hardware flow control (HFC) modes to prevent data overruns. If HFC mode is enabled on a given port, the system uses two extra pins to implement the industry-standard request to send (RTS) and clear to send (CTS) flow control signaling. Each instance is individually programmable.
- 2-wire interface or 4-wire interface with flow control
- 8-byte send/receive FIFO
- Full-duplex operation for asynchronous data transfers
- Interrupts available for frame error, parity error, CTS, Rx FIFO overrun, and FIFO full/partially full conditions
- Automatic parity and frame error detection
- Independent baud-rate generator
- Programmable 9th-bit parity support
- Multidrop support
- Start/stop bit support
- Hardware flow control using RTS/CTS
- Two DMA channels can be connected (read and write FIFOs)
- Programmable word size (5 bits to 8 bits)
The MAX32675 provides UART instances as shown in Table 5.
| INSTANCE | POWER MODE | CLOCK SOURCE | |||||
| AOD_PCLK | PCLK | IBRO | ERFO | INRO | |||
| UART0, UART2 | ACTIVE | No | Yes | Yes | Yes | No | |
A low-power, multichannel, 24-bit Δ-Σ ADC has features and specifications optimized for the precision measurement of sensors and other analog signal sources. The architecture includes a low-noise programmable gain amplifier (PGA), low-power input buffers, programmable matched current sources, differential/single-ended input multiplexer, and integrated on-chip oscillator.
- PGA with Available Gains 1x to 128x
- Very High Input Impedance
- Optimizes Overall Dynamic Range
- Low-Power Input Buffers
- Provide Input Isolation
- Selectable Reference
- Internal Differential (VREF)
- External Differential
- Programmable Current Sources
- Bias for Resistive Sensors
- 16 Current Levels Available
- Detection of Broken Sensor Wires
- 12 Analog Inputs
- 6 Differential or 12 Single Ended
- Sample Rates up to 61440 Samples per Second
- FIR Digital Filters
- Provides Single-Cycle Settling in 16ms
- 90dB of Noise Rejection at 50Hz and 60Hz
- On-Chip Clock Source
- No External Components Required
- External Clock Capable
- Sample Ready Interrupts
- ADC0_RDY and ADC1_RDY
The MAX32675 provides two instances of this ADC (ADC_ZERO, ADC_ONE) that share the multiplexed 12 analog inputs (AIN0–AIN11).
The 12-bit digital-to-analog (DAC) outputs a single-ended voltage. It can be set independently to generate either a static output voltage or to generate a series of preloaded sample outputs at a specified sample rate.
The 12-Bit DAC peripheral support the following features:
- Configurable clock rate and output sample rate.
- Selectable output voltage reference.
- Can be set to output a static voltage level, a preset number of samples at a configurable sample rate, or samples continuously at a configurable sample rate.
- Interpolation filter allows for linearly interpolated output samples to be generated between each pair of output samples (2 to 1, 4 to 1, or 8 to 1).
- DAC output samples are pulled from a FIFO allow continuous sample output generation.
The dedicated hardware-based AES engine supports the following algorithms:
- AES-128
- AES-192
- AES-256
The AES keys are automatically generated by the engine and stored in a dedicated flash to protect against tampering. Key generation and storage are transparent to the user.
Random numbers are a vital part of a secure application. The TRNG provides random numbers for use as cryptographic seeds or strong encryption keys to ensure data privacy.
Software can use random numbers to trigger asynchronous events that result in nondeterministic behavior. This helps thwart replay attacks or key search approaches. A high-entropy source must continuously update an effective true random number generator (TRNG).
A physically unpredictable entropy source continuously drives the provided TRNG. It generates a 128-bit true random number in 128 system clock cycles.
The TRNG can support the system-level validation of many security standards such as FIPS 140-2, PCI-PED, and Common Criteria. Contact Maxim for details of compliance with specific standards.
A cyclic redundancy check (CRC) hardware module provides fast calculations and data integrity checks by application software. The CRC module supports the following polynomials:
- CRC-16-CCITT
- CRC-32 (X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1)
The bootloader allows loading and verification of program memory through a serial interface. Features include:
- Bootloader interface through UART
- Program loading of Motorola™ SREC format files
- Permanent lock state prevents altering or erasing program memory
- Access to the USN for device or customer application identification
- Disable SWD interface to block debug access port functionality
The serial wire debug interface is used for code loading and ICE debug activities. All devices in mass production have the debugging/development interface enabled.