Features
Benefits and Features
- High-Efficiency Microcontroller for Low-Power High-Reliability Devices
- Arm Cortex-M4 Processor with FPU up to 100MHz
- 1MB Dual-Bank Flash with Error Correction
- 200KB SRAM (160KB with ECC Enabled), Optionally Preserved in Lowest Power Modes
- EEPROM Emulation on Flash
- 16KB Unified Cache with ECC
- Resource Protection Unit (RPU) and Memory Protection Unit (MPU)
- Dual- or Single-Supply Operation, 1.7V to 3.6V
- Wide Operating Temperature: -40°C to +105°C
- Flexible Clocking Schemes
- Internal High-Speed 100MHz Oscillator
- Internal Low-Power 7.3728MHz and Ultra-Low-Power 80kHz Oscillators
- 16MHz–32MHz Oscillator, 32.768kHz Oscillator (External Crystal Required)
- External Clock Input for CPU, LPUART, LPTIMER
- Power Management Maximizes Uptime for Battery Applications
- 53.2μA/MHz ACTIVE at 0.9V up to 12MHz (CoreMark®)
- 61.5μA/MHz ACTIVE at 1.1V up to 100MHz
- 2.94μA Full Memory Retention Power in BACKUP Mode at VDD = 1.8V
- 350nA Ultra-Low-Power RTC at VDD = 1.8V
- Wake from LPUART or LPTMR
- Optimal Peripheral Mix Provides Platform Scalability
- Up to 42 General-Purpose I/O Pins
- Up to Three SPI Master/Slave (up to 50Mbps)
- Up to Three 4-Wire UART
- Up to Three I2C Master/Slave 3.4Mbps High Speed
- Up to Four 32-Bit Timers (TMR)
- Up to Two Low-Power 32-Bit Timers (LPTMR)
- One I2S Master/Slave for Digital Audio Interface
- One 12-Channel, 12-Bit, 1Msps SAR ADC with On-Die Temperature Sensor
- Security and Integrity
- Available ECDSA-Based Cryptographic Secure Bootloader in ROM
- Secure Loader Interface over UART
- AES-128/192/256 Hardware Acceleration Engine
- TRNG Compliant to SP800-90B