Pin Specifications

Pin Configuration 40 TQFN

Pin Description

PIN	NAME	FUNCTION MODE					FUNCTION
		Primary Signal (Default)	Alternate Function 1	Alternate Function 2	Alternate Function 3	Alternate Function 4
POWER AND SYSTEM PINS
2	VCORE	—	—	—	—	—	Digital Supply Voltage. Bypass with 1.0μF to VSS.
34	VREG1	—	—	—	—	—	Bypass with 4.7nF to VSS. Do not connect this device pin to any other external circuitry.
39	VDD	—	—	—	—	—	GPIO Supply Voltage. Bypass with 4.7μF to VSS.
EP, 38	VSS	—	—	—	—	—	Digital Ground. Exposed pad (TQFN only). This pad must be connected to VSS. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
33	VREF	—	—	—	—	—	ADC External Reference Input. This is the reference input for the ADC. Bypass with 1.0μF to VSS.
31	VDDA	—	—	—	—	—	Analog Supply Voltage. This pin must always be connected to the VDD device pin at the PCB level. Bypass this pin to VSSA with 1.0μF as close as possible to the package.
32	VSSA	—	—	—	—	—	Analog Ground
35	RSTN	—	—	—	—	—	Hardware Power Reset (Active-Low) Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR reset (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. This pin has an internal pullup to the VDDIO supply.
CLOCK PINS
40	32KOUT	—	—	—	—	—	32kHz Crystal Oscillator Output. Refer to the MAX32672 User Guide for determination of the required external stability capacitors.
1	32KIN	—	—	—	—	—	32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Refer to the MAX32672 User Guide for determination of the required external stability capacitors. Optionally, this pin can be configured as the input for an external CMOS-level clock source.
36	HFXIN	—	—	—	—	—	RF Crystal Oscillator Input. Connect the crystal between HFXIN and HFXOUT. Optionally, this pin can be configured as the input for an external square-wave source. See the Electrical Characteristics table for details of the crystal requirements. Refer to the MAX32672 User Guide for determination of the required external stability capacitors.
37	HFXOUT	—	—	—	—	—	RF Crystal Oscillator Output. Connect the crystal between HFXIN and HFXOUT. See the Electrical Characteristics table for details of the crystal requirements. Refer to the MAX32672 User Guide for determination of the required external stability capacitors.
GPIO AND ALTERNATE FUNCTION
4	P0.0	P0.0	SWDIO	—	TMR0C_IA	—	Single-Wire Debug I/O; Timer0 Port Map C Input 32 Bits or Lower 16 Bits
5	P0.1	P0.1	SWDCLK	—	TMR0C_OA	—	Single-Wire Debug Clock; Timer0 Port Map C Output 32 Bits or Lower 16 Bits
6	P0.2	P0.2	SPI0A_MISO	UART1B_RX	TMR1C_IA	—	SPI0 Master In Slave Out; UART1 Port Map B RX; Timer1 Port Map C Input 32 Bits or Lower 16 Bits
7	P0.3	P0.3	SPI0A_MOSI	UART1B_TX	TMR1C_OA	—	SPI0 Master Out Slave In; UART1 Port Map B Tx; Timer1 Port Map C Output 32 Bits or Lower 16 Bits
8	P0.4	P0.4	SPI0A_SCK	UART1B_CTS	TMR2C_IA	—	SPI0 Serial Clock; UART1 Port Map B CTS; Timer2 Port Map C Input 32 Bits or Lower 16 Bits
9	P0.5	P0.5	SPI0A_SS0	UART1B_RTS	TMR2C_OA	HFX_CLK_OUT	SPI0 Slave Select 0; UART1 Port Map B RTS; Timer2 Port Map C Output; ERFO Buffered Output 32 Bits or Lower 16 Bits
10	P0.6	P0.6	I2C0A_SCL	LPTMR0B_IA	SPI0C_SS1	QEA	I2C0 Serial Clock; Low-Power Timer0 Port Map A Input 32 Bits or Lower 16 Bits; SPI0 Slave Select 1; Quadrature Decoder Phase A Input
11	P0.7	P0.7	I2C0A_SDA	LPTMR0B_OA	SPI0C_SS2	QEB	I2C0 Serial Data; Low-Power Timer0 Port Map A Output 32 Bits or Lower 16 Bits; SPI0 Slave Select 2; Quadrature Decoder Phase B Input
19	P0.8	P0.8	UART0A_RX	I2S0A_SDO	TMR0C_IA	AIN0/AIN_C0_N/AIN_C1_N	UART0 Port Map A Rx; I2S0 Serial Data Output; Timer0 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Negative Input
20	P0.9	P0.9	UART0A_TX	I2S0A_LRCLK	TMR0C_OA	AIN1/AIN_C0_N/AIN_C1_N	UART0 Port Map A Tx; I2S0 Left/Right Clock; Timer0 Port Map C Output 32 Bits or Lower 16 Bits; Comparator Negative Input
21	P0.10	P0.10	UART0A_CTS	I2S0A_BCLK	TMR1C_IA	AIN2/AIN_C0_N/AIN_C1_N	UART0 Port Map A CTS; I2S0 Bit Clock; Timer Port Map C Input 32 Bits or Lower 16 Bits; Comparator Negative Input
22	P0.11	P0.11	UART0A_RTS	I2S0A_SDI	TMR1C_OA	AIN3/AIN_C0_N/AIN_C1_N	UART0 Port Map A RTS; I2S0 Serial Data Input; Timer1 Port Map C Output 32 Bits or Lower 16 Bits; Comparator Negative Input
23	P0.12	P0.12	I2C1A_SCL	EXT_CLK2	TMR2C_IA	AIN4/AIN_C0_P/AIN_C1_P	I2C1 Serial Clock; Low-Power External Clock Input; Timer2 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Positive Input
24	P0.13	P0.13	I2C1A_SDA	32KCAL	TMR2C_OA	AIN5/AIN_C0_P/AIN_C1_P	I2C1 Serial Data; 32.768kHz Calibration Output; Timer2 Port Map C Output 32 Bits or Lower 16 Bits; Comparator Positive Input
25	P0.14	P0.14	SPI1A_MISO	UART2B_RX	TMR3C_IA	AIN6/AIN_C0_P/AIN_C1_P	SPI1 Master In Slave Out; UART2 Port Map B Rx; Timer3 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Positive Input
26	P0.15	P0.15	SPI1A_MOSI	UART2B_TX	TMR3C_OA	AIN7/AIN_C0_P/AIN_C1_P	SPI1 Master Out Slave In; UART2 Port Map B Tx; Timer3 Port Map C Output 32 Bits or Lower 16 Bits; ADC Input 7/Comparator Positive Input
27	P0.16	P0.16	SPI1A_SCK	UART2B_CTS	TMR0C_IA	AIN8	SPI1 Serial Clock; UART2 Port Map B CTS; Timer0 Port Map C Input 32 Bits or Lower 16 Bits; ADC Input 8
28	P0.17	P0.17	SPI1A_SS0	UART2B_RTS	TMR0C_OA	AIN9	SPI1 Slave Select 0; UART2 Port Map B RTS; Timer0 Port Map C Output 32 Bits or Lower 16 Bits; ADC Input 9
29	P0.18	P0.18	I2C2A_SCL	—	TMR1C_IA	AIN10	I2C2 Serial Clock; Timer1 Port Map C Input 32 Bits or Lower 16 Bits; ADC Input 10
30	P0.19	P0.19	I2C2A_SDA	—	TMR1C_OA	AIN11	I2C2 Serial Data; Timer1 Port Map C Output 32 Bits or Lower 16 Bits; ADC Input 11
3	P0.22	P0.22	LPTMR1A_IA	ADC_TRIG_B	TMR0C_IA	—	Low-Power Timer1 Port Map A Input; ADC Trigger Port Map B; Timer0 Port Map C Input 32 Bits or Lower 16 Bits
12	P0.23	P0.23	LPTMR1A_OA	—	SPI0C_SS3	QEI	Low-Power Timer1 Port Map A Output; SPI0 Slave Select 3; Quadrature Decoder Index Input
13	P0.24	P0.24	LPUART0A_CTS	UART0B_RX	I2S0A_SD0	QES	Low-Power UART0 CTS; UART0 Port Map B Rx; I2S0 Serial Data Output; Quadrature Decoder Capture Input
14	P0.25	P0.25	LPUART0A_RTS	UART0B_TX	I2S0A_LRCLK	QMATCH	Low-Power UART0 RTS; UART0 Port Map B Tx; I2S0 Left/Right Clock; Quadrature Decoder Match Output
15	P0.26	P0.26	LPUART0A_RX	UART0B_CTS	I2S0C_BCLK	QDIR	Low-Power UART0 Rx; UART0 Port Map B CTS; I2S0 Bit Clock; Quadrature Decoder Direction Output
16	P0.27	P0.27	LPUART0A_TX	UART0B_RTS	I2S0C_SDI	QERR	Low-Power UART0 Port Map A Tx; UART0 Port Map B Request to Send; I2S 0 Port Map C Serial Data Input; Quadrature Decoder Error Output
17	P0.28	P0.28	UART1A_RX	EXT_CLK1	TMR3C_IA	—	UART1 Port Map A Receive; Timer3 Port Map C Input 32 Bits or Lower 16 Bits; External Clock Input
18	P0.29	P0.29	UART1A_TX	SPI1_SS0	TMR3C_OA	ADC_TRIG_D	UART1 Port Map A Transmit; SPI1 Port Map B Slave Select 0; Timer3  Port Map C Output 32 Bits or Lower 16 Bits; ADC Trigger Port Map D

Pin Configuration 56 TQFN

Pin Description

PIN	NAME	FUNCTION MODE					FUNCTION
		Primary Signal (Default)	Alternate Function 1	Alternate Function 2	Alternate Function 3	Alternate Function 4
POWER AND SYSTEM PINS
56	VCORE	—	—	—	—	—	Digital Supply Voltage. Bypass with 1.0μF to VSS.
48	VREG1	—	—	—	—	—	Bypass with 4.7nF to VSS. Do not connect this device pin to any other external circuitry.
14, 53	VDD	—	—	—	—	—	GPIO Supply Voltage. Bypass with 4.7μF to VSS.
EP, 27, 52	VSS	—	—	—	—	—	Digital Ground. Exposed pad (TQFN only). This pad must be connected to VSS. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
47	VREF	—	—	—	—	—	ADC External Reference Input. This is the reference input for the ADC converter. Bypass with 1.0μF to VSS.
45	VDDA	—	—	—	—	—	Analog Supply Voltage. This pin must always be connected to the VDD device pin at the PCB level. Bypass this pin to VSSA with 1.0μF as close as possible to the package.
46	VSSA	—	—	—	—	—	Analog Ground
49	RSTN	—	—	—	—	—	Hardware Power Reset (Active-Low) Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR reset (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. This pin has an internal pullup to the VDDIO supply.
CLOCK PINS
54	32KOUT	—	—	—	—	—	32kHz Crystal Oscillator Output. Refer to the MAX32672 User Guide for determination of the required external stability capacitors.
55	32KIN	—	—	—	—	—	32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Refer to the MAX32672 User Guide for determination of the required external stability capacitors Optionally, this pin can be configured as the input for an external CMOS-level clock source.
50	HFXIN	—	—	—	—	—	RF Crystal Oscillator Input. Connect the crystal between HFXIN and HFXOUT. Optionally, this pin can be configured as the input for an external square wave source. See the Electrical Characteristics table for details of the crystal requirements. Refer to the MAX32672 User Guide for determination of the required external stability capacitors.
51	HFXOUT	—	—	—	—	—	RF Crystal Oscillator Output. Connect the crystal between HFXIN and HFXOUT. See Electrical Characteristics for details of the crystal requirements. Refer to the MAX32672 User Guide for determination of the required external stability capacitors
GPIO AND ALTERNATE FUNCTION
6	P0.0	P0.0	SWDIO	—	TMR0C_IA	—	Single-Wire Debug I/O; Timer0 Port Map C Input 32 Bits or Lower 16 Bits
7	P0.1	P0.1	SWDCLK	—	TMR0C_OA	—	Single-Wire Debug Clock; Timer0 Port Map C Output 32 Bits or Lower 16 Bits
8	P0.2	P0.2	SPI0A_MISO	UART1B_RX	TMR1C_IA	—	SPI0 Port Map A Master In Slave Out; UART1 Port Map B Rx; Timer1 Port Map C Input 32 Bits or Lower 16 Bits
9	P0.3	P0.3	SPI0A_MOSI	UART1B_TX	TMR1C_OA	—	SPI0 Master Out Slave In; UART1 Port Map B Tx; Timer1 Port Map C Output 32 Bits or Lower 16 Bits
10	P0.4	P0.4	SPI0A_SCK	UART1B_CTS	TMR2C_IA	—	SPI0 Serial Clock; UART1 Port Map B CTS; Timer2 Port Map C Input 32 Bits or Lower 16 Bits
11	P0.5	P0.5	SPI0A_SS0	UART1B_RTS	TMR2C_OA	HFX_CLK_OUT	SPI0 Slave Select 0; UART1 Port Map B RTS; Timer2 Port Map C Output 32 Bits or Lower 16 Bits; ERFO Buffered Output
12	P0.6	P0.6	I2C0A_SCL	LPTMR0B_IA	SPI0C_SS1	QEA	I2C0 Serial Clock; Low-Power Timer0 Port Map A Input 32 Bits or Lower 16 Bits; SPI0 Slave Select 1; Quadrature Decoder Phase A Input
13	P0.7	P0.7	I2C0A_SDA	LPTMR0B_OA	SPI0C_SS2	QEB	I2C0 Serial Data; Low-Power Timer0 Port Map A Output 32 Bits or Lower 16 Bits; SPI0 Slave Select 2; Quadrature Decoder Phase B Input
28	P0.8	P0.8	UART0A_RX	I2S0A_SDO	TMR0C_IA	AIN0/AIN_C0_N/AIN_C1_N	UART0 Port Map A Rx; I2S0 Serial Data Output; Timer0 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Negative Input
29	P0.9	P0.9	UART0A_TX	I2S0A_LRCLK	TMR0C_OA	AIN1/AIN_C0_N/AIN_C1_N	UART0 Port Map A Tx; I2S0 Left/Right Clock; Timer0 Port Map C Output 32 Bits or Lower 16 Bits; Comparator Negative Input
30	P0.10	P0.10	UART0A_CTS	I2S0A_BCLK	TMR1C_IA	AIN2/AIN_C0_N/AIN_C1_N	UART0 Port Map A CTS; I2S0 Bit Clock; Timer1 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Negative Input
31	P0.11	P0.11	UART0A_RTS	I2S0A_SDI	TMR1C_OA	AIN3/AIN_C0_N/AIN_C1_N	UART0 Port Map A RTS; I2S0 Serial Data Input; Timer1 Port Map C Output 32 Bits or Lower 16 Bits; Comparator Negative Input
32	P0.12	P0.12	I2C1A_SCL	EXT_CLK2	TMR2C_IA	AIN4/AIN_C0_P/AIN_C1_P	I2C1 Serial Clock; Low-Power External Clock Input; Timer2 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Positive Input
33	P0.13	P0.13	I2C1A_SDA	32KCAL	TMR2C_OA	AIN5/AIN_C0_P/AIN_C1_P	I2C1 Serial Data; 32.768kHz Calibration Output; Timer2 Port Map C Output 32 Bits or Lower 16 Bits; Comparator Positive Input
34	P0.14	P0.14	SPI1A_MISO	UART2B_RX	TMR3C_IA	AIN6/AIN_C0_P/AIN_C1_P	SPI1 Master In Slave Out; UART2 Port Map B Rx; Timer3 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Positive Input
35	P0.15	P0.15	SPI1A_MOSI	UART2B_TX	TMR3C_OA	AIN7/AIN_C0_P/AIN_C1_P	SPI1 Master Out Slave In; UART2 Port Map B Tx; Timer3 Port Map C Output 32 Bits or Lower 16 Bits; ADC Input 7/Comparator Positive Input
36	P0.16	P0.16	SPI1A_SCK	UART2B_CTS	TMR0C_IA	AIN8	SPI1 Serial Clock; UART2 Port Map B CTS; Timer0 Port Map C Input 32 Bits or Lower 16 Bits; ADC Input 8
41	P0.17	P0.17	SPI1A_SS0	UART2B_RTS	TMR0C_OA	AIN9	SPI1 Slave Select 0; UART2 Port Map B RTS; Timer0 Port Map C Output 32 Bits or Lower 16 Bits; ADC Input 9
42	P0.18	P0.18	I2C2A_SCL	—	TMR1C_IA	AIN10	I2C2 Serial Clock; Timer1 Port Map C Input 32 Bits or Lower 16 Bits; ADC Input 10
43	P0.19	P0.19	I2C2A_SDA	—	TMR1C_OA	AIN11	I2C2 Serial Data; Timer1 Port Map C Output 32 Bits or Lower 16 Bits; ADC Input 11
1	P0.20	P0.20	CM4_RX	—	TMR2C_IA	—	CM4 Rx Event Input; Timer2 Port Map C Input 32 Bits or Lower 16 Bits
2	P0.21	P0.21	CM4_TX	—	TMR2C_OA	—	CM4 Tx Event Output; Timer2 Port Map C Output 32 Bits or Lower 16 Bits
3	P0.22	P0.22	LPTMR1A_IA	ADC_TRIG_B	TMR0C_IA	—	Low-Power Timer1 Port Map A Input; ADC Trigger Port Map B; Timer0 Port Map C Input 32 Bits or Lower 16 Bits
15	P0.23	P0.23	LPTMR1A_OA	—	SPI0C_SS3	QEI	Low-Power Timer1 Port Map A Output; SPI0 Slave Select 3; Quadrature Decoder Index Input
16	P0.24	P0.24	LPUART0A_CTS	UART0B_RX	I2S0A_SD0	QES	Low-Power UART0 CTS; UART0 Port Map B Rx; I2S0 Serial Data Output; Quadrature Decoder Capture Input
17	P0.25	P0.25	LPUART0A_RTS	UART0B_TX	I2S0A_LRCLK	QMATCH	Low-Power UART0 RTS; UART0 Port Map B Tx; I2S0 Left/Right Clock; Quadrature Decoder Match Output
18	P0.26	P0.26	LPUART0A_RX	UART0B_CTS	I2S0C_BCLK	QDIR	Low-Power UART0 Rx; UART0 Port Map B CTS; I2S0 Bit Clock; Quadrature Decoder Direction Output
23	P0.27	P0.27	LPUART0A_TX	UART0B_RTS	I2S0C_SDI	QERR	Low-Power UART0 Port Map A Tx; UART0 Port Map B Request to Send; I2S0 Port Map C Serial Data Input; Quadrature Decoder Error Output
24	P0.28	P0.28	UART1A_RX	EXT_CLK1	TMR3C_IA	—	UART1 Port Map A Receive; Timer3 Port Map C Input 32 Bits or Lower 16 Bits; External Clock Input
25	P0.29	P0.29	UART1A_TX	SPI1_SS0	TMR3C_OA	ADC_TRIG_D	UART1 Port Map A Transmit; SPI1 Port Map B Slave Select 0;Timer3 Port Map C Output 32 Bits or Lower 16 Bits; ADC Trigger Port Map D
26	P0.30	P0.30	UART1A_CTS	—	TMR3C_IA	—	UART1 Port Map A Clear to Send; Timer3 Port Map C Input 32 Bits or Lower 16 Bits
44	P0.31	P0.31	UART1A_RTS	—	TMR3C_OA	—	UART1 Port Map A Request to Send; Timer3 Port Map C Output 32 Bits or Lower 16 Bits
4	P1.0	P1.0	—	—	TMR1C_IA	—	Timer1 Port Map C Input 32 Bits or Lower 16 Bits
20	P1.1	P1.1	SPI2A_MISO	UART0B_RX	TMR3C_OA	—	SPI2 Port Map A Master In Slave Out; UART0 Port Map B Receive; Timer3 Port Map C Output 32 Bits or Lower 16 Bits
19	P1.2	P1.2	SPI2A_MOSI	UART0B_TX	TMR3C_IA	DIV_CLK_OUT	SPI2 Port Map A Master Out Slave In; UART0 Port Map B Transmit; Timer3 Port Map C Input 32 Bits or Lower 16 Bits; Divided_Clock_Output
22	P1.3	P1.3	SPI2A_SCK	UART0B_CTS	—	—	SPI2 Port Map A Serial Clock; UART0 Port Map B Clear to Send
21	P1.4	P1.4	SPI2A_SS0	UART0B_RTS	TMR0C_OA	ADC_TRIG_D	SPI2 Port Map A Slave Select 0; UART0 Port Map B Request to Send; Timer0 Port Map C Output 32 Bits or Lower 16 Bits; ADC Trigger Port Map D
37	P1.5	P1.5	UART2A_RX	—	—	—	UART2 Port Map A Receive
38	P1.6	P1.6	UART2A_TX	—	—	—	UART2 Port Map A Transmit
39	P1.7	P1.7	UART2A_CTS	—	—	—	UART2 Port Map A Clear to Send
40	P1.8	P1.8	UART2A_RTS	—	—	—	UART2 Port Map A Request to Send
5	P1.9	P1.9	—	—	TMR1C_OA	—	Timer1 Port Map C Output 32 Bits or Lower 16 Bits