Package Information

40 TQFN-EP

Package Code	T4055+1
Outline Number	21-0140
Land Pattern Number	90-0016
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ_JA)	45°C/W
Junction to Case (θ_JC)	2°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ_JA)	28°C/W
Junction to Case (θ_JC)	2°C/W

56 TQFN-EP

Package Code	T5677+1
Outline Number	21-0144
Land Pattern Number	90-0042
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ_JA)	36°C/W
Junction to Case (θ_JC)	1°C/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ_JA)	25°C/W
Junction to Case (θ_JC)	1°C/W

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

data-opMAX32672GTNBL%2BT

data-opMAX32672GTNBL%2B

data-opMAX32672GTL%2B

data-opMAX32672GTL%2BT

data-opMAX32672GTLBL%2BT

data-opMAX32672GTLBL%2B

Digital Supply Voltage. Bypass with 1.0μF to VSS.Bypass with 4.7nF to VSS. Do not connect this device pin to any other external circuitry.GPIO Supply Voltage. Bypass with 4.7μF to VSS.Digital Ground. Exposed pad (TQFN only). This pad must be connected to VSS. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.ADC External Reference Input. This is the reference input for the ADC converter. Bypass with 1.0μF to VSS.Analog Supply Voltage. This pin must always be connected to the VDD device pin at the PCB level. Bypass this pin to VSSA with 1.0μF as close as possible to the package.Analog GroundHardware Power Reset (Active-Low) Input. The device remains in reset while this pin is in its active state. When the pin transitions to its inactive state, the device performs a POR reset (resetting all logic on all supplies except for real-time clock circuitry) and begins execution. This pin has an internal pullup to the VDDIO supply.32kHz Crystal Oscillator Output. Refer to the MAX32672 User Guide for determination of the required external stability capacitors.32kHz Crystal Oscillator Input. Connect a 32kHz crystal between 32KIN and 32KOUT for RTC operation. Refer to the MAX32672 User Guide for determination of the required external stability capacitors Optionally, this pin can be configured as the input for an external CMOS-level clock source.RF Crystal Oscillator Input. Connect the crystal between HFXIN and HFXOUT. Optionally, this pin can be configured as the input for an external square wave source. See the Electrical Characteristics table for details of the crystal requirements. Refer to the MAX32672 User Guide for determination of the required external stability capacitors.RF Crystal Oscillator Output. Connect the crystal between HFXIN and HFXOUT. See Electrical Characteristics for details of the crystal requirements. Refer to the MAX32672 User Guide for determination of the required external stability capacitorsSingle-Wire Debug I/O; Timer0 Port Map C Input 32 Bits or Lower 16 BitsSingle-Wire Debug Clock; Timer0 Port Map C Output 32 Bits or Lower 16 BitsSPI0 Port Map A Master In Slave Out; UART1 Port Map B Rx; Timer1 Port Map C Input 32 Bits or Lower 16 BitsSPI0 Master Out Slave In; UART1 Port Map B Tx; Timer1 Port Map C Output 32 Bits or Lower 16 BitsSPI0 Serial Clock; UART1 Port Map B CTS; Timer2 Port Map C Input 32 Bits or Lower 16 BitsSPI0 Slave Select 0; UART1 Port Map B RTS; Timer2 Port Map C Output 32 Bits or Lower 16 Bits; ERFO Buffered Output I2C0 Serial Clock; Low-Power Timer0 Port Map A Input 32 Bits or Lower 16 Bits; SPI0 Slave Select 1; Quadrature Decoder Phase A InputI2C0 Serial Data; Low-Power Timer0 Port Map A Output 32 Bits or Lower 16 Bits; SPI0 Slave Select 2; Quadrature Decoder Phase B InputUART0 Port Map A Rx; I2S0 Serial Data Output; Timer0 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Negative InputUART0 Port Map A Tx; I2S0 Left/Right Clock; Timer0 Port Map C Output 32 Bits or Lower 16 Bits; Comparator Negative Input UART0 Port Map A CTS; I2S0 Bit Clock; Timer1 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Negative InputUART0 Port Map A RTS; I2S0 Serial Data Input; Timer1 Port Map C Output 32 Bits or Lower 16 Bits; Comparator Negative InputI2C1 Serial Clock; Low-Power External Clock Input; Timer2 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Positive Input I2C1 Serial Data; 32.768kHz Calibration Output; Timer2 Port Map C Output 32 Bits or Lower 16 Bits; Comparator Positive Input SPI1 Master In Slave Out; UART2 Port Map B Rx; Timer3 Port Map C Input 32 Bits or Lower 16 Bits; Comparator Positive InputSPI1 Master Out Slave In; UART2 Port Map B Tx; Timer3 Port Map C Output 32 Bits or Lower 16 Bits; ADC Input 7/Comparator Positive InputSPI1 Serial Clock; UART2 Port Map B CTS; Timer0 Port Map C Input 32 Bits or Lower 16 Bits; ADC Input 8SPI1 Slave Select 0; UART2 Port Map B RTS; Timer0 Port Map C Output 32 Bits or Lower 16 Bits; ADC Input 9I2C2 Serial Clock; Timer1 Port Map C Input 32 Bits or Lower 16 Bits; ADC Input 10 I2C2 Serial Data; Timer1 Port Map C Output 32 Bits or Lower 16 Bits; ADC Input 11 Low-Power Timer1 Port Map A Input; ADC Trigger Port Map B; Timer0 Port Map C Input 32 Bits or Lower 16 BitsLow-Power Timer1 Port Map A Output; SPI0 Slave Select 3; Quadrature Decoder Index InputLow-Power UART0 CTS; UART0 Port Map B Rx; I2S0 Serial Data Output; Quadrature Decoder Capture InputLow-Power UART0 RTS; UART0 Port Map B Tx; I2S0 Left/Right Clock; Quadrature Decoder Match OutputLow-Power UART0 Rx; UART0 Port Map B CTS; I2S0 Bit Clock; Quadrature Decoder Direction OutputLow-Power UART0 Port Map A Tx; UART0 Port Map B Request to Send; I2S0 Port Map C Serial Data Input; Quadrature Decoder Error OutputUART1 Port Map A Receive; Timer3 Port Map C Input 32 Bits or Lower 16 Bits; External Clock InputUART1 Port Map A Transmit; SPI1 Port Map B Slave Select 0;Timer3 Port Map C Output 32 Bits or Lower 16 Bits; ADC Trigger Port Map DCM4 Rx Event Input; Timer2 Port Map C Input 32 Bits or Lower 16 BitsCM4 Tx Event Output; Timer2 Port Map C Output 32 Bits or Lower 16 BitsUART1 Port Map A Clear to Send; Timer3 Port Map C Input 32 Bits or Lower 16 BitsUART1 Port Map A Request to Send; Timer3 Port Map C Output 32 Bits or Lower 16 BitsTimer1 Port Map C Input 32 Bits or Lower 16 BitsSPI2 Port Map A Master In Slave Out; UART0 Port Map B Receive; Timer3 Port Map C Output 32 Bits or Lower 16 BitsSPI2 Port Map A Master Out Slave In; UART0 Port Map B Transmit; Timer3 Port Map C Input 32 Bits or Lower 16 Bits; Divided_Clock_OutputSPI2 Port Map A Serial Clock; UART0 Port Map B Clear to SendSPI2 Port Map A Slave Select 0; UART0 Port Map B Request to Send; Timer0 Port Map C Output 32 Bits or Lower 16 Bits; ADC Trigger Port Map DUART2 Port Map A ReceiveUART2 Port Map A TransmitUART2 Port Map A Clear to SendUART2 Port Map A Request to SendTimer1 Port Map C Output 32 Bits or Lower 16 Bits