In the DARWIN family, the MAX32672 is an ultra-low-power, cost-effective, highly integrated, and highly reliable 32-bit microcontroller enabling designs with complex sensor processing without compromising battery life. It combines a flexible and versatile power management unit with the powerful Arm® Cortex®-M4 processor with a floating-point unit (FPU). The MAX32672 also offers legacy designs an easy and cost-optimal upgrade path from 8- or 16-bit microcontrollers.
The device integrates 1MB of flash and 200KB of SRAM to accommodate application and sensor code. Error correction coding (ECC) is implemented on the entire flash, RAM, and cache to ensure extremely reliable code execution even in the harshest of environments. Brownout detection ensures proper operation during power-down and power-up events and unexpected supply transients. The flash is organized into two equal-size physical banks to allow execute-while-write and facilitate "live upgrades."
Multiple high-speed peripherals such as 3.4MHz I2C, 50MHz SPI, and UART are included to maximize communication bandwidth. In addition, a low-power UART (LPUART) is available for operation in the lowest power sleep modes to facilitate wake-up activity without any loss of data. A total of six timers with I/O capability are provided, including two low-power timers to enable pulse counting, capture/compare, and pulse-width modulation (PWM) generation, even in the lowest power sleep modes. An incremental/quadrature encoder interface with multiple diagnostics is included specifically for motor control applications. A 1Msps, 12-channel, 12-bit successive approximation register (SAR) ADC is integrated for the digitization of analog sensor signals or other analog measurements. Two low-power comparators, available in all low-power modes, allow energy-efficient monitoring and wake-up on external analog signals. An Elliptic Curve Digital Signature Algorithm (ECDSA)-based cryptographic secure bootloader is available in ROM. The device is available in a 5mm x 5mm, 40-pin TQFN-EP or 7mm x 7mm, 56-pin TQFN.
- High-Efficiency Microcontroller for Low-Power High-Reliability Devices
- Arm Cortex-M4 Processor with FPU up to 100MHz
- 1MB Dual-Bank Flash with Error Correction
- 200KB SRAM (160KB with ECC Enabled), Optionally Preserved in Lowest Power Modes
- EEPROM Emulation on Flash
- 16KB Unified Cache with ECC
- Resource Protection Unit (RPU) and Memory Protection Unit (MPU)
- Dual- or Single-Supply Operation, 1.7V to 3.6V
- Wide Operating Temperature: -40°C to +105°C
- Flexible Clocking Schemes
- Internal High-Speed 100MHz Oscillator
- Internal Low-Power 7.3728MHz and Ultra-Low-Power 80kHz Oscillators
- 16MHz–32MHz Oscillator, 32.768kHz Oscillator (External Crystal Required)
- External Clock Input for CPU, LPUART, LPTIMER
- Power Management Maximizes Uptime for Battery Applications
- 53.2μA/MHz ACTIVE at 0.9V up to 12MHz (CoreMark®)
- 61.5μA/MHz ACTIVE at 1.1V up to 100MHz
- 2.94μA Full Memory Retention Power in BACKUP Mode at VDD = 1.8V
- 350nA Ultra-Low-Power RTC at VDD = 1.8V
- Wake from LPUART or LPTMR
- Optimal Peripheral Mix Provides Platform Scalability
- Up to 42 General-Purpose I/O Pins
- Up to Three SPI Master/Slave (up to 50Mbps)
- Up to Three 4-Wire UART
- Up to Three I2C Master/Slave 3.4Mbps High Speed
- Up to Four 32-Bit Timers (TMR)
- Up to Two Low-Power 32-Bit Timers (LPTMR)
- One I2S Master/Slave for Digital Audio Interface
- One 12-Channel, 12-Bit, 1Msps SAR ADC with On-Die Temperature Sensor
- Security and Integrity
- Available ECDSA-Based Cryptographic Secure Bootloader in ROM
- Secure Loader Interface over UART
- AES-128/192/256 Hardware Acceleration Engine
- TRNG Compliant to SP800-90B
- Available ECDSA-Based Cryptographic Secure Bootloader in ROM
- Motion/Motor Control, Industrial Sensors
- Optical Communication Modules, Secure Radio Modem Controller
- Battery-Powered Medical Devices
Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
CoreMark is a registered trademark of EEMBC.19-101210; Rev 1; 1/22